Re: [PATCH v5 03/14] dmaengine: dw-edma: Add core quiesce operations

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] dw_edma_v0_core_off() fails to actually stop the DMA engines in HDMA compatibility mode because it relies on the non-existent ENGINE_EN register.
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--- Patch [3]: [PATCH v5 03/14] dmaengine: dw-edma: Add core quiesce operations ---
commit b74cbf35e0d2a9867f8a66e3ed4776b896fc6152
Author: Koichiro Den <den@valinux.co.jp>

dmaengine: dw-edma: Add core quiesce operations

This commit adds core operations to quiesce only the resources represented
by a dw-edma instance. It implements specific handling for unrolled eDMA
and HDMA compatibility mode.

> diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c
> --- a/drivers/dma/dw-edma/dw-edma-v0-core.c
> +++ b/drivers/dma/dw-edma/dw-edma-v0-core.c
[ ... ]
>  static void dw_edma_v0_core_off(struct dw_edma *dw)
>  {
>  	SET_BOTH_32(dw, int_mask,
>  		    EDMA_V0_DONE_INT_MASK | EDMA_V0_ABORT_INT_MASK);
>  	SET_BOTH_32(dw, int_clear,
>  		    EDMA_V0_DONE_INT_MASK | EDMA_V0_ABORT_INT_MASK);
>  	SET_BOTH_32(dw, engine_en, 0);
>  }

[Severity: High]
This isn't a bug introduced by this patch, but looking at
dw_edma_v0_core_off() in drivers/dma/dw-edma/dw-edma-v0-core.c, does it
fail to actually stop the DMA engines in HDMA compatibility mode?

Since HDMA compatibility mode does not implement the ENGINE_EN register (as
noted in the commit message and addressed in the new quiesce path), writing
0 to engine_en here doesn't seem to stop the channels.

If a user unbinds the driver or unloads the module, could the DMA controller
continue executing transfers into memory that is subsequently unmapped and
freed, since chX_pwr_en is never cleared during the remove path?

>  
> +static int dw_edma_v0_core_quiesce(struct dw_edma *dw)
> +{
> +	int ret = 0;
> +	int err;

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Sashiko AI review · https://sashiko.dev/#/patchset/20260717050308.2144108-1-den@valinux.co.jp?part=3