* [linux-next:master 7487/7584] drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:167:40: error: 'regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX' undeclared; did you mean 'regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX'?
@ 2026-07-19 22:25 kernel test robot
0 siblings, 0 replies; only message in thread
From: kernel test robot @ 2026-07-19 22:25 UTC (permalink / raw)
To: Dave Airlie; +Cc: oe-kbuild-all, Mark Brown
tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
head: 0718283ab28bc3907e10b61a6b4be6fefa1cbb2f
commit: 71105826f28ddbc4487994e0a0b1935fdb274bc9 [7487/7584] Merge branch 'drm-next' of https://gitlab.freedesktop.org/drm/kernel.git
config: x86_64-rhel-9.4-bpf (https://download.01.org/0day-ci/archive/20260720/202607200008.N3FpyJaT-lkp@intel.com/config)
compiler: gcc-14 (Debian 14.2.0-19) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260720/202607200008.N3FpyJaT-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202607200008.N3FpyJaT-lkp@intel.com/
Note: the linux-next/master HEAD 0718283ab28bc3907e10b61a6b4be6fefa1cbb2f builds fine.
It may have been fixed somewhere.
All error/warnings (new ones prefixed by >>):
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c: In function 'dcn42b_hpo_dp_stream_encoder_create':
>> drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:167:40: error: 'regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX' undeclared (first use in this function); did you mean 'regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX'?
167 | REG_STRUCT[id].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:149:46: note: in definition of macro 'BASE_INNER'
149 | #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:167:35: note: in expansion of macro 'BASE'
167 | REG_STRUCT[id].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42/dcn42_resource.h:314:17: note: in expansion of macro 'SRI_ARR'
314 | SRI_ARR(DP_SYM32_ENC_VID_CRC_CONTROL, DP_SYM32_ENC, id), \
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:354:9: note: in expansion of macro 'DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI'
354 | DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:1390:9: note: in expansion of macro 'hpo_dp_stream_encoder_reg_init'
1390 | hpo_dp_stream_encoder_reg_init(0),
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:167:40: note: each undeclared identifier is reported only once for each function it appears in
167 | REG_STRUCT[id].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:149:46: note: in definition of macro 'BASE_INNER'
149 | #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:167:35: note: in expansion of macro 'BASE'
167 | REG_STRUCT[id].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42/dcn42_resource.h:314:17: note: in expansion of macro 'SRI_ARR'
314 | SRI_ARR(DP_SYM32_ENC_VID_CRC_CONTROL, DP_SYM32_ENC, id), \
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:354:9: note: in expansion of macro 'DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI'
354 | DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:1390:9: note: in expansion of macro 'hpo_dp_stream_encoder_reg_init'
1390 | hpo_dp_stream_encoder_reg_init(0),
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:168:59: error: 'regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL' undeclared (first use in this function); did you mean 'regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL'?
168 | reg##block##id##_##reg_name
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42/dcn42_resource.h:314:17: note: in expansion of macro 'SRI_ARR'
314 | SRI_ARR(DP_SYM32_ENC_VID_CRC_CONTROL, DP_SYM32_ENC, id), \
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:354:9: note: in expansion of macro 'DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI'
354 | DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:1390:9: note: in expansion of macro 'hpo_dp_stream_encoder_reg_init'
1390 | hpo_dp_stream_encoder_reg_init(0),
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:167:40: error: 'regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX' undeclared (first use in this function); did you mean 'regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX'?
167 | REG_STRUCT[id].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:149:46: note: in definition of macro 'BASE_INNER'
149 | #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:167:35: note: in expansion of macro 'BASE'
167 | REG_STRUCT[id].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42/dcn42_resource.h:315:17: note: in expansion of macro 'SRI_ARR'
315 | SRI_ARR(DP_SYM32_ENC_HBLANK_CONTROL, DP_SYM32_ENC, id)
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:354:9: note: in expansion of macro 'DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI'
354 | DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:1390:9: note: in expansion of macro 'hpo_dp_stream_encoder_reg_init'
1390 | hpo_dp_stream_encoder_reg_init(0),
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:168:59: error: 'regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL' undeclared (first use in this function); did you mean 'regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL'?
168 | reg##block##id##_##reg_name
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42/dcn42_resource.h:315:17: note: in expansion of macro 'SRI_ARR'
315 | SRI_ARR(DP_SYM32_ENC_HBLANK_CONTROL, DP_SYM32_ENC, id)
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:354:9: note: in expansion of macro 'DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI'
354 | DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:1390:9: note: in expansion of macro 'hpo_dp_stream_encoder_reg_init'
1390 | hpo_dp_stream_encoder_reg_init(0),
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:25:
>> drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42/dcn42_resource.h:314:72: warning: left-hand operand of comma expression has no effect [-Wunused-value]
314 | SRI_ARR(DP_SYM32_ENC_VID_CRC_CONTROL, DP_SYM32_ENC, id), \
| ^
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:354:9: note: in expansion of macro 'DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI'
354 | DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:1390:9: note: in expansion of macro 'hpo_dp_stream_encoder_reg_init'
1390 | hpo_dp_stream_encoder_reg_init(0),
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:1390:42: warning: left-hand operand of comma expression has no effect [-Wunused-value]
1390 | hpo_dp_stream_encoder_reg_init(0),
| ^
>> drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:167:40: error: 'regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX' undeclared (first use in this function); did you mean 'regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX'?
167 | REG_STRUCT[id].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:149:46: note: in definition of macro 'BASE_INNER'
149 | #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:167:35: note: in expansion of macro 'BASE'
167 | REG_STRUCT[id].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42/dcn42_resource.h:314:17: note: in expansion of macro 'SRI_ARR'
314 | SRI_ARR(DP_SYM32_ENC_VID_CRC_CONTROL, DP_SYM32_ENC, id), \
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:354:9: note: in expansion of macro 'DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI'
354 | DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:1391:17: note: in expansion of macro 'hpo_dp_stream_encoder_reg_init'
1391 | hpo_dp_stream_encoder_reg_init(1),
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:168:59: error: 'regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL' undeclared (first use in this function); did you mean 'regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL'?
168 | reg##block##id##_##reg_name
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42/dcn42_resource.h:314:17: note: in expansion of macro 'SRI_ARR'
314 | SRI_ARR(DP_SYM32_ENC_VID_CRC_CONTROL, DP_SYM32_ENC, id), \
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:354:9: note: in expansion of macro 'DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI'
354 | DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:1391:17: note: in expansion of macro 'hpo_dp_stream_encoder_reg_init'
1391 | hpo_dp_stream_encoder_reg_init(1),
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:167:40: error: 'regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX' undeclared (first use in this function); did you mean 'regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX'?
167 | REG_STRUCT[id].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:149:46: note: in definition of macro 'BASE_INNER'
149 | #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:167:35: note: in expansion of macro 'BASE'
167 | REG_STRUCT[id].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42/dcn42_resource.h:315:17: note: in expansion of macro 'SRI_ARR'
315 | SRI_ARR(DP_SYM32_ENC_HBLANK_CONTROL, DP_SYM32_ENC, id)
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:354:9: note: in expansion of macro 'DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI'
354 | DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:1391:17: note: in expansion of macro 'hpo_dp_stream_encoder_reg_init'
1391 | hpo_dp_stream_encoder_reg_init(1),
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:168:59: error: 'regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL' undeclared (first use in this function); did you mean 'regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL'?
168 | reg##block##id##_##reg_name
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42/dcn42_resource.h:315:17: note: in expansion of macro 'SRI_ARR'
315 | SRI_ARR(DP_SYM32_ENC_HBLANK_CONTROL, DP_SYM32_ENC, id)
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:354:9: note: in expansion of macro 'DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI'
354 | DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:1391:17: note: in expansion of macro 'hpo_dp_stream_encoder_reg_init'
1391 | hpo_dp_stream_encoder_reg_init(1),
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42/dcn42_resource.h:314:72: warning: left-hand operand of comma expression has no effect [-Wunused-value]
314 | SRI_ARR(DP_SYM32_ENC_VID_CRC_CONTROL, DP_SYM32_ENC, id), \
| ^
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:354:9: note: in expansion of macro 'DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI'
354 | DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:1391:17: note: in expansion of macro 'hpo_dp_stream_encoder_reg_init'
1391 | hpo_dp_stream_encoder_reg_init(1),
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:1391:50: warning: left-hand operand of comma expression has no effect [-Wunused-value]
1391 | hpo_dp_stream_encoder_reg_init(1),
| ^
>> drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:167:40: error: 'regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX' undeclared (first use in this function); did you mean 'regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX'?
167 | REG_STRUCT[id].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:149:46: note: in definition of macro 'BASE_INNER'
149 | #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:167:35: note: in expansion of macro 'BASE'
167 | REG_STRUCT[id].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42/dcn42_resource.h:314:17: note: in expansion of macro 'SRI_ARR'
314 | SRI_ARR(DP_SYM32_ENC_VID_CRC_CONTROL, DP_SYM32_ENC, id), \
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:354:9: note: in expansion of macro 'DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI'
354 | DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:1392:17: note: in expansion of macro 'hpo_dp_stream_encoder_reg_init'
1392 | hpo_dp_stream_encoder_reg_init(2);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:168:59: error: 'regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL' undeclared (first use in this function); did you mean 'regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL'?
168 | reg##block##id##_##reg_name
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42/dcn42_resource.h:314:17: note: in expansion of macro 'SRI_ARR'
314 | SRI_ARR(DP_SYM32_ENC_VID_CRC_CONTROL, DP_SYM32_ENC, id), \
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:354:9: note: in expansion of macro 'DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI'
354 | DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:1392:17: note: in expansion of macro 'hpo_dp_stream_encoder_reg_init'
1392 | hpo_dp_stream_encoder_reg_init(2);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:167:40: error: 'regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX' undeclared (first use in this function); did you mean 'regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX'?
167 | REG_STRUCT[id].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:149:46: note: in definition of macro 'BASE_INNER'
149 | #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:167:35: note: in expansion of macro 'BASE'
167 | REG_STRUCT[id].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42/dcn42_resource.h:315:17: note: in expansion of macro 'SRI_ARR'
315 | SRI_ARR(DP_SYM32_ENC_HBLANK_CONTROL, DP_SYM32_ENC, id)
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:354:9: note: in expansion of macro 'DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI'
354 | DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:1392:17: note: in expansion of macro 'hpo_dp_stream_encoder_reg_init'
1392 | hpo_dp_stream_encoder_reg_init(2);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:168:59: error: 'regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL' undeclared (first use in this function); did you mean 'regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL'?
168 | reg##block##id##_##reg_name
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42/dcn42_resource.h:315:17: note: in expansion of macro 'SRI_ARR'
315 | SRI_ARR(DP_SYM32_ENC_HBLANK_CONTROL, DP_SYM32_ENC, id)
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:354:9: note: in expansion of macro 'DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI'
354 | DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:1392:17: note: in expansion of macro 'hpo_dp_stream_encoder_reg_init'
1392 | hpo_dp_stream_encoder_reg_init(2);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42/dcn42_resource.h:314:72: warning: left-hand operand of comma expression has no effect [-Wunused-value]
314 | SRI_ARR(DP_SYM32_ENC_VID_CRC_CONTROL, DP_SYM32_ENC, id), \
| ^
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:354:9: note: in expansion of macro 'DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI'
354 | DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:1392:17: note: in expansion of macro 'hpo_dp_stream_encoder_reg_init'
1392 | hpo_dp_stream_encoder_reg_init(2);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
vim +167 drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c
a3d3758b2ee159 Matthew Stewart 2026-05-17 152
a3d3758b2ee159 Matthew Stewart 2026-05-17 153 #define SR(reg_name) \
a3d3758b2ee159 Matthew Stewart 2026-05-17 154 REG_STRUCT.reg_name = BASE(reg##reg_name##_BASE_IDX) + \
a3d3758b2ee159 Matthew Stewart 2026-05-17 155 reg##reg_name
a3d3758b2ee159 Matthew Stewart 2026-05-17 156 #define SR_ARR(reg_name, id) \
a3d3758b2ee159 Matthew Stewart 2026-05-17 157 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + \
a3d3758b2ee159 Matthew Stewart 2026-05-17 158 reg##reg_name
a3d3758b2ee159 Matthew Stewart 2026-05-17 159 #define SR_ARR_INIT(reg_name, id, value) \
a3d3758b2ee159 Matthew Stewart 2026-05-17 160 REG_STRUCT[id].reg_name = value
a3d3758b2ee159 Matthew Stewart 2026-05-17 161
a3d3758b2ee159 Matthew Stewart 2026-05-17 162 #define SRI(reg_name, block, id) \
a3d3758b2ee159 Matthew Stewart 2026-05-17 163 REG_STRUCT.reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \
a3d3758b2ee159 Matthew Stewart 2026-05-17 164 reg##block##id##_##reg_name
a3d3758b2ee159 Matthew Stewart 2026-05-17 165
a3d3758b2ee159 Matthew Stewart 2026-05-17 166 #define SRI_ARR(reg_name, block, id) \
a3d3758b2ee159 Matthew Stewart 2026-05-17 @167 REG_STRUCT[id].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \
a3d3758b2ee159 Matthew Stewart 2026-05-17 @168 reg##block##id##_##reg_name
a3d3758b2ee159 Matthew Stewart 2026-05-17 169
:::::: The code at line 167 was first introduced by commit
:::::: a3d3758b2ee159a0985bc2f973a892200c2ab62b drm/amd/display: Add DCN42B DC resource files
:::::: TO: Matthew Stewart <matthew.stewart2@amd.com>
:::::: CC: Alex Deucher <alexander.deucher@amd.com>
--
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https://github.com/intel/lkp-tests/wiki
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2026-07-19 22:25 [linux-next:master 7487/7584] drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn42b/dcn42b_resource.c:167:40: error: 'regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX' undeclared; did you mean 'regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX'? kernel test robot
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