From: Shivansh Dhiman <shivansh.dhiman@amd.com>
To: <seanjc@google.com>, <pbonzini@redhat.com>, <tglx@linutronix.de>,
<mingo@redhat.com>
Cc: <kvm@vger.kernel.org>, <x86@kernel.org>, <yosry@kernel.org>,
<jmattson@google.com>, <thomas.lendacky@amd.com>,
<nikunj.dadhania@amd.com>, <ravi.bangoria@amd.com>,
<santosh.shukla@amd.com>, <shivansh.dhiman@amd.com>
Subject: [PATCH v4 0/5] KVM: SVM: Add Bus Lock Detect support and refactor LBRV
Date: Tue, 21 Jul 2026 05:05:55 +0000 [thread overview]
Message-ID: <20260721050600.87268-1-shivansh.dhiman@amd.com> (raw)
Bus Lock Detect (BLD) is a CPU feature that raises a #DB trap when an
instruction acquires a bus lock, allowing software to detect and act on bus
locks. It is enabled via MSR_IA32_DEBUGCTLMSR bit 2.
This series adds BLD support to AMD SVM and exposes the capability to the
guest. On AMD, MSR_IA32_DEBUGCTLMSR is virtualized only when LBR
Virtualization (LBRV) is enabled, so BLD depends on LBRV. Enabling that
dependency cleanly required first refactoring the LBRV handling, so the bulk
of the series is preparatory:
1: Refactor svm_update_lbrv() so new LBRV dependencies are trivial to add.
2: Sanitize V_LBR in the nested control cache and drop the now-redundant
X86_FEATURE_LBRV checks.
3: Use kvm_dr6_fixed() for nested DR6 so DR6_BUS_LOCK (bit 11) is forced
per guest CPUID instead of unconditionally.
4: Turn the DEBUGCTL_RESERVED_BITS macro into a per-vCPU helper (prep).
5: Add Bus Lock Detect support, wiring BLD to LBRV, gating
DEBUGCTLMSR_BUS_LOCK_DETECT on guest CPUID, and exposing the cap.
Regards,
Shivansh
---
Changelog:
v3 -> v4:
* Rename nested_vmcb12_has_lbrv() to nested_lbrv_enabled() (Yosry).
* Drop the redundant !lbrv check and the extra comment (Yosry).
* Spell out in the changelog what breaks when DR6_BUS_LOCK is forced to 1
(Nikunj).
* Make it a pure NFC macro-to-helper conversion, and move the
BUS_LOCK_DETECT gating to patch 5 (Nikunj).
* Fold in the DEBUGCTLMSR_BUS_LOCK_DETECT gating moved from patch 4.
* Collect Reviewed-by tags.
v2 -> v3:
* Reworked the single v2 patch into a prep series (patches 1-4) plus the
feature.
* Rewrite svm_update_lbrv() as 'if' statements so the BLD LBRV
dependency can be added cleanly (Yosry Ahmed).
* Sanitize V_LBR in the nested control cache like NP/GMET and drop the
redundant X86_FEATURE_LBRV checks (Yosry Ahmed).
* Use kvm_dr6_fixed() for nested DR6 instead of DR6_FIXED_1 | DR6_RTM.
* Compute DEBUGCTL reserved bits per-vCPU, gating BUS_LOCK_DETECT on
guest CPUID rather than a static macro.
v2 resend:
* Rebased on kvm-x86-next-2026.06.24.
v1 -> v2:
* Used guest_cpu_cap_has() instead of guest_cpuid_has().
v3: https://lore.kernel.org/kvm/20260709082953.69434-1-shivansh.dhiman@amd.com/
v2 Resend: https://lore.kernel.org/kvm/20260629081018.60618-1-shivansh.dhiman@amd.com/
v2: https://lore.kernel.org/kvm/20251121081228.426974-1-shivansh.dhiman@amd.com/
v1: https://lore.kernel.org/all/20240808062937.1149-5-ravi.bangoria@amd.com
---
Shivansh Dhiman (5):
KVM: SVM: Refactor svm_update_lbrv()
KVM: nSVM: Disable LBRV in nested control cache when unsupported
KVM: nSVM: Sanitize nested DR6 using kvm_dr6_fixed()
KVM: SVM: Turn DEBUGCTL_RESERVED_BITS into a helper
KVM: SVM: Add Bus Lock Detect support
arch/x86/kvm/regs.c | 3 ++-
arch/x86/kvm/regs.h | 1 +
arch/x86/kvm/svm/nested.c | 26 ++++++++++++++------------
arch/x86/kvm/svm/svm.c | 28 ++++++++++++++++++++--------
arch/x86/kvm/svm/svm.h | 13 +++++++++++--
5 files changed, 48 insertions(+), 23 deletions(-)
base-commit: 50406d35f5635e1cc523e61409d57e851b5f5df8
--
2.43.0
next reply other threads:[~2026-07-21 5:06 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-21 5:05 Shivansh Dhiman [this message]
2026-07-21 5:05 ` [PATCH v4 1/5] KVM: SVM: Refactor svm_update_lbrv() Shivansh Dhiman
2026-07-21 6:40 ` Nikunj A. Dadhania
2026-07-21 9:16 ` Shivansh Dhiman
2026-09-25 17:31 ` Sean Christopherson
2026-09-30 22:16 ` Shivansh Dhiman
2026-07-21 5:05 ` [PATCH v4 2/5] KVM: nSVM: Disable LBRV in nested control cache when unsupported Shivansh Dhiman
2026-07-21 5:05 ` [PATCH v4 3/5] KVM: nSVM: Sanitize nested DR6 using kvm_dr6_fixed() Shivansh Dhiman
2026-07-21 5:21 ` sashiko-bot
2026-09-25 17:26 ` Sean Christopherson
2026-09-25 17:39 ` Sean Christopherson
2026-09-30 22:16 ` Shivansh Dhiman
2026-07-21 5:05 ` [PATCH v4 4/5] KVM: SVM: Turn DEBUGCTL_RESERVED_BITS into a helper Shivansh Dhiman
2026-09-25 17:43 ` Sean Christopherson
2026-09-30 22:29 ` Shivansh Dhiman
2026-07-21 5:06 ` [PATCH v4 5/5] KVM: SVM: Add Bus Lock Detect support Shivansh Dhiman
2026-09-25 17:45 ` [PATCH v4 0/5] KVM: SVM: Add Bus Lock Detect support and refactor LBRV Sean Christopherson
2026-09-25 23:01 ` Sean Christopherson
2026-09-28 18:38 ` Shivansh Dhiman
2026-10-01 20:18 ` Shivansh Dhiman
2026-10-01 23:11 ` Sean Christopherson
2026-09-30 23:05 ` Shivansh Dhiman
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260721050600.87268-1-shivansh.dhiman@amd.com \
--to=shivansh.dhiman@amd.com \
--cc=jmattson@google.com \
--cc=kvm@vger.kernel.org \
--cc=mingo@redhat.com \
--cc=nikunj.dadhania@amd.com \
--cc=pbonzini@redhat.com \
--cc=ravi.bangoria@amd.com \
--cc=santosh.shukla@amd.com \
--cc=seanjc@google.com \
--cc=tglx@linutronix.de \
--cc=thomas.lendacky@amd.com \
--cc=x86@kernel.org \
--cc=yosry@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.