* [PATCH v2 1/5] dt-bindings: arm: google: Add dt bindings for frankel/blazer/mustang
2026-07-22 9:55 [PATCH v2 0/5] Add Laguna/Tensor G5 SoC and Frankel, Blazer & Mustang boards Peter Griffin
@ 2026-07-22 9:55 ` Peter Griffin
2026-07-22 9:55 ` [PATCH v2 2/5] dt-bindings: serial: snps-dw-apb-uart: Add "google,lga-uart" Peter Griffin
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Peter Griffin @ 2026-07-22 9:55 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
André Draszik, Tudor Ambarus, Greg Kroah-Hartman, Jiri Slaby,
Catalin Marinas, Will Deacon, Arnd Bergmann, Krzysztof Kozlowski,
Alexandre Belloni, Linus Walleij, Drew Fustini, Kees Cook,
Tony Luck, Guilherme G. Piccoli
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-serial, soc, Douglas Anderson, Juan Yescas, RD Babiera,
Brian Norris, William McVicker, kernel-team, Peter Griffin
Add binding documentation for Tensor G5 SoC (Laguna) which is referred
to in code as "lga" and three of the boards that use the Laguna SoC
Frankel (Pixel 10), Blazer (Pixel 10 Pro) and Mustang (Pixel 10 Pro XL).
Additionally update to use a more efficient and scalable way to express
the various names a SoC is known by.
Co-developed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
Changes in v2:
* Update ect rule as per Krysztof suggestion
* Remove all the pre-production variants (EVT, DVT etc)
* The equivalent patch in the previous submission is
https://lore.kernel.org/lkml/05c833f0-15bc-4a86-9ac4-daf835fe4393@kernel.org/
but this is now almost entirely different diff. I've added the
co-developed-by tag as I've kept the more efficient way to express
the names a SoC is known by.
---
Documentation/devicetree/bindings/arm/google.yaml | 48 ++++++++++++++---------
1 file changed, 29 insertions(+), 19 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/google.yaml b/Documentation/devicetree/bindings/arm/google.yaml
index 99961e5282e5..b5977e20f393 100644
--- a/Documentation/devicetree/bindings/arm/google.yaml
+++ b/Documentation/devicetree/bindings/arm/google.yaml
@@ -13,27 +13,16 @@ description: |
ARM platforms using SoCs designed by Google branded "Tensor" used in Pixel
devices.
- Currently upstream this is devices using "gs101" SoC which is found in Pixel
- 6, Pixel 6 Pro and Pixel 6a.
-
- Google have a few different names for the SoC:
- - Marketing name ("Tensor")
- - Codename ("Whitechapel")
- - SoC ID ("gs101")
- - Die ID ("S5P9845")
-
- Likewise there are a couple of names for the actual device
- - Marketing name ("Pixel 6")
- - Codename ("Oriole")
-
- Devicetrees should use the lowercased SoC ID and lowercased board codename,
- e.g. gs101 and gs101-oriole.
+ Currently upstream this is devices using gs101 SoC which is found in Pixel
+ 6, Pixel 6 Pro and Pixel 6a and Laguna SoC canonically referred to as lga
+ found in Pixel 10, Pixel 10 Pro and Pixel 10 Pro XL.
properties:
$nodename:
const: '/'
compatible:
oneOf:
+ # Google Tensor G1 AKA gs101 AKA whitechapel AKA Die ID S5P9845 boards
- description: Google Pixel 6 or 6 Pro (Oriole or Raven)
items:
- enum:
@@ -41,14 +30,35 @@ properties:
- google,gs101-raven
- const: google,gs101
- # Bootloader requires empty ect node to be present
+ # Google Tensor G5 AKA lga (laguna) SoC and boards
+ - description:
+ Google Pixel 10, 10 Pro, 10 Pro XL (Frankel, Blazer,
+ Mustang).
+ items:
+ - enum:
+ - google,lga-blazer
+ - google,lga-frankel
+ - google,lga-mustang
+ - const: google,lga
+
ect:
type: object
additionalProperties: false
-required:
- - ect
-
additionalProperties: true
+allOf:
+ # Bootloader requires empty ect node to be present
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: google,gs101
+ then:
+ required:
+ - ect
+ else:
+ properties:
+ ect: false
+
...
--
2.55.0.229.g6434b31f56-goog
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v2 2/5] dt-bindings: serial: snps-dw-apb-uart: Add "google,lga-uart"
2026-07-22 9:55 [PATCH v2 0/5] Add Laguna/Tensor G5 SoC and Frankel, Blazer & Mustang boards Peter Griffin
2026-07-22 9:55 ` [PATCH v2 1/5] dt-bindings: arm: google: Add dt bindings for frankel/blazer/mustang Peter Griffin
@ 2026-07-22 9:55 ` Peter Griffin
2026-07-22 9:55 ` [PATCH v2 3/5] arm64: dts: google: Add dts directory for Google-designed silicon Peter Griffin
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Peter Griffin @ 2026-07-22 9:55 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
André Draszik, Tudor Ambarus, Greg Kroah-Hartman, Jiri Slaby,
Catalin Marinas, Will Deacon, Arnd Bergmann, Krzysztof Kozlowski,
Alexandre Belloni, Linus Walleij, Drew Fustini, Kees Cook,
Tony Luck, Guilherme G. Piccoli
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-serial, soc, Douglas Anderson, Juan Yescas, RD Babiera,
Brian Norris, William McVicker, kernel-team, Peter Griffin,
Krzysztof Kozlowski
From: Douglas Anderson <dianders@chromium.org>
The Google Tensor G5 SoC (known as "laguna" and canonically written in
code as "lga") has a UART based on Designware IP. The UART appears to
work reasonably well, at least for serial console, with the existing
driver in Linux. Add a compatible for this UART based on the canonical
"lga" name for this SoC with a fallback to the existing
"snps,dw-apb-uart".
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
index 685c1eceb782..24589466a4be 100644
--- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
@@ -54,6 +54,7 @@ properties:
- anlogic,dr1v90-uart
- brcm,bcm11351-dw-apb-uart
- brcm,bcm21664-dw-apb-uart
+ - google,lga-uart
- rockchip,px30-uart
- rockchip,rk1808-uart
- rockchip,rk3036-uart
--
2.55.0.229.g6434b31f56-goog
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v2 3/5] arm64: dts: google: Add dts directory for Google-designed silicon
2026-07-22 9:55 [PATCH v2 0/5] Add Laguna/Tensor G5 SoC and Frankel, Blazer & Mustang boards Peter Griffin
2026-07-22 9:55 ` [PATCH v2 1/5] dt-bindings: arm: google: Add dt bindings for frankel/blazer/mustang Peter Griffin
2026-07-22 9:55 ` [PATCH v2 2/5] dt-bindings: serial: snps-dw-apb-uart: Add "google,lga-uart" Peter Griffin
@ 2026-07-22 9:55 ` Peter Griffin
2026-07-22 9:55 ` [PATCH v2 4/5] arm64: dts: google: Add initial dts for frankel/blazer/mustang Peter Griffin
2026-07-22 9:55 ` [PATCH v2 5/5] arm64: defconfig: enable Tensor G5 SoC family Peter Griffin
4 siblings, 0 replies; 7+ messages in thread
From: Peter Griffin @ 2026-07-22 9:55 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
André Draszik, Tudor Ambarus, Greg Kroah-Hartman, Jiri Slaby,
Catalin Marinas, Will Deacon, Arnd Bergmann, Krzysztof Kozlowski,
Alexandre Belloni, Linus Walleij, Drew Fustini, Kees Cook,
Tony Luck, Guilherme G. Piccoli
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-serial, soc, Douglas Anderson, Juan Yescas, RD Babiera,
Brian Norris, William McVicker, kernel-team, Peter Griffin
From: Douglas Anderson <dianders@chromium.org>
The first four Google Tensor SoCs were offshoots of Samsung Exynos
SoCs and their device trees were organized under the "exynos/google"
directory. Starting with the Google Tensor G5 SoC in Pixel 10 phones,
Google Tensor SoCs are now of Google's own design. Add a location in
the tree to store these device tree files.
Changes by Peter Griffin
* update config symbol help with at least 4 lines to avoid checkpatch
warning
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
MAINTAINERS | 1 +
arch/arm64/Kconfig.platforms | 8 ++++++++
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/google/Makefile | 1 +
4 files changed, 11 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index c61ef65d71ef..010d4de81a1b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11012,6 +11012,7 @@ F: Documentation/devicetree/bindings/phy/google,lga-usb-phy.yaml
F: Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-gen.yaml
F: Documentation/devicetree/bindings/usb/google,lga-dwc3.yaml
F: arch/arm64/boot/dts/exynos/google/
+F: arch/arm64/boot/dts/google/
F: drivers/clk/samsung/clk-gs101.c
F: drivers/phy/phy-google-usb.c
F: drivers/soc/samsung/gs101-pmu.c
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 72c812e76b0b..f83eb4ea878c 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -147,6 +147,14 @@ config ARCH_EXYNOS
help
This enables support for ARMv8 based Samsung Exynos SoC family.
+config ARCH_GOOGLE
+ bool "Google-Designed SoC family"
+ help
+ This enables support for Google Tensor SoCs starting at the
+ Google Tensor G5 (Laguna) found in Pixel 10 and later phones.
+ Tensor G1 to G4 are offshoots of the Exynos family and are
+ enabled via ARCH_EXYNOS.
+
config ARCH_K3
bool "Texas Instruments Inc. K3 multicore SoC architecture"
select SOC_TI
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 98ec8f1b76e4..566f0c863d55 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -18,6 +18,7 @@ subdir-y += cavium
subdir-y += cix
subdir-y += exynos
subdir-y += freescale
+subdir-y += google
subdir-y += hisilicon
subdir-y += intel
subdir-y += lg
diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/google/Makefile
new file mode 100644
index 000000000000..a6b187e2d631
--- /dev/null
+++ b/arch/arm64/boot/dts/google/Makefile
@@ -0,0 +1 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
--
2.55.0.229.g6434b31f56-goog
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 4/5] arm64: dts: google: Add initial dts for frankel/blazer/mustang
2026-07-22 9:55 [PATCH v2 0/5] Add Laguna/Tensor G5 SoC and Frankel, Blazer & Mustang boards Peter Griffin
` (2 preceding siblings ...)
2026-07-22 9:55 ` [PATCH v2 3/5] arm64: dts: google: Add dts directory for Google-designed silicon Peter Griffin
@ 2026-07-22 9:55 ` Peter Griffin
2026-07-22 10:04 ` sashiko-bot
2026-07-22 9:55 ` [PATCH v2 5/5] arm64: defconfig: enable Tensor G5 SoC family Peter Griffin
4 siblings, 1 reply; 7+ messages in thread
From: Peter Griffin @ 2026-07-22 9:55 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
André Draszik, Tudor Ambarus, Greg Kroah-Hartman, Jiri Slaby,
Catalin Marinas, Will Deacon, Arnd Bergmann, Krzysztof Kozlowski,
Alexandre Belloni, Linus Walleij, Drew Fustini, Kees Cook,
Tony Luck, Guilherme G. Piccoli
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-serial, soc, Douglas Anderson, Juan Yescas, RD Babiera,
Brian Norris, William McVicker, kernel-team, Peter Griffin
From: Douglas Anderson <dianders@chromium.org>
Add initial device trees for frankel (Pixel 10), blazer (Pixel 10
Pro) and mustang (Pixel 10 Pro XL). These device trees are enough to
boot to a serial prompt using an initramfs.
Currently only Laguna B0 silicon found in mass production phones is
officially supported. Further revisions such as A0 silicon and EVT
devices maybe added in the future if they are useful. As of today,
these device trees boot fine on EVT devices with A0 silicon.
Many things can be noted about these device trees:
1. Even newer versions of the bootloader will still error out if they
don't find a UFS node to add calibration data to. Until UFS is
supported, we provide a bogus UFS node for the bootloader. While
the bootloader could be changed, there is no long-term benefit
since eventually the device tree will have a UFS node.
2. They purposely choose to use the full 64-bit address and size cells
for the root node and the `soc@0` node. Although I haven't tested
the need for this, I presume the arguments made in
commit bede7d2dc8f3 ("arm64: dts: qcom: sdm845: Increase address
and size cells for soc") would apply here.
3. Though it looks as if the UART is never enabled, the bootloader
knows to enable the UART when the console is turned on. Baud rate
is configurable in the bootloader so is never hardcoded in the
device tree.
Changes by Peter Griffin:
- Remove dtbo overlay approach and add individual board dts
- Update to lga-pixel-common naming like gs101-pixel-common
- Reorder nodes alpha-numerically by the node name
- Add ramoops reserved-memory (tested with console=pstore)
- Add reserved-memory for bootloader & gsa logs
- Add reserved-memory for Android BootLoader ABL (used on Watchdog
reset to extract boolotader logs / parse breadcrumbs / ramdump etc).
- Add osc 38.4Mhz fixed-clock
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Co-developed-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
Changes in v2 (by Peter Griffin):
* Remove dtbo overlay approach and add individual board dts
* Update to lga-pixel-common naming like gs101-pixel-common
* Reorder nodes alpha-numerically by the node name
* Add ramoops reserved-memory (tested with console=pstore)
* Add reserved-memory for bootloader & gsa logs
* Add reserved-memory for Android BootLoader ABL (used on Watchdog
reset to extract boolotader logs / parse breadcrumbs / ramdump etc).
* Add osc 38.4Mhz fixed-clock
---
arch/arm64/boot/dts/google/Makefile | 5 +
arch/arm64/boot/dts/google/lga-blazer.dts | 15 +
arch/arm64/boot/dts/google/lga-frankel.dts | 16 +
arch/arm64/boot/dts/google/lga-mustang.dts | 15 +
arch/arm64/boot/dts/google/lga-pixel-common.dtsi | 23 ++
arch/arm64/boot/dts/google/lga.dtsi | 423 +++++++++++++++++++++++
6 files changed, 497 insertions(+)
diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/google/Makefile
index a6b187e2d631..4e833b2561e0 100644
--- a/arch/arm64/boot/dts/google/Makefile
+++ b/arch/arm64/boot/dts/google/Makefile
@@ -1 +1,6 @@
# SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+
+dtb-$(CONFIG_ARCH_GOOGLE) += \
+ lga-blazer.dtb \
+ lga-frankel.dtb \
+ lga-mustang.dtb
diff --git a/arch/arm64/boot/dts/google/lga-blazer.dts b/arch/arm64/boot/dts/google/lga-blazer.dts
new file mode 100644
index 000000000000..0894606624f8
--- /dev/null
+++ b/arch/arm64/boot/dts/google/lga-blazer.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Blazer Device Tree (Pixel 10 Pro)
+ *
+ * Copyright 2021-2023 Google LLC
+ */
+
+/dts-v1/;
+
+#include "lga-pixel-common.dtsi"
+
+/ {
+ model = "Blazer";
+ compatible = "google,lga-blazer", "google,lga";
+};
diff --git a/arch/arm64/boot/dts/google/lga-frankel.dts b/arch/arm64/boot/dts/google/lga-frankel.dts
new file mode 100644
index 000000000000..57df197a544f
--- /dev/null
+++ b/arch/arm64/boot/dts/google/lga-frankel.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Frankel Device Tree (Pixel 10)
+ *
+ * Copyright 2021-2023 Google LLC
+ */
+
+/dts-v1/;
+
+#include "lga-pixel-common.dtsi"
+
+/ {
+ model = "Frankel";
+ compatible = "google,lga-frankel", "google,lga";
+};
+
diff --git a/arch/arm64/boot/dts/google/lga-mustang.dts b/arch/arm64/boot/dts/google/lga-mustang.dts
new file mode 100644
index 000000000000..6ac0b5ef22ff
--- /dev/null
+++ b/arch/arm64/boot/dts/google/lga-mustang.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Mustang Device Tree (Pixel 10 Pro XL)
+ *
+ * Copyright 2021-2023 Google LLC
+ */
+
+/dts-v1/;
+
+#include "lga-pixel-common.dtsi"
+
+/ {
+ model = "Mustang";
+ compatible = "google,lga-mustang", "google,lga";
+};
diff --git a/arch/arm64/boot/dts/google/lga-pixel-common.dtsi b/arch/arm64/boot/dts/google/lga-pixel-common.dtsi
new file mode 100644
index 000000000000..57c318ab44c9
--- /dev/null
+++ b/arch/arm64/boot/dts/google/lga-pixel-common.dtsi
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Google Pixel 10 family common dtsi.
+ *
+ * Copyright 2024-2025 Google LLC.
+ */
+
+#include "lga.dtsi"
+
+&{/} {
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ aliases {
+ serial0 = "/soc@0/serial@db62000"; /* &lsion_cli16_uart */
+ ufs0 = "/ufs-placeholder"; /* &ufs - TODO "/soc@0/ufs@3c400000" */
+ };
+};
+
+&osc {
+ clock-frequency = <38400000>;
+};
diff --git a/arch/arm64/boot/dts/google/lga.dtsi b/arch/arm64/boot/dts/google/lga.dtsi
new file mode 100644
index 000000000000..343156a8c039
--- /dev/null
+++ b/arch/arm64/boot/dts/google/lga.dtsi
@@ -0,0 +1,423 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Google Tensor G5 (laguna) SoC rev B0
+ *
+ * Copyright 2024-2025 Google LLC.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+
+ osc: clock-38400000 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hayes_0: cpu@0 {
+ compatible = "arm,cortex-a520";
+ reg = <0x000>;
+
+ #cooling-cells = <2>;
+ capacity-dmips-mhz = <258>;
+ device_type = "cpu";
+ enable-method = "psci";
+ power-domain-names = "psci";
+ power-domains = <&cpu_pd0>;
+ };
+
+ hayes_1: cpu@100 {
+ compatible = "arm,cortex-a520";
+ reg = <0x100>;
+
+ #cooling-cells = <2>;
+ capacity-dmips-mhz = <258>;
+ device_type = "cpu";
+ enable-method = "psci";
+ power-domain-names = "psci";
+ power-domains = <&cpu_pd1>;
+ };
+
+ hunter_0: cpu@200 {
+ compatible = "arm,cortex-a725";
+ reg = <0x200>;
+
+ #cooling-cells = <2>;
+ capacity-dmips-mhz = <891>;
+ device_type = "cpu";
+ enable-method = "psci";
+ power-domain-names = "psci";
+ power-domains = <&cpu_pd2>;
+ };
+
+ hunter_1: cpu@300 {
+ compatible = "arm,cortex-a725";
+ reg = <0x300>;
+
+ #cooling-cells = <2>;
+ capacity-dmips-mhz = <891>;
+ device_type = "cpu";
+ enable-method = "psci";
+ power-domain-names = "psci";
+ power-domains = <&cpu_pd3>;
+ };
+
+ hunter_2: cpu@400 {
+ compatible = "arm,cortex-a725";
+ reg = <0x400>;
+
+ #cooling-cells = <2>;
+ capacity-dmips-mhz = <891>;
+ device_type = "cpu";
+ enable-method = "psci";
+ power-domain-names = "psci";
+ power-domains = <&cpu_pd4>;
+ };
+
+ hunter_3: cpu@500 {
+ compatible = "arm,cortex-a725";
+ reg = <0x500>;
+
+ #cooling-cells = <2>;
+ capacity-dmips-mhz = <891>;
+ device_type = "cpu";
+ enable-method = "psci";
+ power-domain-names = "psci";
+ power-domains = <&cpu_pd5>;
+ };
+
+ hunter_4: cpu@600 {
+ compatible = "arm,cortex-a725";
+ reg = <0x600>;
+
+ #cooling-cells = <2>;
+ capacity-dmips-mhz = <891>;
+ device_type = "cpu";
+ enable-method = "psci";
+ power-domain-names = "psci";
+ power-domains = <&cpu_pd6>;
+ };
+
+ hunterelp_0: cpu@700 {
+ compatible = "arm,cortex-x4";
+ reg = <0x700>;
+
+ #cooling-cells = <2>;
+ capacity-dmips-mhz = <1024>;
+ device_type = "cpu";
+ enable-method = "psci";
+ power-domain-names = "psci";
+ power-domains = <&cpu_pd7>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&hayes_0>;
+ };
+ core1 {
+ cpu = <&hayes_1>;
+ };
+ core2 {
+ cpu = <&hunter_0>;
+ };
+ core3 {
+ cpu = <&hunter_1>;
+ };
+ core4 {
+ cpu = <&hunter_2>;
+ };
+ core5 {
+ cpu = <&hunter_3>;
+ };
+ core6 {
+ cpu = <&hunter_4>;
+ };
+ core7 {
+ cpu = <&hunterelp_0>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ cpu_lit_c2: cpu-lit-c2 {
+ compatible = "arm,idle-state";
+
+ entry-latency-us = <132>;
+ exit-latency-us = <296>;
+ min-residency-us = <3610>;
+
+ idle-state-name = "cpu-lit-c2";
+ local-timer-stop;
+
+ arm,psci-suspend-param = <0x40000003>;
+ };
+
+ cpu_mid1_c2: cpu-mid1-c2 {
+ compatible = "arm,idle-state";
+
+ entry-latency-us = <130>;
+ exit-latency-us = <274>;
+ min-residency-us = <2720>;
+
+ idle-state-name = "cpu-mid1-c2";
+ local-timer-stop;
+
+ arm,psci-suspend-param = <0x40000003>;
+ };
+
+ cpu_mid2_c2: cpu-mid2-c2 {
+ compatible = "arm,idle-state";
+
+ entry-latency-us = <130>;
+ exit-latency-us = <274>;
+ min-residency-us = <2720>;
+
+ idle-state-name = "cpu-mid2-c2";
+ local-timer-stop;
+
+ arm,psci-suspend-param = <0x40000003>;
+ };
+
+ cpu_big_c2: cpu-big-c2 {
+ compatible = "arm,idle-state";
+
+ entry-latency-us = <110>;
+ exit-latency-us = <413>;
+ min-residency-us = <3950>;
+
+ idle-state-name = "cpu-big-c2";
+ local-timer-stop;
+
+ arm,psci-suspend-param = <0x40000003>;
+ };
+ };
+
+ domain-idle-states {
+ cluster_1_c3: cluster-1-c3 {
+ compatible = "domain-idle-state";
+
+ entry-latency-us = <325>;
+ exit-latency-us = <553>;
+ min-residency-us = <10000>;
+
+ idle-state-name = "cluster-1-c3";
+
+ arm,psci-suspend-param = <0x40010033>;
+ };
+
+ cluster_2_c3: cluster-2-c3 {
+ compatible = "domain-idle-state";
+
+ entry-latency-us = <345>;
+ exit-latency-us = <673>;
+ min-residency-us = <10000>;
+
+ idle-state-name = "cluster-2-c3";
+
+ arm,psci-suspend-param = <0x40010033>;
+ };
+
+ cluster_c4_deep: cluster-c4-deep {
+ compatible = "domain-idle-state";
+
+ entry-latency-us = <510>;
+ exit-latency-us = <1027>;
+ min-residency-us = <10000>;
+
+ idle-state-name = "cluster-c4-deep";
+
+ arm,psci-suspend-param = <0x40020333>;
+ };
+ };
+ };
+
+ memory: memory@80000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0x0 0x80000000 0x0 0x0>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+
+ cpu_pd0: power-domain-cpu0 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&cpu_lit_c2>;
+ power-domains = <&cpu_top_cl>;
+ };
+
+ cpu_pd1: power-domain-cpu1 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&cpu_lit_c2>;
+ power-domains = <&cpu_top_cl>;
+ };
+
+ cpu_pd2: power-domain-cpu2 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&cpu_mid1_c2>;
+ power-domains = <&cpucl1>;
+ };
+
+ cpu_pd3: power-domain-cpu3 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&cpu_mid1_c2>;
+ power-domains = <&cpucl1>;
+ };
+
+ cpu_pd4: power-domain-cpu4 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&cpu_mid1_c2>;
+ power-domains = <&cpucl1>;
+ };
+
+ cpu_pd5: power-domain-cpu5 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&cpu_mid2_c2>;
+ power-domains = <&cpucl2>;
+ };
+
+ cpu_pd6: power-domain-cpu6 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&cpu_mid2_c2>;
+ power-domains = <&cpucl2>;
+ };
+
+ cpu_pd7: power-domain-cpu7 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&cpu_big_c2>;
+ power-domains = <&cpucl2>;
+ };
+
+ cpucl1: power-domain-cluster-1 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&cluster_1_c3>;
+ power-domains = <&cpu_top_cl>;
+ };
+
+ cpucl2: power-domain-cluster-2 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&cluster_2_c3>;
+ power-domains = <&cpu_top_cl>;
+ };
+
+ cpu_top_cl: power-domain-top-cluster {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&cluster_c4_deep>;
+ };
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /*
+ * Store ramoops at a known location in DRAM, for access by the ABL
+ * following a crash-reset.
+ */
+ ramoops@95200000 {
+ compatible = "ramoops";
+ reg = <0x0 0x95200000 0x0 0x400000>;
+ console-size = <0x200000>;
+ pmsg-size = <0x200000>;
+ };
+
+ /* bootloader logs */
+ bldr_log_reserved: bldr-log-reserved@95600000 {
+ reg = <0x0 0x95600000 0x0 0x100000>;
+ no-map;
+ };
+
+ /* gsa logs */
+ gsa_reserved_log: gsa-reserved-log@a61b0000 {
+ reg = <0x0 0xa61b0000 0x0 0x00004000>;
+ no-map;
+ };
+
+ /* Android BootLoader (ABL) for ramdump/coredump processing */
+ abl@be000000 {
+ reg = <0x0 0xbe000000 0x0 0x1000000>;
+ no-map;
+ };
+ };
+
+ soc: soc@0 {
+ compatible = "simple-bus";
+ ranges = <0 0 0 0 0x10 0>;
+
+ dma-ranges = <0 0 0 0 0x10 0>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ gic: interrupt-controller@5880000 {
+ compatible = "arm,gic-v3";
+ reg = <0 0x05880000 0 0x10000>,
+ <0 0x05900000 0 0x200000>;
+ ranges;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ #interrupt-cells = <4>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ ppi-partitions {
+ ppi_cluster0: interrupt-partition-0 {
+ affinity = <&hayes_0 &hayes_1
+ &hunter_0 &hunter_1 &hunter_2
+ &hunter_3 &hunter_4>;
+ };
+
+ ppi_cluster1: interrupt-partition-1 {
+ affinity = <&hunterelp_0>;
+ };
+ };
+ };
+
+ lsion_cli16_uart: serial@db62000 {
+ compatible = "google,lga-uart", "snps,dw-apb-uart";
+ reg = <0 0x0db62000 0 0x100>;
+
+ clock-frequency = <200000000>;
+ interrupts = <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH 0>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts =
+ <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW) 0>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW) 0>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW) 0>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW) 0>;
+ };
+
+ /*
+ * The Pixel bootloader considers it a fatal error if it doesn't find
+ * a `ufs0` alias so it can add calibration data to the node. Until
+ * the proper UFS controller node is added under the SoC, create a
+ * temporary node to make the bootloader happy.
+ */
+ ufs: ufs-placeholder {
+ };
+};
--
2.55.0.229.g6434b31f56-goog
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v2 4/5] arm64: dts: google: Add initial dts for frankel/blazer/mustang
2026-07-22 9:55 ` [PATCH v2 4/5] arm64: dts: google: Add initial dts for frankel/blazer/mustang Peter Griffin
@ 2026-07-22 10:04 ` sashiko-bot
0 siblings, 0 replies; 7+ messages in thread
From: sashiko-bot @ 2026-07-22 10:04 UTC (permalink / raw)
To: Peter Griffin; +Cc: conor+dt, devicetree, robh
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Invalid use of GIC_CPU_MASK_SIMPLE(1) in a GICv3 interrupt specifier.
--
--- Patch [4]: [PATCH v2 4/5] arm64: dts: google: Add initial dts for frankel/blazer/mustang ---
commit 70ad3c51746ae3a6716daf5117667c85c92e2de0
Author: Douglas Anderson <dianders@chromium.org>
arm64: dts: google: Add initial dts for frankel/blazer/mustang
Add initial device trees for frankel (Pixel 10), blazer (Pixel 10
Pro) and mustang (Pixel 10 Pro XL). These device trees are enough to
boot to a serial prompt using an initramfs.
> diff --git a/arch/arm64/boot/dts/google/lga.dtsi b/arch/arm64/boot/dts/google/lga.dtsi
> new file mode 100644
> index 0000000000000..343156a8c0390
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/lga.dtsi
[ ... ]
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts =
> + <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW) 0>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW) 0>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW) 0>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW) 0>;
[Severity: Low]
Does this incorrectly use GIC_CPU_MASK_SIMPLE(1) for a GICv3 interrupt controller?
Since this device tree uses a GICv3 controller, the CPU mask in the flags cell
for PPI interrupts is deprecated. While the Linux kernel dynamically masks this
out, other operating systems or hypervisors consuming this device tree might
strictly evaluate it and incorrectly limit the per-CPU timer to CPU 0, or
reject the device tree outright.
> + };
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260722-contrib-pg-pixel10-initial-dts-v2-0-3abae9717feb@linaro.org?part=4
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 5/5] arm64: defconfig: enable Tensor G5 SoC family
2026-07-22 9:55 [PATCH v2 0/5] Add Laguna/Tensor G5 SoC and Frankel, Blazer & Mustang boards Peter Griffin
` (3 preceding siblings ...)
2026-07-22 9:55 ` [PATCH v2 4/5] arm64: dts: google: Add initial dts for frankel/blazer/mustang Peter Griffin
@ 2026-07-22 9:55 ` Peter Griffin
4 siblings, 0 replies; 7+ messages in thread
From: Peter Griffin @ 2026-07-22 9:55 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
André Draszik, Tudor Ambarus, Greg Kroah-Hartman, Jiri Slaby,
Catalin Marinas, Will Deacon, Arnd Bergmann, Krzysztof Kozlowski,
Alexandre Belloni, Linus Walleij, Drew Fustini, Kees Cook,
Tony Luck, Guilherme G. Piccoli
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-serial, soc, Douglas Anderson, Juan Yescas, RD Babiera,
Brian Norris, William McVicker, kernel-team, Peter Griffin
Enable the Google Tensor G5 (Laguna) SoC family in the arm64
defconfig. This SoC family is found in Pixel 10 and later phones.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index f4dfd0cc853c..930a4f27ee56 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -50,6 +50,7 @@ CONFIG_ARCH_BLAIZE=y
CONFIG_ARCH_BST=y
CONFIG_ARCH_CIX=y
CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_GOOGLE=y
CONFIG_ARCH_SPARX5=y
CONFIG_ARCH_K3=y
CONFIG_ARCH_LG1K=y
--
2.55.0.229.g6434b31f56-goog
^ permalink raw reply related [flat|nested] 7+ messages in thread