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From: Linu Cherian <linu.cherian@arm.com>
To: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>,
	Ryan Roberts <ryan.roberts@arm.com>,
	Kevin Brodsky <kevin.brodsky@arm.com>,
	Anshuman Khandual <anshuman.khandual@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, Linu Cherian <linu.cherian@arm.com>,
	Gavin Shan <gshan@redhat.com>
Subject: [PATCH v4 2/6] arm64: cputype: Add C1-Nano definitions
Date: Thu, 23 Jul 2026 10:10:29 +0530	[thread overview]
Message-ID: <20260723044034.2983651-3-linu.cherian@arm.com> (raw)
In-Reply-To: <20260723044034.2983651-1-linu.cherian@arm.com>

Add cputype definitions for C1-Nano.

The definition can be found in C1-Nano TRM,
https://developer.arm.com/documentation/107753/0002
as part of MIDR_EL1 bit descriptions.

This is going to be used in the bbml3 support list.

Reviewed-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Linu Cherian <linu.cherian@arm.com>
---
 arch/arm64/include/asm/cputype.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index e41fae46426b..1fa29616e586 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -100,6 +100,7 @@
 #define ARM_CPU_PART_CORTEX_A720AE	0xD89
 #define ARM_CPU_PART_C1_ULTRA		0xD8C
 #define ARM_CPU_PART_NEOVERSE_N3	0xD8E
+#define ARM_CPU_PART_C1_NANO		0xD8A
 #define ARM_CPU_PART_C1_PRO		0xD8B
 #define ARM_CPU_PART_C1_PREMIUM		0xD90
 
@@ -195,6 +196,7 @@
 #define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE)
 #define MIDR_C1_ULTRA MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_ULTRA)
 #define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
+#define MIDR_C1_NANO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_NANO)
 #define MIDR_C1_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PRO)
 #define MIDR_C1_PREMIUM MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PREMIUM)
 #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
-- 
2.43.0


  parent reply	other threads:[~2026-07-23  4:42 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-23  4:40 [PATCH v4 0/6] Add BBML3 cpu feature Linu Cherian
2026-07-23  4:40 ` [PATCH v4 1/6] arm64: cputype: Add Cortex-A520AE definitions Linu Cherian
2026-07-23  4:40 ` Linu Cherian [this message]
2026-07-23  4:40 ` [PATCH v4 3/6] arm64: cpufeature: Extend bbml2_noabort support list Linu Cherian
2026-07-23  7:26   ` Anshuman Khandual
2026-07-23  4:40 ` [PATCH v4 4/6] arm64: sysreg: Add BBM_3 Linu Cherian
2026-07-23  4:40 ` [PATCH v4 5/6] arm64: cpufeature: Rename BBML2_NOABORT as BBML3 Linu Cherian
2026-08-06 17:11   ` Will Deacon
2026-08-07  2:32     ` Linu Cherian
2026-07-23  4:40 ` [PATCH v4 6/6] arm64: cpufeature: Detect BBML3 based on ID_AA64MMFR2_EL1.BBM Linu Cherian
2026-07-31 15:13   ` Will Deacon
2026-08-03  3:52     ` Linu Cherian
2026-08-03  4:19       ` Anshuman Khandual
2026-08-04 13:51       ` Will Deacon
2026-08-05  9:20         ` Linu Cherian
2026-08-06 11:26           ` Will Deacon
2026-08-06 17:11 ` [PATCH v4 0/6] Add BBML3 cpu feature Will Deacon

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