[PATCH 0/5] mmc: tegra: Add Tegra238 and Tegra264 SDHCI support

[PATCH 0/5] mmc: tegra: Add Tegra238 and Tegra264 SDHCI support

[Prathamesh Shete]

Add SDHCI support for the Tegra238 and Tegra264 SoCs.

The series documents the compatible strings and adds the corresponding
SoC data. It also adds the Tegra264 SDMMC1 device tree node.

Prathamesh Shete (5):
  dt-bindings: mmc: tegra: Document Tegra238 SDHCI
  mmc: sdhci-tegra: Add Tegra238 SoC data
  dt-bindings: mmc: tegra: Document Tegra264 SDHCI
  mmc: sdhci-tegra: Add Tegra264 SoC data
  arm64: tegra: Add Tegra264 SDMMC1 device tree node

 .../bindings/mmc/nvidia,tegra20-sdhci.yaml    |  6 ++++
 arch/arm64/boot/dts/nvidia/tegra264.dtsi      | 34 +++++++++++++++++++
 drivers/mmc/host/sdhci-tegra.c                | 30 ++++++++++++++++
 3 files changed, 70 insertions(+)

-- 
2.17.1

[PATCH 1/5] dt-bindings: mmc: tegra: Document Tegra238 SDHCI

[Prathamesh Shete]

Add the compatible string for the SDHCI block found on the Tegra238 SoC.

Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
---
 .../devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml         | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
index 72987f0326a1..0926a0cb892e 100644
--- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
+++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
@@ -39,6 +39,10 @@ properties:
               - nvidia,tegra234-sdhci
           - const: nvidia,tegra186-sdhci
 
+      - items:
+          - const: nvidia,tegra238-sdhci
+          - const: nvidia,tegra194-sdhci
+
   reg:
     maxItems: 1
 
-- 
2.17.1

[PATCH 2/5] mmc: sdhci-tegra: Add Tegra238 SoC data

[Prathamesh Shete]

Add a new SoC data structure for Tegra238 platforms and register the
nvidia,tegra238-sdhci compatible string. Configure the supported
features and tap delay values for the Tegra238 SDHCI controller.

Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
---
 drivers/mmc/host/sdhci-tegra.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 221e48b59f48..5fd900ff9eb5 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -1572,7 +1572,22 @@ static const struct sdhci_tegra_soc_data soc_data_tegra234 = {
 	.max_tap_delay = 111,
 };
 
+static const struct sdhci_tegra_soc_data soc_data_tegra238 = {
+	.pdata = &sdhci_tegra186_pdata,
+	.dma_mask = DMA_BIT_MASK(39),
+	.nvquirks = NVQUIRK_NEEDS_PAD_CONTROL |
+		    NVQUIRK_HAS_PADCALIB |
+		    NVQUIRK_DIS_CARD_CLK_CONFIG_TAP |
+		    NVQUIRK_ENABLE_SDR50 |
+		    NVQUIRK_ENABLE_SDR104 |
+		    NVQUIRK_PROGRAM_STREAMID |
+		    NVQUIRK_HAS_TMCLK,
+	.min_tap_delay = 95,
+	.max_tap_delay = 111,
+};
+
 static const struct of_device_id sdhci_tegra_dt_match[] = {
+	{ .compatible = "nvidia,tegra238-sdhci", .data = &soc_data_tegra238 },
 	{ .compatible = "nvidia,tegra234-sdhci", .data = &soc_data_tegra234 },
 	{ .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 },
 	{ .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 },
-- 
2.17.1

[PATCH 3/5] dt-bindings: mmc: tegra: Document Tegra264 SDHCI

[Prathamesh Shete]

Add the compatible string for the SDHCI block found on the Tegra264 SoC.

Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
---
 .../devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml         | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
index 0926a0cb892e..3cac067c7c98 100644
--- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
+++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
@@ -40,7 +40,9 @@ properties:
           - const: nvidia,tegra186-sdhci
 
       - items:
-          - const: nvidia,tegra238-sdhci
+          - enum:
+              - nvidia,tegra238-sdhci
+              - nvidia,tegra264-sdhci
           - const: nvidia,tegra194-sdhci
 
   reg:
-- 
2.17.1

[PATCH 4/5] mmc: sdhci-tegra: Add Tegra264 SoC data

[Prathamesh Shete]

Add a new SoC data structure for Tegra264 platforms and register the
nvidia,tegra264-sdhci compatible string. Configure the supported
features and tap delay values for the Tegra264 SDHCI controller.

Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
---
 drivers/mmc/host/sdhci-tegra.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 5fd900ff9eb5..5c5efb62d7ec 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -1572,6 +1572,20 @@ static const struct sdhci_tegra_soc_data soc_data_tegra234 = {
 	.max_tap_delay = 111,
 };
 
+static const struct sdhci_tegra_soc_data soc_data_tegra264 = {
+	.pdata = &sdhci_tegra186_pdata,
+	.dma_mask = DMA_BIT_MASK(39),
+	.nvquirks = NVQUIRK_NEEDS_PAD_CONTROL |
+		    NVQUIRK_HAS_PADCALIB |
+		    NVQUIRK_DIS_CARD_CLK_CONFIG_TAP |
+		    NVQUIRK_ENABLE_SDR50 |
+		    NVQUIRK_ENABLE_SDR104 |
+		    NVQUIRK_PROGRAM_STREAMID |
+		    NVQUIRK_HAS_TMCLK,
+	.min_tap_delay = 95,
+	.max_tap_delay = 111,
+};
+
 static const struct sdhci_tegra_soc_data soc_data_tegra238 = {
 	.pdata = &sdhci_tegra186_pdata,
 	.dma_mask = DMA_BIT_MASK(39),
@@ -1587,6 +1601,7 @@ static const struct sdhci_tegra_soc_data soc_data_tegra238 = {
 };
 
 static const struct of_device_id sdhci_tegra_dt_match[] = {
+	{ .compatible = "nvidia,tegra264-sdhci", .data = &soc_data_tegra264 },
 	{ .compatible = "nvidia,tegra238-sdhci", .data = &soc_data_tegra238 },
 	{ .compatible = "nvidia,tegra234-sdhci", .data = &soc_data_tegra234 },
 	{ .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 },
-- 
2.17.1

[PATCH 5/5] arm64: tegra: Add Tegra264 SDMMC1 device tree node

[Prathamesh Shete]

Add device tree node for the Tegra264 SDMMC1 instance.

Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra264.dtsi | 34 ++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
index 2d2cb1a3d95c..f1eafb6a3970 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
@@ -3631,6 +3631,40 @@
 			status = "disabled";
 		};
 
+		mmc@c570000 {
+			compatible = "nvidia,tegra264-sdhci", "nvidia,tegra194-sdhci";
+			reg = <0x00 0x0c570000 0x0 0x10000>;
+			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&bpmp TEGRA264_CLK_SDMMC1>,
+				 <&bpmp TEGRA264_CLK_SDMMC_LEGACY_TM>;
+			clock-names = "sdhci", "tmclk";
+			assigned-clocks = <&bpmp TEGRA264_CLK_SDMMC1>,
+					  <&bpmp TEGRA264_CLK_PLLC4_MUXED>;
+			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLC4_MUXED>,
+						 <&bpmp TEGRA264_CLK_PLLC4_OUT0>;
+			resets = <&bpmp TEGRA264_RESET_SDMMC1>;
+			reset-names = "sdhci";
+			interconnects = <&mc TEGRA264_MEMORY_CLIENT_SDMMC0R &emc>,
+					<&mc TEGRA264_MEMORY_CLIENT_SDMMC0W &emc>;
+			interconnect-names = "dma-mem", "write";
+			iommus = <&smmu2 TEGRA264_SID_SDMMC0>;
+			nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
+			nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>;
+			nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
+			nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
+			nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
+			nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
+			nvidia,default-tap = <0x6>;
+			nvidia,default-trim = <0x0>;
+			sd-uhs-sdr12;
+			sd-uhs-sdr25;
+			sd-uhs-sdr50;
+			sd-uhs-sdr104;
+			mmc-hs200-1_8v;
+			dma-coherent;
+			status = "disabled";
+		};
+
 		i2c0: i2c@c630000 {
 			compatible = "nvidia,tegra264-i2c";
 			reg = <0x00 0x0c630000 0x0 0x10000>;
-- 
2.17.1

Re: [PATCH 5/5] arm64: tegra: Add Tegra264 SDMMC1 device tree node

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Missing pinctrl configuration for SDMMC1 pad voltage switching.
--

--- Patch [5]: [PATCH 5/5] arm64: tegra: Add Tegra264 SDMMC1 device tree node ---
commit 9ce1cc837d5e304cb5792016306e46a502dddf18
Author: Prathamesh Shete <pshete@nvidia.com>

arm64: tegra: Add Tegra264 SDMMC1 device tree node

Add device tree node for the Tegra264 SDMMC1 instance.

> diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> index 2d8e7e37830ff..8b1f45b5c4cb9 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> @@ -3631,6 +3631,40 @@ i2c16: i2c@c430000 {
>  			status = "disabled";
>  		};
>  
> +		mmc@c570000 {
> +			compatible = "nvidia,tegra264-sdhci", "nvidia,tegra194-sdhci";
> +			reg = <0x00 0x0c570000 0x0 0x10000>;

[Severity: High]
Does this node need pinctrl configurations to support the declared UHS modes?

This node defines UHS modes (e.g., sd-uhs-sdr104) later in the block but lacks
the corresponding pinctrl-names and pinctrl-x properties required by the
sdhci-tegra driver to safely switch pad voltages.

Because the Tegra264 SDHCI host driver declares NVQUIRK_NEEDS_PAD_CONTROL,
missing these properties causes tegra_sdhci_init_pinctrl_info() to fail during
probe. This skips assigning the sdhci_tegra_start_signal_voltage_switch
callback.

When the MMC core later attempts to switch to 1.8V for the declared UHS modes,
it will fall back to the default sdhci_start_signal_voltage_switch()
implementation. This modifies the controller registers but fails to adjust the
actual Tegra SoC pad driver voltages.

Could this leave the physical pads stuck at 3.3V while negotiating 1.8V,
potentially causing signal integrity issues, data corruption, or hardware
damage when an SD card capable of UHS modes is inserted?

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260724075700.714261-1-pshete@nvidia.com?part=5