All of lore.kernel.org
 help / color / mirror / Atom feed
From: sashiko-bot@kernel.org
To: "Qiang Yu" <qiang.yu@oss.qualcomm.com>
Cc: robh@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org,
	olteanv@gmail.com, linux-phy@lists.infradead.org,
	vkoul@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v7 3/6] arm64: dts: qcom: glymur: Add PCIe3 PHY and PCIe3a controller nodes
Date: Fri, 24 Jul 2026 10:15:56 +0000	[thread overview]
Message-ID: <20260724101556.9A1961F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260724-glymur_linkmode_0724-v7-3-65c8469c6b65@oss.qualcomm.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Hardcoded literal '0' is used instead of the 'GIC_SPI' macro in the interrupt-map property.
--

--- Patch [3]: [PATCH v7 3/6] arm64: dts: qcom: glymur: Add PCIe3 PHY and PCIe3a controller nodes ---
commit dd1c15a3b44d0578ffea10fd2c542a6e374a70d7
Author: Qiang Yu <qiang.yu@oss.qualcomm.com>

arm64: dts: qcom: glymur: Add PCIe3 PHY and PCIe3a controller nodes

This commit adds the PCIe3 PHY and PCIe3a controller nodes to the glymur
device tree. It models the shared PHY as a single provider, updates the GCC
pipe clock parent array, and defines the PCIe3a PCI node.

> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi

[ ... ]

> @@ -3722,6 +3780,280 @@ pcie3b_port0_ep: endpoint {
>  			};
>  		};
>  
> +		pcie3a: pcie@1c10000 {

[ ... ]

> +			interrupts = <GIC_SPI 948 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 949 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 942 IRQ_TYPE_LEVEL_HIGH>;

[ ... ]

> +			#interrupt-cells = <1>;
> +			interrupt-map-mask = <0 0 0 0x7>;
> +			interrupt-map = <0 0 0 1 &intc 0 0 0 848 IRQ_TYPE_LEVEL_HIGH>,

[Severity: Low]
This isn't a bug, but is it intended to use the literal '0' here for the
parent interrupt specifier type instead of the 'GIC_SPI' macro? The
'interrupts' property just above uses 'GIC_SPI', so using the macro here might
improve consistency and readability.

> +					<0 0 0 2 &intc 0 0 0 849 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 3 &intc 0 0 0 850 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 4 &intc 0 0 0 851 IRQ_TYPE_LEVEL_HIGH>;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260724-glymur_linkmode_0724-v7-0-65c8469c6b65@oss.qualcomm.com?part=3

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

WARNING: multiple messages have this Message-ID (diff)
From: sashiko-bot@kernel.org
To: "Qiang Yu" <qiang.yu@oss.qualcomm.com>
Cc: robh@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org,
	olteanv@gmail.com, linux-phy@lists.infradead.org,
	vkoul@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v7 3/6] arm64: dts: qcom: glymur: Add PCIe3 PHY and PCIe3a controller nodes
Date: Fri, 24 Jul 2026 10:15:56 +0000	[thread overview]
Message-ID: <20260724101556.9A1961F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260724-glymur_linkmode_0724-v7-3-65c8469c6b65@oss.qualcomm.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Hardcoded literal '0' is used instead of the 'GIC_SPI' macro in the interrupt-map property.
--

--- Patch [3]: [PATCH v7 3/6] arm64: dts: qcom: glymur: Add PCIe3 PHY and PCIe3a controller nodes ---
commit dd1c15a3b44d0578ffea10fd2c542a6e374a70d7
Author: Qiang Yu <qiang.yu@oss.qualcomm.com>

arm64: dts: qcom: glymur: Add PCIe3 PHY and PCIe3a controller nodes

This commit adds the PCIe3 PHY and PCIe3a controller nodes to the glymur
device tree. It models the shared PHY as a single provider, updates the GCC
pipe clock parent array, and defines the PCIe3a PCI node.

> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi

[ ... ]

> @@ -3722,6 +3780,280 @@ pcie3b_port0_ep: endpoint {
>  			};
>  		};
>  
> +		pcie3a: pcie@1c10000 {

[ ... ]

> +			interrupts = <GIC_SPI 948 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 949 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 942 IRQ_TYPE_LEVEL_HIGH>;

[ ... ]

> +			#interrupt-cells = <1>;
> +			interrupt-map-mask = <0 0 0 0x7>;
> +			interrupt-map = <0 0 0 1 &intc 0 0 0 848 IRQ_TYPE_LEVEL_HIGH>,

[Severity: Low]
This isn't a bug, but is it intended to use the literal '0' here for the
parent interrupt specifier type instead of the 'GIC_SPI' macro? The
'interrupts' property just above uses 'GIC_SPI', so using the macro here might
improve consistency and readability.

> +					<0 0 0 2 &intc 0 0 0 849 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 3 &intc 0 0 0 850 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 4 &intc 0 0 0 851 IRQ_TYPE_LEVEL_HIGH>;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260724-glymur_linkmode_0724-v7-0-65c8469c6b65@oss.qualcomm.com?part=3

  reply	other threads:[~2026-07-24 10:15 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-24 10:01 [PATCH v7 0/6] Add QMP PCIe Multi-PHY support Qiang Yu
2026-07-24 10:01 ` Qiang Yu
2026-07-24 10:01 ` [PATCH v7 1/6] dt-bindings: phy: qcom: Add Glymur QMP PCIe multiple link-mode PHY Qiang Yu
2026-07-24 10:01   ` Qiang Yu
2026-07-24 10:01 ` [PATCH v7 2/6] phy: qcom: qmp-pcie: Add QMP PCIe Multi-PHY driver Qiang Yu
2026-07-24 10:01   ` Qiang Yu
2026-07-24 10:12   ` sashiko-bot
2026-07-24 10:12     ` sashiko-bot
2026-07-24 10:01 ` [PATCH v7 3/6] arm64: dts: qcom: glymur: Add PCIe3 PHY and PCIe3a controller nodes Qiang Yu
2026-07-24 10:01   ` Qiang Yu
2026-07-24 10:15   ` sashiko-bot [this message]
2026-07-24 10:15     ` sashiko-bot
2026-07-24 10:01 ` [PATCH v7 4/6] arm64: dts: qcom: glymur-crd: Add PHY supplies for pcie3_phy Qiang Yu
2026-07-24 10:01   ` Qiang Yu
2026-07-24 10:01 ` [PATCH v7 5/6] arm64: dts: qcom: mahua: Replace pcie3a/pcie3_phy with dedicated pcie3b_phy Qiang Yu
2026-07-24 10:01   ` Qiang Yu
2026-07-24 10:01 ` [PATCH v7 6/6] arm64: dts: qcom: mahua-crd: Add PHY supplies for pcie3b_phy Qiang Yu
2026-07-24 10:01   ` Qiang Yu

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20260724101556.9A1961F000E9@smtp.kernel.org \
    --to=sashiko-bot@kernel.org \
    --cc=conor+dt@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=linux-phy@lists.infradead.org \
    --cc=neil.armstrong@linaro.org \
    --cc=olteanv@gmail.com \
    --cc=qiang.yu@oss.qualcomm.com \
    --cc=robh@kernel.org \
    --cc=sashiko-reviews@lists.linux.dev \
    --cc=vkoul@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.