[PATCH] ARM: dts: BCM5301X: fix PCIe controller 2 second interrupt

[PATCH] ARM: dts: BCM5301X: fix PCIe controller 2 second interrupt

[Rosen Penev]

PCIe controller 2 has interrupts 0-4 mapping to GIC SPI 138-142. The
mapping for interrupt 1 was incorrectly set to 138 due to a copy-paste
error. Fix it to 139.

Assisted-by: opencode:big-pickle
Signed-off-by: Rosen Penev <rosenp@gmail.com>
---
 arch/arm/boot/dts/broadcom/bcm-ns.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/broadcom/bcm-ns.dtsi b/arch/arm/boot/dts/broadcom/bcm-ns.dtsi
index 392a25713669..bd52de0faa3e 100644
--- a/arch/arm/boot/dts/broadcom/bcm-ns.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm-ns.dtsi
@@ -141,7 +141,7 @@ axi@18000000 {
 
 			/* PCIe Controller 2 */
 			<0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
-			<0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00014000 1 &gic GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 			<0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 			<0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 			<0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-- 
2.55.0

Re: [PATCH] ARM: dts: BCM5301X: fix PCIe controller 2 second interrupt

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The commit message inaccurately claims that PCIe controller 2 has interrupts 0-4 mapping to GIC SPI 138-142, omitting the mapping for interrupt 5 to GIC SPI 143.
--

--- Patch [1]: [PATCH] ARM: dts: BCM5301X: fix PCIe controller 2 second interrupt ---
commit 61d1b598a171b93e277ba55c095b09aad8291a33
Author: Rosen Penev <rosenp@gmail.com>

ARM: dts: BCM5301X: fix PCIe controller 2 second interrupt

This commit corrects the interrupt mapping for PCIe controller 2 in the
device tree. It updates interrupt 1 to map to GIC SPI 139, fixing a
copy-paste error where it was previously mapped to 138.

> PCIe controller 2 has interrupts 0-4 mapping to GIC SPI 138-142. The
> mapping for interrupt 1 was incorrectly set to 138 due to a copy-paste
> error. Fix it to 139.

[Severity: Medium]
Is this description accurate regarding the number of mapped interrupts?

Looking at arch/arm/boot/dts/broadcom/bcm-ns.dtsi, the device tree explicitly
maps interrupts 0 through 5 for PCIe controller 2:

			/* PCIe Controller 2 */
			<0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
			<0x00014000 1 &gic GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
			<0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
			<0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
			<0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
			<0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,

Could the commit message be updated to mention that interrupts 0-5 map to
GIC SPI 138-143?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260725215722.9323-1-rosenp@gmail.com?part=1

Re: [PATCH] ARM: dts: BCM5301X: fix PCIe controller 2 second interrupt

[Rosen Penev]

On Sat, Jul 25, 2026 at 3:00 PM <sashiko-bot@kernel.org> wrote:
>
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] The commit message inaccurately claims that PCIe controller 2 has interrupts 0-4 mapping to GIC SPI 138-142, omitting the mapping for interrupt 5 to GIC SPI 143.
Quite pedantic.
> --
>
> --- Patch [1]: [PATCH] ARM: dts: BCM5301X: fix PCIe controller 2 second interrupt ---
> commit 61d1b598a171b93e277ba55c095b09aad8291a33
> Author: Rosen Penev <rosenp@gmail.com>
>
> ARM: dts: BCM5301X: fix PCIe controller 2 second interrupt
>
> This commit corrects the interrupt mapping for PCIe controller 2 in the
> device tree. It updates interrupt 1 to map to GIC SPI 139, fixing a
> copy-paste error where it was previously mapped to 138.
>
> > PCIe controller 2 has interrupts 0-4 mapping to GIC SPI 138-142. The
> > mapping for interrupt 1 was incorrectly set to 138 due to a copy-paste
> > error. Fix it to 139.
>
> [Severity: Medium]
> Is this description accurate regarding the number of mapped interrupts?
>
> Looking at arch/arm/boot/dts/broadcom/bcm-ns.dtsi, the device tree explicitly
> maps interrupts 0 through 5 for PCIe controller 2:
>
>                         /* PCIe Controller 2 */
>                         <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
>                         <0x00014000 1 &gic GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
>                         <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
>                         <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
>                         <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
>                         <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
>
> Could the commit message be updated to mention that interrupts 0-5 map to
> GIC SPI 138-143?
>
> --
> Sashiko AI review · https://sashiko.dev/#/patchset/20260725215722.9323-1-rosenp@gmail.com?part=1