From: sashiko-bot@kernel.org
To: "Bibo Mao" <maobibo@loongson.cn>
Cc: kvm@vger.kernel.org
Subject: Re: [PATCH 6/6] LoongArch: KVM: Enable separate vmid feature
Date: Mon, 27 Jul 2026 07:40:08 +0000 [thread overview]
Message-ID: <20260727074008.953AA1F00A3D@smtp.kernel.org> (raw)
In-Reply-To: <20260727072109.2151675-7-maobibo@loongson.cn>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] CSR_GTLBC_USEVMID is not cleared when virtualization is disabled, leaving the CPU in an inconsistent state and leaking hypervisor state to the underlying hardware.
--
--- Patch [6]: [PATCH 6/6] LoongArch: KVM: Enable separate vmid feature ---
commit 255d457e2558ae0a9e092e8d465e179d08390542
Author: Bibo Mao <maobibo@loongson.cn>
LoongArch: KVM: Enable separate vmid feature
With CSR GTLBC shortname for Guest TLB Control Register, separate vmid
feature will be enabled if bit 14 CSR_GTLBC_USEVMID is set. Enable
this feature if cpu_has_guestid is true when LVZ is enabled and the LVZ
version is 2.
> diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c
> index 86b1af823e2b4..43f5b40786f24 100644
> --- a/arch/loongarch/kvm/main.c
> +++ b/arch/loongarch/kvm/main.c
> @@ -365,7 +365,7 @@ int kvm_arch_enable_virtualization_cpu(void)
> write_csr_gcfg(0);
> write_csr_gstat(0);
> write_csr_gintc(0);
> - clear_csr_gtlbc(CSR_GTLBC_USETGID | CSR_GTLBC_TOTI);
> + clear_csr_gtlbc(CSR_GTLBC_USETGID | CSR_GTLBC_TOTI | CSR_GTLBC_USEVMID);
[Severity: Medium]
Since this clears the newly added CSR_GTLBC_USEVMID bit during initialization,
should it also be cleared in kvm_arch_disable_virtualization_cpu() when
hardware virtualization is disabled?
Currently, kvm_arch_disable_virtualization_cpu() only clears the prior bits:
arch/loongarch/kvm/main.c:kvm_arch_disable_virtualization_cpu() {
write_csr_gcfg(0);
write_csr_gstat(0);
write_csr_gintc(0);
clear_csr_gtlbc(CSR_GTLBC_USETGID | CSR_GTLBC_TOTI);
...
}
Does missing this bit during teardown leave the CPU in an inconsistent state
by retaining KVM-specific control bits in the Guest TLB Control register?
This might cause issues during CPU offline/online cycles, kexec into a
different kernel, or when another hypervisor initializes the CPU.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260727072109.2151675-1-maobibo@loongson.cn?part=6
prev parent reply other threads:[~2026-07-27 7:40 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-27 7:21 [PATCH 0/6] LoongArch: KVM: Add separate vmid support Bibo Mao
2026-07-27 7:21 ` [PATCH 1/6] LoongArch: KVM: Add vmid support for stage2 MMU Bibo Mao
2026-07-27 7:21 ` [PATCH 2/6] LoongArch: KVM: Add separate vCPU and VM id update function Bibo Mao
2026-07-27 7:21 ` [PATCH 3/6] LoongArch: KVM: Add separate vmid feature support Bibo Mao
2026-07-27 7:42 ` sashiko-bot
2026-07-27 7:21 ` [PATCH 4/6] LoongArch: KVM: implement vmid updating logic Bibo Mao
2026-07-27 7:49 ` sashiko-bot
2026-07-27 7:21 ` [PATCH 5/6] LoongArch: KVM: Add remote tlb flushing support Bibo Mao
2026-07-27 7:46 ` sashiko-bot
2026-07-27 7:21 ` [PATCH 6/6] LoongArch: KVM: Enable separate vmid feature Bibo Mao
2026-07-27 7:40 ` sashiko-bot [this message]
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