* [PATCH v2 0/3] CPM6 Channel Separation Support
@ 2026-07-28 9:17 Devendra K Verma
0 siblings, 0 replies; 2+ messages in thread
From: Devendra K Verma @ 2026-07-28 9:17 UTC (permalink / raw)
To: mani, vkoul, frank.li
Cc: den, dmaengine, linux-pci, linux-kernel, michal.simek, devverma
'Designware Cores PCI Express DM Controller - Reference
Manual', section 3.2.34.3, VSEC for DEVICE INFORMATION supports
the channel separation mechanisms. Basically, the HDMA IP allows
the user to configure the separation between DMA channel
registers and retrieve it via the VSEC capability mentioned
above.
In order to use the VSEC functionality following changes have
been made:
o For Xilinx IP alone, the macros declared are made device
name agnostic to expand the usage of macros for similar
functionality.
o Utilize the existing VSEC implementation to retrieve
the channel separation and translate it to correct size.
o Modify the structs and functions to calculate correct
DMA channel register base using the channel, direction
and channel separation selected.
Devendra K Verma (3):
dmaengine: dw-edma: Make Xilinx Macros Dev Name Agnostic
dmaengine: dw-edma: Enable Chan Separation via VSEC
dmaengine: dw-edma: Add changes to support Channel Separation
drivers/dma/dw-edma/dw-edma-pcie.c | 81 ++++++++++++--------
drivers/dma/dw-edma/dw-hdma-v0-core.c | 23 +++---
drivers/dma/dw-edma/dw-hdma-v0-debugfs.c | 17 ++--
drivers/dma/dw-edma/dw-hdma-v0-regs.h | 10 ---
drivers/pci/controller/dwc/pcie-designware.c | 1 +
include/linux/dma/edma.h | 1 +
6 files changed, 72 insertions(+), 61 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 2+ messages in thread
* [PATCH v2 0/3] CPM6 Channel Separation Support
@ 2026-07-28 9:17 Devendra K Verma
0 siblings, 0 replies; 2+ messages in thread
From: Devendra K Verma @ 2026-07-28 9:17 UTC (permalink / raw)
To: mani, vkoul, frank.li
Cc: den, dmaengine, linux-pci, linux-kernel, michal.simek, devverma
'Designware Cores PCI Express DM Controller - Reference
Manual', section 3.2.34.3, VSEC for DEVICE INFORMATION supports
the channel separation mechanisms. Basically, the HDMA IP allows
the user to configure the separation between DMA channel
registers and retrieve it via the VSEC capability mentioned
above.
In order to use the VSEC functionality following changes have
been made:
o For Xilinx IP alone, the macros declared are made device
name agnostic to expand the usage of macros for similar
functionality.
o Utilize the existing VSEC implementation to retrieve
the channel separation and translate it to correct size.
o Modify the structs and functions to calculate correct
DMA channel register base using the channel, direction
and channel separation selected.
Devendra K Verma (3):
dmaengine: dw-edma: Make Xilinx Macros Dev Name Agnostic
dmaengine: dw-edma: Enable Chan Separation via VSEC
dmaengine: dw-edma: Add changes to support Channel Separation
drivers/dma/dw-edma/dw-edma-pcie.c | 81 ++++++++++++--------
drivers/dma/dw-edma/dw-hdma-v0-core.c | 23 +++---
drivers/dma/dw-edma/dw-hdma-v0-debugfs.c | 17 ++--
drivers/dma/dw-edma/dw-hdma-v0-regs.h | 10 ---
drivers/pci/controller/dwc/pcie-designware.c | 1 +
include/linux/dma/edma.h | 1 +
6 files changed, 72 insertions(+), 61 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 2+ messages in thread
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