Re: [PATCH 03/13] clk: samsung: exynos8855: add block top and peric clock support

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The UART DBG PCLK gate clock is incorrectly assigned the functional (baud rate) clock as its parent instead of the NOC peripheral bus clock.
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--- Patch [3]: [PATCH 03/13] clk: samsung: exynos8855: add block top and peric clock support ---
commit 749ec1f523b7d61993f27762dded3422cad15aae
Author: raghav.s <raghav.s@samsung.com>

clk: samsung: exynos8855: add block top and peric clock support

This commit adds support for the CMU_TOP and CMU_PERIC clock domains
on the Exynos 8855 SoC. It registers compatible strings and cmu_info
data to provide clocks for these blocks.

> diff --git a/drivers/clk/samsung/clk-exynos8855.c b/drivers/clk/samsung/clk-exynos8855.c
> new file mode 100644
> index 0000000000000..93528f0077a4f
> --- /dev/null
> +++ b/drivers/clk/samsung/clk-exynos8855.c

[ ... ]

> +static const struct samsung_gate_clock peric_gate_clks[] __initconst = {
> +	/* System will hang if this critical clock is gated */
> +	GATE(CLK_GOUT_CMU_PERIC_IPCLKPORT_PCLK, "gout_cmu_peric_ipclkport_pclk",
> +	     "dout_clkcmu_peric_nocp",
> +	     CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_CMU_PERIC_IPCLKPORT_PCLK,
> +	     21, CLK_IS_CRITICAL, 0),
> +	GATE(CLK_GOUT_SYSREG_PERIC_IPCLKPORT_PCLK, "gout_sysreg_peric_ipclkport_pclk",
> +	     "dout_clkcmu_peric_nocp",
> +	     CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_SYSREG_PERIC_IPCLKPORT_PCLK,
> +	     21, 0, 0),
> +	/* System will hang if this critical clock is gated */
> +	GATE(CLK_GOUT_UART_DBG_PERIC_IPCLKPORT_PCLK, "gout_uart_dbg_peric_ipclkport_pclk",
> +	     "dout_clkcmu_peric_uart_dbg",
> +	     CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_UART_DBG_IPCLKPORT_PCLK,
> +	     21, CLK_IS_CRITICAL, 0),

[Severity: High]
Is dout_clkcmu_peric_uart_dbg the correct parent clock for the UART DBG
PCLK here? 

It looks like this assigns the functional baud rate clock to the PCLK,
whereas other IPCLKPORTs use the dout_clkcmu_peric_nocp peripheral bus
clock.

If register accesses to the UART_DBG block are clocked by the functional
clock rather than the NOC peripheral bus clock, could changing the UART baud
rate improperly scale the APB bus clock for this IP? This might lead to bus
stalls or system hangs when the kernel scales the baud rate or transitions
states, especially since this clock is marked as CLK_IS_CRITICAL.

> +	GATE(CLK_GOUT_USI_PERIC_IPCLKPORT_PCLK, "gout_usi_peric_ipclkport_pclk",
> +	     "dout_clkcmu_peric_nocp",
> +	     CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_USI00_USI_IPCLKPORT_PCLK,
> +	     21, 0, 0),
> +};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260728121111.2077860-1-raghav.s@samsung.com?part=3