From: "Bingyu.Xian" <shanbeeyoo@gmail.com>
To: Anup Patel <anup@brainfault.org>
Cc: Atish Patra <atish.patra@linux.dev>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Quan Zhou <zhouquan@iscas.ac.cn>,
stable@vger.kernel.org
Subject: [PATCH v3 0/3] RISC-V: KVM: G-stage fault path fix and cleanup
Date: Wed, 29 Jul 2026 20:07:30 +0800 [thread overview]
Message-ID: <20260729120733.829457-1-shanbeeyoo@gmail.com> (raw)
In-Reply-To: <20260729075230.743030-1-shanbeeyoo@gmail.com>
Three small changes to the RISC-V G-stage page fault path, sent as
separate patches per review feedback.
1/3: Treat -EEXIST from kvm_riscv_gstage_map_page() as a quiet
success, aligning RISC-V with x86 and arm64. Real bug fix;
Fixes: 9d05c1fee837, Cc: stable.
2/3: vma_pageshift: short -> unsigned int. No-functional-change
type cleanup in preparation for sharing a common
struct kvm_page_fault across architectures.
3/3: Widen the G-stage fault address to gpa_t end to end -- the
local in gstage_page_fault(), the (gpa_t) cast before the <<2
shift, and the fault_addr parameters of kvm_riscv_vcpu_mmio_load/
store(). This completes the RV32 34-bit GPA fix that v2 only
half-addressed: v2 widened the local and cast the shift, but the
address was still narrowed to 32 bits at the MMIO handler call
(unsigned long parameter), aliasing accesses above 4 GB into the
low 4 GB. The handlers' internal uses (run->mmio.phys_addr is
__u64, kvm_io_bus_read/write() take gpa_t) are already 64-bit.
Also in preparation for sharing a common struct kvm_page_fault.
No functional change on RV64. Not Cc'd to stable: RV32 KVM is
unsupported and this is untested at runtime.
Changes since v2 [1]:
- Split into separate patches per feedback.
- Completed the fault_addr widening v2 left half-done: widened the
kvm_riscv_vcpu_mmio_load/store() fault_addr parameters to gpa_t so
the 34-bit address is not truncated at the MMIO handler call.
The KVM_MEM_USERFAULT port that motivated this cleanup will follow as a
separate RFC.
[1] https://lore.kernel.org/kvm/20260729075230.743030-1-shanbeeyoo@gmail.com/
Bingyu.Xian (3):
RISC-V: KVM: Treat -EEXIST from G-stage map as success
RISC-V: KVM: Use unsigned int for vma_pageshift
RISC-V: KVM: Widen G-stage fault address to gpa_t
arch/riscv/include/asm/kvm_vcpu_insn.h | 4 ++--
arch/riscv/kvm/mmu.c | 8 +++++---
arch/riscv/kvm/vcpu_exit.c | 5 +++--
arch/riscv/kvm/vcpu_insn.c | 4 ++--
4 files changed, 12 insertions(+), 9 deletions(-)
--
2.54.0
--
kvm-riscv mailing list
kvm-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/kvm-riscv
WARNING: multiple messages have this Message-ID (diff)
From: "Bingyu.Xian" <shanbeeyoo@gmail.com>
To: Anup Patel <anup@brainfault.org>
Cc: Atish Patra <atish.patra@linux.dev>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Quan Zhou <zhouquan@iscas.ac.cn>,
stable@vger.kernel.org
Subject: [PATCH v3 0/3] RISC-V: KVM: G-stage fault path fix and cleanup
Date: Wed, 29 Jul 2026 20:07:30 +0800 [thread overview]
Message-ID: <20260729120733.829457-1-shanbeeyoo@gmail.com> (raw)
In-Reply-To: <20260729075230.743030-1-shanbeeyoo@gmail.com>
Three small changes to the RISC-V G-stage page fault path, sent as
separate patches per review feedback.
1/3: Treat -EEXIST from kvm_riscv_gstage_map_page() as a quiet
success, aligning RISC-V with x86 and arm64. Real bug fix;
Fixes: 9d05c1fee837, Cc: stable.
2/3: vma_pageshift: short -> unsigned int. No-functional-change
type cleanup in preparation for sharing a common
struct kvm_page_fault across architectures.
3/3: Widen the G-stage fault address to gpa_t end to end -- the
local in gstage_page_fault(), the (gpa_t) cast before the <<2
shift, and the fault_addr parameters of kvm_riscv_vcpu_mmio_load/
store(). This completes the RV32 34-bit GPA fix that v2 only
half-addressed: v2 widened the local and cast the shift, but the
address was still narrowed to 32 bits at the MMIO handler call
(unsigned long parameter), aliasing accesses above 4 GB into the
low 4 GB. The handlers' internal uses (run->mmio.phys_addr is
__u64, kvm_io_bus_read/write() take gpa_t) are already 64-bit.
Also in preparation for sharing a common struct kvm_page_fault.
No functional change on RV64. Not Cc'd to stable: RV32 KVM is
unsupported and this is untested at runtime.
Changes since v2 [1]:
- Split into separate patches per feedback.
- Completed the fault_addr widening v2 left half-done: widened the
kvm_riscv_vcpu_mmio_load/store() fault_addr parameters to gpa_t so
the 34-bit address is not truncated at the MMIO handler call.
The KVM_MEM_USERFAULT port that motivated this cleanup will follow as a
separate RFC.
[1] https://lore.kernel.org/kvm/20260729075230.743030-1-shanbeeyoo@gmail.com/
Bingyu.Xian (3):
RISC-V: KVM: Treat -EEXIST from G-stage map as success
RISC-V: KVM: Use unsigned int for vma_pageshift
RISC-V: KVM: Widen G-stage fault address to gpa_t
arch/riscv/include/asm/kvm_vcpu_insn.h | 4 ++--
arch/riscv/kvm/mmu.c | 8 +++++---
arch/riscv/kvm/vcpu_exit.c | 5 +++--
arch/riscv/kvm/vcpu_insn.c | 4 ++--
4 files changed, 12 insertions(+), 9 deletions(-)
--
2.54.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: "Bingyu.Xian" <shanbeeyoo@gmail.com>
To: Anup Patel <anup@brainfault.org>
Cc: Atish Patra <atish.patra@linux.dev>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Quan Zhou <zhouquan@iscas.ac.cn>,
stable@vger.kernel.org
Subject: [PATCH v3 0/3] RISC-V: KVM: G-stage fault path fix and cleanup
Date: Wed, 29 Jul 2026 20:07:30 +0800 [thread overview]
Message-ID: <20260729120733.829457-1-shanbeeyoo@gmail.com> (raw)
In-Reply-To: <20260729075230.743030-1-shanbeeyoo@gmail.com>
Three small changes to the RISC-V G-stage page fault path, sent as
separate patches per review feedback.
1/3: Treat -EEXIST from kvm_riscv_gstage_map_page() as a quiet
success, aligning RISC-V with x86 and arm64. Real bug fix;
Fixes: 9d05c1fee837, Cc: stable.
2/3: vma_pageshift: short -> unsigned int. No-functional-change
type cleanup in preparation for sharing a common
struct kvm_page_fault across architectures.
3/3: Widen the G-stage fault address to gpa_t end to end -- the
local in gstage_page_fault(), the (gpa_t) cast before the <<2
shift, and the fault_addr parameters of kvm_riscv_vcpu_mmio_load/
store(). This completes the RV32 34-bit GPA fix that v2 only
half-addressed: v2 widened the local and cast the shift, but the
address was still narrowed to 32 bits at the MMIO handler call
(unsigned long parameter), aliasing accesses above 4 GB into the
low 4 GB. The handlers' internal uses (run->mmio.phys_addr is
__u64, kvm_io_bus_read/write() take gpa_t) are already 64-bit.
Also in preparation for sharing a common struct kvm_page_fault.
No functional change on RV64. Not Cc'd to stable: RV32 KVM is
unsupported and this is untested at runtime.
Changes since v2 [1]:
- Split into separate patches per feedback.
- Completed the fault_addr widening v2 left half-done: widened the
kvm_riscv_vcpu_mmio_load/store() fault_addr parameters to gpa_t so
the 34-bit address is not truncated at the MMIO handler call.
The KVM_MEM_USERFAULT port that motivated this cleanup will follow as a
separate RFC.
[1] https://lore.kernel.org/kvm/20260729075230.743030-1-shanbeeyoo@gmail.com/
Bingyu.Xian (3):
RISC-V: KVM: Treat -EEXIST from G-stage map as success
RISC-V: KVM: Use unsigned int for vma_pageshift
RISC-V: KVM: Widen G-stage fault address to gpa_t
arch/riscv/include/asm/kvm_vcpu_insn.h | 4 ++--
arch/riscv/kvm/mmu.c | 8 +++++---
arch/riscv/kvm/vcpu_exit.c | 5 +++--
arch/riscv/kvm/vcpu_insn.c | 4 ++--
4 files changed, 12 insertions(+), 9 deletions(-)
--
2.54.0
next prev parent reply other threads:[~2026-07-29 12:07 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-29 7:07 [PATCH] RISC-V: KVM: Fix spurious -EEXIST and clean up gstage fault path types Bingyu.Xian
2026-07-29 7:07 ` Bingyu.Xian
2026-07-29 7:07 ` Bingyu.Xian
2026-07-29 7:17 ` sashiko-bot
2026-07-29 7:52 ` [PATCH v2] " Bingyu.Xian
2026-07-29 7:52 ` Bingyu.Xian
2026-07-29 7:52 ` Bingyu.Xian
2026-07-29 8:03 ` sashiko-bot
2026-07-29 12:07 ` Bingyu.Xian [this message]
2026-07-29 12:07 ` [PATCH v3 0/3] RISC-V: KVM: G-stage fault path fix and cleanup Bingyu.Xian
2026-07-29 12:07 ` Bingyu.Xian
2026-07-29 12:07 ` [PATCH v3 1/3] RISC-V: KVM: Treat -EEXIST from G-stage map as success Bingyu.Xian
2026-07-29 12:07 ` Bingyu.Xian
2026-07-29 12:07 ` Bingyu.Xian
2026-07-29 12:07 ` [PATCH v3 2/3] RISC-V: KVM: Use unsigned int for vma_pageshift Bingyu.Xian
2026-07-29 12:07 ` Bingyu.Xian
2026-07-29 12:07 ` Bingyu.Xian
2026-07-29 12:07 ` [PATCH v3 3/3] RISC-V: KVM: Widen G-stage fault address to gpa_t Bingyu.Xian
2026-07-29 12:07 ` Bingyu.Xian
2026-07-29 12:07 ` Bingyu.Xian
2026-07-29 8:05 ` [PATCH] RISC-V: KVM: Fix spurious -EEXIST and clean up gstage fault path types Anup Patel
2026-07-29 8:05 ` Anup Patel
2026-07-29 8:05 ` Anup Patel
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