* [PATCH] target/riscv: prevent abrupt abortion on unassigned value write to tdata
@ 2026-07-29 23:00 Abhigyan Kumar
2026-08-14 13:14 ` abh
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Abhigyan Kumar @ 2026-07-29 23:00 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, Alistair Francis, Weiwei Li, Daniel Henrique Barboza,
Liu Zhiwei, Chao Liu, Palmer Dabbelt, Abhigyan Kumar
tdata_csr_write is approachable by guest programs. In case of unassigned
values written to a tdata CSR in debug mode, the switch-case falls
through straight to default causing an immediate abort. The risc-v spec
says:
All tdata registers follow write-any-read-legal semantics. If a debugger
writes an unsupported configuration, the register will read back a value
that is supported (which may simply be a disabled trigger). This means
that a debugger must always read back values it writes to tdata
registers, unless it already knows what is supported.
This fix correctly ensures that the WARL behaviour of tdata CSRs.
Fixes: a42bd001 ("target/riscv: debug: Determine the trigger type from
tdata1.type")
Signed-off-by: Abhigyan Kumar <314abh@gmail.com>
---
target/riscv/tcg/debug.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/tcg/debug.c b/target/riscv/tcg/debug.c
index 3c0fe7010..ae493235d 100644
--- a/target/riscv/tcg/debug.c
+++ b/target/riscv/tcg/debug.c
@@ -913,7 +913,8 @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val)
trigger_type);
break;
default:
- g_assert_not_reached();
+ qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d is unassigned\n",
+ trigger_type);
}
}
--
2.55.0
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH] target/riscv: prevent abrupt abortion on unassigned value write to tdata
2026-07-29 23:00 [PATCH] target/riscv: prevent abrupt abortion on unassigned value write to tdata Abhigyan Kumar
@ 2026-08-14 13:14 ` abh
2026-09-03 4:31 ` Alistair Francis
2026-09-03 4:57 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: abh @ 2026-08-14 13:14 UTC (permalink / raw)
To: qemu-riscv
Cc: qemu-devel, chao.liu, zhiwei_liu, daniel.barboza, liwei1518,
alistair.francis, palmer
On 7/30/26 4:30 AM, Abhigyan Kumar wrote:
> tdata_csr_write is approachable by guest programs. In case of unassigned
> values written to a tdata CSR in debug mode, the switch-case falls
> through straight to default causing an immediate abort. The risc-v spec
> says:
>
> All tdata registers follow write-any-read-legal semantics. If a debugger
> writes an unsupported configuration, the register will read back a value
> that is supported (which may simply be a disabled trigger). This means
> that a debugger must always read back values it writes to tdata
> registers, unless it already knows what is supported.
>
> This fix correctly ensures that the WARL behaviour of tdata CSRs.
>
> Fixes: a42bd001 ("target/riscv: debug: Determine the trigger type from
> tdata1.type")
> Signed-off-by: Abhigyan Kumar <314abh@gmail.com>
> ---
> target/riscv/tcg/debug.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/tcg/debug.c b/target/riscv/tcg/debug.c
> index 3c0fe7010..ae493235d 100644
> --- a/target/riscv/tcg/debug.c
> +++ b/target/riscv/tcg/debug.c
> @@ -913,7 +913,8 @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val)
> trigger_type);
> break;
> default:
> - g_assert_not_reached();
> + qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d is unassigned\n",
> + trigger_type);
> }
> }
>
Greetings. It has been over two weeks since I submitted this patch. It's
my humble request to know the status of the review/acceptance for my
patch. Please inform me about any required amends.
Thank you for your patience and attention.
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] target/riscv: prevent abrupt abortion on unassigned value write to tdata
2026-07-29 23:00 [PATCH] target/riscv: prevent abrupt abortion on unassigned value write to tdata Abhigyan Kumar
2026-08-14 13:14 ` abh
@ 2026-09-03 4:31 ` Alistair Francis
2026-09-03 4:57 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2026-09-03 4:31 UTC (permalink / raw)
To: 314abh@gmail.com, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, chao.liu.zevorn@gmail.com,
daniel.barboza@oss.qualcomm.com, palmer@dabbelt.com,
liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com
On Thu, 2026-07-30 at 04:30 +0530, Abhigyan Kumar wrote:
> tdata_csr_write is approachable by guest programs. In case of
> unassigned
> values written to a tdata CSR in debug mode, the switch-case falls
> through straight to default causing an immediate abort. The risc-v
> spec
> says:
>
> All tdata registers follow write-any-read-legal semantics. If a
> debugger
> writes an unsupported configuration, the register will read back
> a value
> that is supported (which may simply be a disabled trigger). This
> means
> that a debugger must always read back values it writes to tdata
> registers, unless it already knows what is supported.
>
> This fix correctly ensures that the WARL behaviour of tdata CSRs.
>
> Fixes: a42bd001 ("target/riscv: debug: Determine the trigger type
> from
> tdata1.type")
> Signed-off-by: Abhigyan Kumar <314abh@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/tcg/debug.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/tcg/debug.c b/target/riscv/tcg/debug.c
> index 3c0fe7010..ae493235d 100644
> --- a/target/riscv/tcg/debug.c
> +++ b/target/riscv/tcg/debug.c
> @@ -913,7 +913,8 @@ void tdata_csr_write(CPURISCVState *env, int
> tdata_index, target_ulong val)
> trigger_type);
> break;
> default:
> - g_assert_not_reached();
> + qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d is
> unassigned\n",
> + trigger_type);
> }
> }
>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] target/riscv: prevent abrupt abortion on unassigned value write to tdata
2026-07-29 23:00 [PATCH] target/riscv: prevent abrupt abortion on unassigned value write to tdata Abhigyan Kumar
2026-08-14 13:14 ` abh
2026-09-03 4:31 ` Alistair Francis
@ 2026-09-03 4:57 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2026-09-03 4:57 UTC (permalink / raw)
To: 314abh@gmail.com, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, chao.liu.zevorn@gmail.com,
daniel.barboza@oss.qualcomm.com, palmer@dabbelt.com,
liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com
On Thu, 2026-07-30 at 04:30 +0530, Abhigyan Kumar wrote:
> tdata_csr_write is approachable by guest programs. In case of
> unassigned
> values written to a tdata CSR in debug mode, the switch-case falls
> through straight to default causing an immediate abort. The risc-v
> spec
> says:
>
> All tdata registers follow write-any-read-legal semantics. If a
> debugger
> writes an unsupported configuration, the register will read back
> a value
> that is supported (which may simply be a disabled trigger). This
> means
> that a debugger must always read back values it writes to tdata
> registers, unless it already knows what is supported.
>
> This fix correctly ensures that the WARL behaviour of tdata CSRs.
>
> Fixes: a42bd001 ("target/riscv: debug: Determine the trigger type
> from
> tdata1.type")
> Signed-off-by: Abhigyan Kumar <314abh@gmail.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/tcg/debug.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/tcg/debug.c b/target/riscv/tcg/debug.c
> index 3c0fe7010..ae493235d 100644
> --- a/target/riscv/tcg/debug.c
> +++ b/target/riscv/tcg/debug.c
> @@ -913,7 +913,8 @@ void tdata_csr_write(CPURISCVState *env, int
> tdata_index, target_ulong val)
> trigger_type);
> break;
> default:
> - g_assert_not_reached();
> + qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d is
> unassigned\n",
> + trigger_type);
> }
> }
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2026-09-03 4:57 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-07-29 23:00 [PATCH] target/riscv: prevent abrupt abortion on unassigned value write to tdata Abhigyan Kumar
2026-08-14 13:14 ` abh
2026-09-03 4:31 ` Alistair Francis
2026-09-03 4:57 ` Alistair Francis
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.