* [PATCH v2 0/9] ARM: stm32: add STM32H7R7 and ART-Pi2 support
@ 2026-07-31 10:44 Liu Changjie
2026-07-23 15:48 ` [PATCH v2 1/9] dt-bindings: arm: stm32: add Ruiside ART-Pi2 Liu Changjie
` (8 more replies)
0 siblings, 9 replies; 12+ messages in thread
From: Liu Changjie @ 2026-07-31 10:44 UTC (permalink / raw)
To: Jonathan Corbet, Shuah Khan, Maxime Coquelin, Alexandre Torgue,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Michael Turquette,
Stephen Boyd, Brian Masney, Antonio Borneo, Linus Walleij,
Russell King, Lee Jones, Philipp Zabel, Dario Binacchi
Cc: linux-doc, linux-kernel, linux-stm32, linux-arm-kernel,
devicetree, linux-clk, linux-gpio, mfd
Add initial mainline support for the STM32H7R7 and the Ruiside ART-Pi2
development board.
The ART-Pi2 boots through first-stage firmware in the STM32 internal flash.
That firmware configures the PLLs and memory interfaces before Linux
executes in place from external XSPI NOR, with 32 MiB of HyperRAM used as
system RAM. Reprogramming the PLLs from Linux could therefore stop the
instruction stream.
The RCC driver intentionally reconstructs the active clock rates from the
firmware-programmed RCC registers. It exposes the resulting SYSCLK, bus,
timer, UART and SDMMC clocks, while Linux owns only the peripheral clock
gates used by the initial device tree. The same RCC probe registers the
reset lines through reset_simple_ops; the first reset consumer is SDMMC1.
The pinctrl driver covers GPIOA-H and GPIOM-P, including the AF0 trace
functions described by the STM32H7RS pin-control data. The board device
tree enables UART4, TIM5, twelve GPIO banks, two LEDs, the user button and
the four-bit SDMMC1 interface used by the microSD socket. The socket has
no card detect signal connected to the MCU, so the board uses broken-cd.
ARM noMMU selects DMA_GLOBAL_POOL, so the board reserves a 2 MiB shared DMA
pool for the SDMMC internal DMA descriptor and bounce buffer.
Changes in v2:
- clk: register as a builtin platform driver with a probe instead of
CLK_OF_DECLARE_DRIVER; switch to devm_of_iomap()/devm_clk_get()/devm
clock registration; register gates with clk_parent_data; drop the
unused slab.h include; reverse-Christmas-tree the pll_rate() locals
and add the missing blank line (all per Brian Masney's review).
- clk: register the RCC reset controller from probe via reset_simple_ops
(select RESET_SIMPLE), and give the RCC node a single
"st,stm32h7rs-rcc" compatible so the generic reset-simple platform
driver no longer competes for the node.
- dts: clock TIM5 from a DT fixed-clock because it is initialized via
TIMER_OF_DECLARE() before the RCC platform driver.
- dts: use the pinctrl "ranges" offsets for the GPIO bank unit-addresses
to fix the kernel test robot dtc warnings.
- Add the STM32H7RS files to MAINTAINERS and expand the Kconfig help.
Link to v1:
https://lore.kernel.org/r/MN0PR19MB60912FA1E75E4E55B2E27D34ACCD2@MN0PR19MB6091.namprd19.prod.outlook.com
Tested on an ART-Pi2 with the exact kernel from this series:
- booted an XIP kernel from external NOR to a static-FLAT BusyBox
userspace;
- detected 32 MiB of HyperRAM;
- used UART4 as early and normal console;
- used TIM5 as clockevent and clocksource;
- RCC bound as a platform driver and registered the reset controller,
the bus/timer/UART/SDMMC clocks and the peripheral gates;
- registered all twelve GPIO banks, both LEDs and the gpio-key input
device;
- detected a 59.5 GiB SDXC card through mmci-pl18x, then wrote a 1 MiB
random file to an ext4 partition, synced, unmounted and remounted it,
and verified identical SHA-256 hashes before deleting the test file
and unmounting cleanly;
- built the target DTB with CHECK_DTBS=y and passed dt-doc-validate for
the changed bindings;
- ran checkpatch on all nine patches with no errors.
The test kernel kept the Cortex-M7 instruction and data caches disabled.
DMA coherency with the data cache enabled remains to be validated
separately.
The only dtbs_check diagnostic is the existing lack of a schema matching
"arm,cortex-m7".
Liu Changjie (9):
dt-bindings: arm: stm32: add Ruiside ART-Pi2
dt-bindings: clock: stm32: add STM32H7RS RCC
clk: stm32: add STM32H7RS RCC driver
dt-bindings: pinctrl: stm32: add STM32H7RS
pinctrl: stm32: add STM32H7RS support
ARM: stm32: add STM32H7R7 platform support
ARM: dts: stm32: add STM32H7R7 SoC
ARM: dts: stm32: add Ruiside ART-Pi2 board
ARM: stm32: document STM32H7R7 support
Documentation/arch/arm/index.rst | 1 +
.../arch/arm/stm32/stm32h7r7-overview.rst | 28 +
.../devicetree/bindings/arm/stm32/stm32.yaml | 3 +
.../bindings/clock/st,stm32-rcc.yaml | 73 +-
.../bindings/pinctrl/st,stm32-pinctrl.yaml | 7 +-
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
MAINTAINERS | 6 +
arch/arm/Kconfig.debug | 12 +
arch/arm/boot/dts/st/Makefile | 1 +
arch/arm/boot/dts/st/stm32h7r7.dtsi | 261 +++
arch/arm/boot/dts/st/stm32h7r7l8-art-pi2.dts | 100 +
arch/arm/boot/dts/st/stm32h7rs-pinctrl.dtsi | 63 +
arch/arm/include/debug/stm32.S | 2 +-
arch/arm/mach-stm32/Kconfig | 9 +
arch/arm/mach-stm32/board-dt.c | 1 +
drivers/clk/Kconfig | 6 +
drivers/clk/Makefile | 1 +
drivers/clk/clk-stm32h7rs.c | 521 +++++
drivers/pinctrl/stm32/Kconfig | 11 +
drivers/pinctrl/stm32/Makefile | 1 +
drivers/pinctrl/stm32/pinctrl-stm32h7rs.c | 1849 +++++++++++++++++
include/dt-bindings/clock/stm32h7rs-clks.h | 32 +
include/dt-bindings/mfd/stm32h7rs-rcc.h | 11 +
23 files changed, 2985 insertions(+), 16 deletions(-)
create mode 100644 Documentation/arch/arm/stm32/stm32h7r7-overview.rst
create mode 100644 arch/arm/boot/dts/st/stm32h7r7.dtsi
create mode 100644 arch/arm/boot/dts/st/stm32h7r7l8-art-pi2.dts
create mode 100644 arch/arm/boot/dts/st/stm32h7rs-pinctrl.dtsi
create mode 100644 drivers/clk/clk-stm32h7rs.c
create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32h7rs.c
create mode 100644 include/dt-bindings/clock/stm32h7rs-clks.h
create mode 100644 include/dt-bindings/mfd/stm32h7rs-rcc.h
base-commit: 248951ddc14de84de3910f9b13f51491a8cd91df
--
2.55.0
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v2 1/9] dt-bindings: arm: stm32: add Ruiside ART-Pi2 2026-07-31 10:44 [PATCH v2 0/9] ARM: stm32: add STM32H7R7 and ART-Pi2 support Liu Changjie @ 2026-07-23 15:48 ` Liu Changjie 2026-07-23 15:48 ` [PATCH v2 2/9] dt-bindings: clock: stm32: add STM32H7RS RCC Liu Changjie ` (7 subsequent siblings) 8 siblings, 0 replies; 12+ messages in thread From: Liu Changjie @ 2026-07-23 15:48 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel Document the Ruiside vendor prefix and the ART-Pi2 board compatible. The board is built around the STM32H7R7 microcontroller. Signed-off-by: Liu Changjie <liucj1228@outlook.com> --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 3 +++ Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 2 files changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index c6af3a463..337448dc4 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -50,6 +50,9 @@ properties: - enum: - st,stm32h750i-art-pi - const: st,stm32h750 + - items: + - const: ruiside,art-pi2 + - const: st,stm32h7r7 - items: - enum: - st,stm32mp135f-dk diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 396044f36..401971b7f 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1425,6 +1425,8 @@ patternProperties: description: Shenzhen Roofull Technology Co, Ltd "^roseapplepi,.*": description: RoseapplePi.org + "^ruiside,.*": + description: Shanghai Ruiside Electronic Technology Co., Ltd. "^rve,.*": description: Recharge Véhicule Électrique (RVE) inc. "^saef,.*": -- 2.55.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 2/9] dt-bindings: clock: stm32: add STM32H7RS RCC 2026-07-31 10:44 [PATCH v2 0/9] ARM: stm32: add STM32H7R7 and ART-Pi2 support Liu Changjie 2026-07-23 15:48 ` [PATCH v2 1/9] dt-bindings: arm: stm32: add Ruiside ART-Pi2 Liu Changjie @ 2026-07-23 15:48 ` Liu Changjie 2026-08-09 10:15 ` sashiko-bot 2026-07-23 15:48 ` [PATCH v2 3/9] clk: stm32: add STM32H7RS RCC driver Liu Changjie ` (6 subsequent siblings) 8 siblings, 1 reply; 12+ messages in thread From: Liu Changjie @ 2026-07-23 15:48 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue, Lee Jones, Dario Binacchi Cc: linux-clk, devicetree, linux-stm32, linux-arm-kernel, linux-kernel, mfd Extend the STM32 RCC binding for STM32H7RS and add its clock and reset IDs. First-stage firmware configures the clock tree for external-memory execution, so Linux consumes the active tree and controls peripheral gates and resets. Signed-off-by: Liu Changjie <liucj1228@outlook.com> --- Changes in v2: - Give "st,stm32h7rs-rcc" its own standalone compatible (drop the "st,stm32-rcc" fallback) so the RCC node is matched only by the STM32H7RS clock driver and not by the generic reset-simple platform driver; update the example accordingly. .../bindings/clock/st,stm32-rcc.yaml | 73 +++++++++++++++---- include/dt-bindings/clock/stm32h7rs-clks.h | 32 ++++++++ include/dt-bindings/mfd/stm32h7rs-rcc.h | 11 +++ 3 files changed, 102 insertions(+), 14 deletions(-) create mode 100644 include/dt-bindings/clock/stm32h7rs-clks.h create mode 100644 include/dt-bindings/mfd/stm32h7rs-rcc.h diff --git a/Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml index f83a6120d..b512da6c2 100644 --- a/Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml +++ b/Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml @@ -23,6 +23,7 @@ properties: - st,stm32f746-rcc - st,stm32h743-rcc - const: st,stm32-rcc + - const: st,stm32h7rs-rcc - items: - enum: - st,stm32f469-rcc @@ -47,6 +48,10 @@ properties: minItems: 2 maxItems: 3 + clock-names: + minItems: 2 + maxItems: 2 + st,syscfg: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -79,14 +84,13 @@ required: - '#reset-cells' - '#clock-cells' - clocks - - st,syscfg allOf: - if: properties: compatible: contains: - const: st,stm32h743-rcc + const: st,stm32h7rs-rcc then: properties: '#clock-cells': @@ -97,23 +101,55 @@ allOf: items: - description: high speed external (HSE) clock input - description: low speed external (LSE) clock input - - description: Inter-IC sound (I2S) clock input + clock-names: + items: + - const: hse + - const: lse + st,syscfg: false st,ssc-modfreq-hz: false st,ssc-moddepth-permyriad: false st,ssc-modmethod: false + required: + - clock-names else: - properties: - '#clock-cells': - const: 2 - description: | - - The first cell is the clock type, possible values are 0 for - gated clocks and 1 otherwise. - - The second cell is the clock index for the specified type. - clocks: - items: - - description: high speed external (HSE) clock input - - description: Inter-IC sound (I2S) clock input + required: + - st,syscfg + allOf: + - if: + properties: + compatible: + contains: + const: st,stm32h743-rcc + then: + properties: + '#clock-cells': + const: 1 + description: | + The clock index for the specified type. + clocks: + items: + - description: high speed external (HSE) clock input + - description: low speed external (LSE) clock input + - description: Inter-IC sound (I2S) clock input + clock-names: false + st,ssc-modfreq-hz: false + st,ssc-moddepth-permyriad: false + st,ssc-modmethod: false + + else: + properties: + '#clock-cells': + const: 2 + description: | + - The first cell is the clock type, possible values are 0 for + gated clocks and 1 otherwise. + - The second cell is the clock index for the specified type. + clocks: + items: + - description: high speed external (HSE) clock input + - description: Inter-IC sound (I2S) clock input + clock-names: false additionalProperties: false @@ -140,5 +176,14 @@ examples: clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>; st,syscfg = <&pwrcfg>; }; + - | + reset-clock-controller@58024400 { + compatible = "st,stm32h7rs-rcc"; + reg = <0x58024400 0x400>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&clk_hse>, <&clk_lse>; + clock-names = "hse", "lse"; + }; ... diff --git a/include/dt-bindings/clock/stm32h7rs-clks.h b/include/dt-bindings/clock/stm32h7rs-clks.h new file mode 100644 index 000000000..e62e5d7e4 --- /dev/null +++ b/include/dt-bindings/clock/stm32h7rs-clks.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +#ifndef _DT_BINDINGS_CLOCK_STM32H7RS_CLKS_H +#define _DT_BINDINGS_CLOCK_STM32H7RS_CLKS_H + +#define STM32H7RS_SYS_CK 0 +#define STM32H7RS_HCLK 1 +#define STM32H7RS_PCLK1 2 +#define STM32H7RS_PCLK2 3 +#define STM32H7RS_PCLK4 4 +#define STM32H7RS_PCLK5 5 + +#define STM32H7RS_TIM5_CK 6 +#define STM32H7RS_UART4_CK 7 + +#define STM32H7RS_GPIOA_CK 8 +#define STM32H7RS_GPIOB_CK 9 +#define STM32H7RS_GPIOC_CK 10 +#define STM32H7RS_GPIOD_CK 11 +#define STM32H7RS_GPIOE_CK 12 +#define STM32H7RS_GPIOF_CK 13 +#define STM32H7RS_GPIOG_CK 14 +#define STM32H7RS_GPIOH_CK 15 +#define STM32H7RS_GPIOM_CK 16 +#define STM32H7RS_GPION_CK 17 +#define STM32H7RS_GPIOO_CK 18 +#define STM32H7RS_GPIOP_CK 19 + +#define STM32H7RS_SDMMC1_CK 20 + +#define STM32H7RS_MAX_CLKS 21 + +#endif /* _DT_BINDINGS_CLOCK_STM32H7RS_CLKS_H */ diff --git a/include/dt-bindings/mfd/stm32h7rs-rcc.h b/include/dt-bindings/mfd/stm32h7rs-rcc.h new file mode 100644 index 000000000..2302e0df1 --- /dev/null +++ b/include/dt-bindings/mfd/stm32h7rs-rcc.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +#ifndef _DT_BINDINGS_MFD_STM32H7RS_RCC_H +#define _DT_BINDINGS_MFD_STM32H7RS_RCC_H + +/* AHB5 */ +#define STM32H7RS_RCC_AHB5_SDMMC1 8 + +#define STM32H7RS_AHB5_RESET(bit) \ + (STM32H7RS_RCC_AHB5_##bit + (0x7c * 8)) + +#endif /* _DT_BINDINGS_MFD_STM32H7RS_RCC_H */ -- 2.55.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v2 2/9] dt-bindings: clock: stm32: add STM32H7RS RCC 2026-07-23 15:48 ` [PATCH v2 2/9] dt-bindings: clock: stm32: add STM32H7RS RCC Liu Changjie @ 2026-08-09 10:15 ` sashiko-bot 0 siblings, 0 replies; 12+ messages in thread From: sashiko-bot @ 2026-08-09 10:15 UTC (permalink / raw) To: Liu Changjie; +Cc: robh, mfd, lee, devicetree, conor+dt > Extend the STM32 RCC binding for STM32H7RS and add its clock and > reset IDs. First-stage firmware configures the clock tree for > external-memory execution, so Linux consumes the active tree and > controls peripheral gates and resets. > > Signed-off-by: Liu Changjie <liucj1228@outlook.com> Sashiko has reviewed this patch and found no issues. It looks great! -- Sashiko AI review · https://sashiko.dev/#/patchset/MN0PR19MB6091DB524E7A07E16D108F52ACDF2@MN0PR19MB6091.namprd19.prod.outlook.com?part=2 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 3/9] clk: stm32: add STM32H7RS RCC driver 2026-07-31 10:44 [PATCH v2 0/9] ARM: stm32: add STM32H7R7 and ART-Pi2 support Liu Changjie 2026-07-23 15:48 ` [PATCH v2 1/9] dt-bindings: arm: stm32: add Ruiside ART-Pi2 Liu Changjie 2026-07-23 15:48 ` [PATCH v2 2/9] dt-bindings: clock: stm32: add STM32H7RS RCC Liu Changjie @ 2026-07-23 15:48 ` Liu Changjie 2026-07-23 15:49 ` [PATCH v2 4/9] dt-bindings: pinctrl: stm32: add STM32H7RS Liu Changjie ` (5 subsequent siblings) 8 siblings, 0 replies; 12+ messages in thread From: Liu Changjie @ 2026-07-23 15:48 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, Brian Masney, Maxime Coquelin, Alexandre Torgue, Philipp Zabel Cc: linux-kernel, linux-clk, linux-stm32, linux-arm-kernel Register the active STM32H7RS system, bus and selected peripheral clocks without reprogramming the PLLs used for execute-in-place. Decode the PLL2 S and T outputs used by SDMMC from PLL2DIVR2. Expose gates for TIM5, UART4, GPIO banks A-H and M-P, and SDMMC1. Signed-off-by: Liu Changjie <liucj1228@outlook.com> --- Changes in v2: - Register as a builtin platform driver with a probe instead of CLK_OF_DECLARE_DRIVER (Brian Masney). - Use devm_of_iomap(), devm_clk_get() and the devm clock registration / provider helpers, and drop the hand-written failure unwinding (Brian Masney). - Register the peripheral gates with struct clk_parent_data via devm_clk_hw_register_gate_parent_data() instead of parent_name (Brian Masney). - Register the RCC reset controller from probe using reset_simple_ops (select RESET_SIMPLE) instead of relying on a separate reset-simple bind to a shared compatible. - Drop the unused <linux/slab.h> include (Brian Masney). - Reorder the stm32h7rs_pll_rate() locals in reverse-Christmas-tree order and add the missing blank line before the return (Brian Masney). drivers/clk/Kconfig | 6 + drivers/clk/Makefile | 1 + drivers/clk/clk-stm32h7rs.c | 521 ++++++++++++++++++++++++++++++++++++ 3 files changed, 528 insertions(+) create mode 100644 drivers/clk/clk-stm32h7rs.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 1717ce75a..666d92a7d 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -448,6 +448,12 @@ config COMMON_CLK_STM32H7 help Support for stm32h7 SoC family clocks +config COMMON_CLK_STM32H7RS + def_bool COMMON_CLK && MACH_STM32H7R7 + select RESET_SIMPLE + help + Support for STM32H7RS SoC family clocks + config COMMON_CLK_MMP2 def_bool COMMON_CLK && (MACH_MMP2_DT || MACH_MMP3_DT) help diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index cc108a75a..3dcb2f525 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -98,6 +98,7 @@ obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o obj-$(CONFIG_COMMON_CLK_SP7021) += clk-sp7021.o obj-$(CONFIG_COMMON_CLK_STM32F) += clk-stm32f4.o obj-$(CONFIG_COMMON_CLK_STM32H7) += clk-stm32h7.o +obj-$(CONFIG_COMMON_CLK_STM32H7RS) += clk-stm32h7rs.o obj-$(CONFIG_COMMON_CLK_TPS68470) += clk-tps68470.o obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o obj-$(CONFIG_CLK_TWL) += clk-twl.o diff --git a/drivers/clk/clk-stm32h7rs.c b/drivers/clk/clk-stm32h7rs.c new file mode 100644 index 000000000..8d94953d2 --- /dev/null +++ b/drivers/clk/clk-stm32h7rs.c @@ -0,0 +1,521 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Clock driver for the STM32H7RS Reset and Clock Controller. + * + * The first-stage firmware configures the oscillators and PLLs before Linux + * starts executing from external NOR. The driver reconstructs that running + * clock tree from RCC registers and gives Linux ownership of peripheral clock + * gates without disturbing the XIP-critical PLL configuration. + */ + +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/math64.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/reset-controller.h> +#include <linux/reset/reset-simple.h> +#include <linux/spinlock.h> + +#include <dt-bindings/clock/stm32h7rs-clks.h> + +#define RCC_CR 0x000 +#define RCC_CFGR 0x010 +#define RCC_CDCFGR 0x018 +#define RCC_BMCFGR 0x01c +#define RCC_APBCFGR 0x020 +#define RCC_PLLCKSELR 0x028 +#define RCC_PLLCFGR 0x02c +#define RCC_PLL1DIVR1 0x030 +#define RCC_PLL1FRACR 0x034 +#define RCC_PLL2DIVR1 0x038 +#define RCC_PLL2FRACR 0x03c +#define RCC_PLL3DIVR1 0x040 +#define RCC_PLL3FRACR 0x044 +#define RCC_CCIPR1 0x04c +#define RCC_CCIPR2 0x050 +#define RCC_PLL2DIVR2 0x0c4 +#define RCC_AHB5ENR 0x134 +#define RCC_AHB4ENR 0x140 +#define RCC_APB1ENR1 0x148 + +#define RCC_CR_HSIDIV_SHIFT 3 +#define RCC_CFGR_SWS_SHIFT 3 +#define RCC_CFGR_TIMPRE BIT(15) +#define RCC_PLLCFGR_FRACEN(_pll) BIT(((_pll) - 1) * 11) +#define RCC_PLL_ON(_pll) BIT(24 + (((_pll) - 1) * 2)) + +#define RCC_CDCFGR_CPRE_SHIFT 0 +#define RCC_BMCFGR_BMPRE_SHIFT 0 +#define RCC_APBCFGR_PPRE1_SHIFT 0 +#define RCC_APBCFGR_PPRE2_SHIFT 4 +#define RCC_APBCFGR_PPRE4_SHIFT 8 +#define RCC_APBCFGR_PPRE5_SHIFT 12 + +#define RCC_CCIPR1_SDMMC12SEL BIT(2) +#define RCC_CCIPR2_UARTSEL_MASK GENMASK(2, 0) + +#define HSI_RATE 64000000UL +#define CSI_RATE 4000000UL + +static DEFINE_SPINLOCK(stm32h7rs_rcc_lock); + +static const u16 pll_divr_offset[] = { + RCC_PLL1DIVR1, RCC_PLL2DIVR1, RCC_PLL3DIVR1, +}; + +static const u16 pll_fracr_offset[] = { + RCC_PLL1FRACR, RCC_PLL2FRACR, RCC_PLL3FRACR, +}; + +static const u8 pll_m_shift[] = { 4, 12, 20 }; + +enum stm32h7rs_pll_output { + PLL_P, + PLL_Q, + PLL_R, + PLL_S, + PLL_T, +}; + +static unsigned long stm32h7rs_hsi_rate(void __iomem *base) +{ + u32 div = (readl_relaxed(base + RCC_CR) >> RCC_CR_HSIDIV_SHIFT) & 0x3; + + return HSI_RATE >> div; +} + +static unsigned long stm32h7rs_pll_rate(void __iomem *base, unsigned int pll, + unsigned int output, + unsigned long hse_rate) +{ + static const u8 output_shift[] = { 9, 16, 24 }; + u32 divr1, frac = 0, m, n, out_div, source; + unsigned long parent_rate; + u64 numerator; + + if (pll < 1 || pll > ARRAY_SIZE(pll_divr_offset) || output > PLL_T) + return 0; + + if (output > PLL_R && pll != 2) + return 0; + + if (!(readl_relaxed(base + RCC_CR) & RCC_PLL_ON(pll))) + return 0; + + source = readl_relaxed(base + RCC_PLLCKSELR) & GENMASK(1, 0); + switch (source) { + case 0: + parent_rate = stm32h7rs_hsi_rate(base); + break; + case 1: + parent_rate = CSI_RATE; + break; + case 2: + parent_rate = hse_rate; + break; + default: + return 0; + } + + m = (readl_relaxed(base + RCC_PLLCKSELR) >> pll_m_shift[pll - 1]) & 0x3f; + if (!m || !parent_rate) + return 0; + + divr1 = readl_relaxed(base + pll_divr_offset[pll - 1]); + n = (divr1 & GENMASK(8, 0)) + 1; + if (readl_relaxed(base + RCC_PLLCFGR) & RCC_PLLCFGR_FRACEN(pll)) + frac = (readl_relaxed(base + pll_fracr_offset[pll - 1]) >> 3) & + GENMASK(12, 0); + + if (output <= PLL_R) { + out_div = ((divr1 >> output_shift[output]) & + GENMASK(6, 0)) + 1; + } else { + u32 divr2 = readl_relaxed(base + RCC_PLL2DIVR2); + u8 shift = output == PLL_S ? 0 : 8; + + out_div = ((divr2 >> shift) & GENMASK(2, 0)) + 1; + } + + numerator = (u64)parent_rate * (n * 8192ULL + frac); + + return div64_u64(numerator, (u64)m * 8192ULL * out_div); +} + +static unsigned long stm32h7rs_ahb_rate(unsigned long parent_rate, u32 val) +{ + static const u16 div_table[] = { 2, 4, 8, 16, 64, 128, 256, 512 }; + + if (val < 8) + return parent_rate; + + return parent_rate / div_table[val - 8]; +} + +static unsigned long stm32h7rs_sys_rate(void __iomem *base, + unsigned long hse_rate) +{ + unsigned long rate; + u32 cpre, source; + + source = (readl_relaxed(base + RCC_CFGR) >> RCC_CFGR_SWS_SHIFT) & 0x7; + switch (source) { + case 0: + rate = stm32h7rs_hsi_rate(base); + break; + case 1: + rate = CSI_RATE; + break; + case 2: + rate = hse_rate; + break; + case 3: + rate = stm32h7rs_pll_rate(base, 1, PLL_P, hse_rate); + break; + default: + return 0; + } + + cpre = (readl_relaxed(base + RCC_CDCFGR) >> RCC_CDCFGR_CPRE_SHIFT) & 0xf; + return stm32h7rs_ahb_rate(rate, cpre); +} + +static unsigned long stm32h7rs_apb_rate(void __iomem *base, + unsigned long hclk_rate, u8 shift) +{ + u32 prescaler = (readl_relaxed(base + RCC_APBCFGR) >> shift) & 0x7; + + if (prescaler < 4) + return hclk_rate; + + return hclk_rate >> (prescaler - 3); +} + +static unsigned long stm32h7rs_timer_rate(void __iomem *base, + unsigned long hclk_rate, + unsigned long pclk_rate) +{ + u32 prescaler = (readl_relaxed(base + RCC_APBCFGR) >> + RCC_APBCFGR_PPRE1_SHIFT) & 0x7; + + if (prescaler < 4) + return pclk_rate; + + if (!(readl_relaxed(base + RCC_CFGR) & RCC_CFGR_TIMPRE)) + return pclk_rate * 2; + + return prescaler < 6 ? hclk_rate : pclk_rate * 4; +} + +static unsigned long stm32h7rs_uart4_rate(void __iomem *base, + unsigned long hse_rate, + unsigned long lse_rate, + unsigned long pclk1_rate) +{ + u32 source = readl_relaxed(base + RCC_CCIPR2) & RCC_CCIPR2_UARTSEL_MASK; + + switch (source) { + case 0: + return pclk1_rate; + case 1: + return stm32h7rs_pll_rate(base, 2, PLL_Q, hse_rate); + case 2: + return stm32h7rs_pll_rate(base, 3, PLL_Q, hse_rate); + case 3: + return stm32h7rs_hsi_rate(base); + case 4: + return CSI_RATE; + case 5: + return lse_rate; + default: + return 0; + } +} + +static unsigned long stm32h7rs_sdmmc1_rate(void __iomem *base, + unsigned long hse_rate) +{ + if (readl_relaxed(base + RCC_CCIPR1) & RCC_CCIPR1_SDMMC12SEL) + return stm32h7rs_pll_rate(base, 2, PLL_T, hse_rate); + + return stm32h7rs_pll_rate(base, 2, PLL_S, hse_rate); +} + +static int h7rs_register_fixed(struct device *dev, + struct clk_hw_onecell_data *data, + unsigned int id, const char *name, + unsigned long rate) +{ + struct clk_hw *hw; + + hw = devm_clk_hw_register_fixed_rate(dev, name, NULL, CLK_IS_CRITICAL, + rate); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + data->hws[id] = hw; + + return 0; +} + +enum stm32h7rs_parent { + STM32H7RS_PARENT_HCLK, + STM32H7RS_PARENT_TIM5, + STM32H7RS_PARENT_UART4, + STM32H7RS_PARENT_SDMMC1, + STM32H7RS_PARENT_COUNT, +}; + +struct stm32h7rs_gate { + const char *name; + u16 offset; + u8 id; + u8 parent; + u8 bit_idx; +}; + +static const struct stm32h7rs_gate stm32h7rs_gates[] = { + { "tim5", RCC_APB1ENR1, STM32H7RS_TIM5_CK, + STM32H7RS_PARENT_TIM5, 3 }, + { "uart4", RCC_APB1ENR1, STM32H7RS_UART4_CK, + STM32H7RS_PARENT_UART4, 19 }, + { "gpioa", RCC_AHB4ENR, STM32H7RS_GPIOA_CK, + STM32H7RS_PARENT_HCLK, 0 }, + { "gpiob", RCC_AHB4ENR, STM32H7RS_GPIOB_CK, + STM32H7RS_PARENT_HCLK, 1 }, + { "gpioc", RCC_AHB4ENR, STM32H7RS_GPIOC_CK, + STM32H7RS_PARENT_HCLK, 2 }, + { "gpiod", RCC_AHB4ENR, STM32H7RS_GPIOD_CK, + STM32H7RS_PARENT_HCLK, 3 }, + { "gpioe", RCC_AHB4ENR, STM32H7RS_GPIOE_CK, + STM32H7RS_PARENT_HCLK, 4 }, + { "gpiof", RCC_AHB4ENR, STM32H7RS_GPIOF_CK, + STM32H7RS_PARENT_HCLK, 5 }, + { "gpiog", RCC_AHB4ENR, STM32H7RS_GPIOG_CK, + STM32H7RS_PARENT_HCLK, 6 }, + { "gpioh", RCC_AHB4ENR, STM32H7RS_GPIOH_CK, + STM32H7RS_PARENT_HCLK, 7 }, + { "gpiom", RCC_AHB4ENR, STM32H7RS_GPIOM_CK, + STM32H7RS_PARENT_HCLK, 12 }, + { "gpion", RCC_AHB4ENR, STM32H7RS_GPION_CK, + STM32H7RS_PARENT_HCLK, 13 }, + { "gpioo", RCC_AHB4ENR, STM32H7RS_GPIOO_CK, + STM32H7RS_PARENT_HCLK, 14 }, + { "gpiop", RCC_AHB4ENR, STM32H7RS_GPIOP_CK, + STM32H7RS_PARENT_HCLK, 15 }, + { "sdmmc1", RCC_AHB5ENR, STM32H7RS_SDMMC1_CK, + STM32H7RS_PARENT_SDMMC1, 8 }, +}; + +static int h7rs_register_gate(struct device *dev, + struct clk_hw_onecell_data *data, + const struct stm32h7rs_gate *gate, + const struct clk_hw *parent_hw, + void __iomem *base) +{ + const struct clk_parent_data parent_data = { .hw = parent_hw }; + struct clk_hw *hw; + + hw = devm_clk_hw_register_gate_parent_data(dev, gate->name, + &parent_data, + CLK_IGNORE_UNUSED, + base + gate->offset, + gate->bit_idx, 0, + &stm32h7rs_rcc_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + data->hws[gate->id] = hw; + + return 0; +} + +static int stm32h7rs_rcc_probe(struct platform_device *pdev) +{ + struct clk_hw *parent_hws[STM32H7RS_PARENT_COUNT]; + struct clk_hw_onecell_data *clk_data; + struct reset_simple_data *reset; + struct device *dev = &pdev->dev; + unsigned long sdmmc1_rate; + unsigned long uart4_rate; + unsigned long timer_rate; + unsigned long pclk5_rate; + unsigned long pclk4_rate; + unsigned long pclk2_rate; + unsigned long pclk1_rate; + unsigned long hclk_rate; + unsigned long sys_rate; + unsigned long lse_rate; + unsigned long hse_rate; + resource_size_t size; + struct clk *input; + void __iomem *base; + unsigned int i; + u32 bmpre; + int ret; + + base = devm_of_iomap(dev, dev->of_node, 0, &size); + if (IS_ERR(base)) + return dev_err_probe(dev, PTR_ERR(base), + "unable to map RCC registers\n"); + + input = devm_clk_get(dev, "hse"); + if (IS_ERR(input)) + return dev_err_probe(dev, PTR_ERR(input), + "unable to get HSE input clock\n"); + hse_rate = clk_get_rate(input); + + input = devm_clk_get(dev, "lse"); + if (IS_ERR(input)) + return dev_err_probe(dev, PTR_ERR(input), + "unable to get LSE input clock\n"); + lse_rate = clk_get_rate(input); + + reset = devm_kzalloc(dev, sizeof(*reset), GFP_KERNEL); + if (!reset) + return -ENOMEM; + + spin_lock_init(&reset->lock); + reset->membase = base; + reset->rcdev.owner = THIS_MODULE; + reset->rcdev.nr_resets = size * BITS_PER_BYTE; + reset->rcdev.ops = &reset_simple_ops; + reset->rcdev.of_node = dev->of_node; + + ret = devm_reset_controller_register(dev, &reset->rcdev); + if (ret) + return dev_err_probe(dev, ret, + "failed to register reset controller\n"); + + clk_data = devm_kzalloc(dev, + struct_size(clk_data, hws, STM32H7RS_MAX_CLKS), + GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + clk_data->num = STM32H7RS_MAX_CLKS; + for (i = 0; i < clk_data->num; i++) + clk_data->hws[i] = ERR_PTR(-ENOENT); + + sys_rate = stm32h7rs_sys_rate(base, hse_rate); + bmpre = (readl_relaxed(base + RCC_BMCFGR) >> + RCC_BMCFGR_BMPRE_SHIFT) & 0xf; + hclk_rate = stm32h7rs_ahb_rate(sys_rate, bmpre); + pclk1_rate = stm32h7rs_apb_rate(base, hclk_rate, + RCC_APBCFGR_PPRE1_SHIFT); + pclk2_rate = stm32h7rs_apb_rate(base, hclk_rate, + RCC_APBCFGR_PPRE2_SHIFT); + pclk4_rate = stm32h7rs_apb_rate(base, hclk_rate, + RCC_APBCFGR_PPRE4_SHIFT); + pclk5_rate = stm32h7rs_apb_rate(base, hclk_rate, + RCC_APBCFGR_PPRE5_SHIFT); + timer_rate = stm32h7rs_timer_rate(base, hclk_rate, pclk1_rate); + uart4_rate = stm32h7rs_uart4_rate(base, hse_rate, lse_rate, pclk1_rate); + sdmmc1_rate = stm32h7rs_sdmmc1_rate(base, hse_rate); + + if (!sys_rate || !hclk_rate || !pclk1_rate || !pclk2_rate || + !pclk4_rate || !pclk5_rate || !timer_rate || !uart4_rate || + !sdmmc1_rate) + return dev_err_probe(dev, -EINVAL, + "invalid boot clock configuration\n"); + + ret = h7rs_register_fixed(dev, clk_data, STM32H7RS_SYS_CK, + "h7rs_sys_ck", sys_rate); + if (ret) + return dev_err_probe(dev, ret, + "failed to register system clock\n"); + + ret = h7rs_register_fixed(dev, clk_data, STM32H7RS_HCLK, + "h7rs_hclk", hclk_rate); + if (ret) + return dev_err_probe(dev, ret, + "failed to register HCLK\n"); + + ret = h7rs_register_fixed(dev, clk_data, STM32H7RS_PCLK1, + "h7rs_pclk1", pclk1_rate); + if (ret) + return dev_err_probe(dev, ret, + "failed to register PCLK1\n"); + + ret = h7rs_register_fixed(dev, clk_data, STM32H7RS_PCLK2, + "h7rs_pclk2", pclk2_rate); + if (ret) + return dev_err_probe(dev, ret, + "failed to register PCLK2\n"); + + ret = h7rs_register_fixed(dev, clk_data, STM32H7RS_PCLK4, + "h7rs_pclk4", pclk4_rate); + if (ret) + return dev_err_probe(dev, ret, + "failed to register PCLK4\n"); + + ret = h7rs_register_fixed(dev, clk_data, STM32H7RS_PCLK5, + "h7rs_pclk5", pclk5_rate); + if (ret) + return dev_err_probe(dev, ret, + "failed to register PCLK5\n"); + + parent_hws[STM32H7RS_PARENT_HCLK] = clk_data->hws[STM32H7RS_HCLK]; + parent_hws[STM32H7RS_PARENT_TIM5] = + devm_clk_hw_register_fixed_rate(dev, "tim5_ker", NULL, + CLK_IS_CRITICAL, timer_rate); + parent_hws[STM32H7RS_PARENT_UART4] = + devm_clk_hw_register_fixed_rate(dev, "uart4_ker", NULL, + CLK_IS_CRITICAL, uart4_rate); + parent_hws[STM32H7RS_PARENT_SDMMC1] = + devm_clk_hw_register_fixed_rate(dev, "sdmmc1_ker", NULL, + CLK_IS_CRITICAL, sdmmc1_rate); + + for (i = STM32H7RS_PARENT_TIM5; i < STM32H7RS_PARENT_COUNT; i++) { + if (IS_ERR(parent_hws[i])) + return dev_err_probe(dev, PTR_ERR(parent_hws[i]), + "failed to register parent clock %u\n", + i); + } + + for (i = 0; i < ARRAY_SIZE(stm32h7rs_gates); i++) { + const struct stm32h7rs_gate *gate = &stm32h7rs_gates[i]; + + ret = h7rs_register_gate(dev, clk_data, gate, + parent_hws[gate->parent], base); + if (ret) + return dev_err_probe(dev, ret, + "failed to register %s clock\n", + gate->name); + } + + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); + if (ret) + return dev_err_probe(dev, ret, + "failed to add clock provider\n"); + + dev_info(dev, + "sys=%lu hclk=%lu pclk1=%lu tim5=%lu uart4=%lu sdmmc1=%lu\n", + sys_rate, hclk_rate, pclk1_rate, timer_rate, uart4_rate, + sdmmc1_rate); + + return 0; +} + +static const struct of_device_id stm32h7rs_rcc_match[] = { + { .compatible = "st,stm32h7rs-rcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, stm32h7rs_rcc_match); + +static struct platform_driver stm32h7rs_rcc_driver = { + .probe = stm32h7rs_rcc_probe, + .driver = { + .name = "stm32h7rs-rcc", + .of_match_table = stm32h7rs_rcc_match, + }, +}; +builtin_platform_driver(stm32h7rs_rcc_driver); + +MODULE_DESCRIPTION("STM32H7RS Reset and Clock Controller driver"); +MODULE_LICENSE("GPL"); -- 2.55.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 4/9] dt-bindings: pinctrl: stm32: add STM32H7RS 2026-07-31 10:44 [PATCH v2 0/9] ARM: stm32: add STM32H7R7 and ART-Pi2 support Liu Changjie ` (2 preceding siblings ...) 2026-07-23 15:48 ` [PATCH v2 3/9] clk: stm32: add STM32H7RS RCC driver Liu Changjie @ 2026-07-23 15:49 ` Liu Changjie 2026-07-23 15:49 ` [PATCH v2 5/9] pinctrl: stm32: add STM32H7RS support Liu Changjie ` (4 subsequent siblings) 8 siblings, 0 replies; 12+ messages in thread From: Liu Changjie @ 2026-07-23 15:49 UTC (permalink / raw) To: Antonio Borneo, Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue Cc: linux-gpio, devicetree, linux-stm32, linux-arm-kernel, linux-kernel Add the STM32H7RS pin controller compatible. The H7RS family exposes GPIO banks M through P, so extend the bank names and EXTI I/O port selector range accordingly. Signed-off-by: Liu Changjie <liucj1228@outlook.com> --- .../devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml index 76d956b4a..6e74485b1 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml @@ -24,6 +24,7 @@ properties: - st,stm32f746-pinctrl - st,stm32f769-pinctrl - st,stm32h743-pinctrl + - st,stm32h7rs-pinctrl - st,stm32mp135-pinctrl - st,stm32mp157-pinctrl - st,stm32mp157-z-pinctrl @@ -115,6 +116,10 @@ patternProperties: - GPIOI - GPIOJ - GPIOK + - GPIOM + - GPION + - GPIOO + - GPIOP - GPIOZ st,bank-ioport: @@ -123,7 +128,7 @@ patternProperties: to select GPIOs as interrupts). $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 - maximum: 11 + maximum: 15 patternProperties: "^(.+-hog(-[0-9]+)?)$": -- 2.55.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 5/9] pinctrl: stm32: add STM32H7RS support 2026-07-31 10:44 [PATCH v2 0/9] ARM: stm32: add STM32H7R7 and ART-Pi2 support Liu Changjie ` (3 preceding siblings ...) 2026-07-23 15:49 ` [PATCH v2 4/9] dt-bindings: pinctrl: stm32: add STM32H7RS Liu Changjie @ 2026-07-23 15:49 ` Liu Changjie 2026-07-23 15:49 ` [PATCH v2 6/9] ARM: stm32: add STM32H7R7 platform support Liu Changjie ` (3 subsequent siblings) 8 siblings, 0 replies; 12+ messages in thread From: Liu Changjie @ 2026-07-23 15:49 UTC (permalink / raw) To: Antonio Borneo, Linus Walleij, Maxime Coquelin, Alexandre Torgue Cc: linux-kernel, linux-gpio, linux-stm32, linux-arm-kernel Add the STM32H7RS pin multiplexing table for GPIO banks A through H and M through P. Hook the driver into Kconfig so STM32H7R7 platforms select it by default. Signed-off-by: Liu Changjie <liucj1228@outlook.com> --- drivers/pinctrl/stm32/Kconfig | 11 + drivers/pinctrl/stm32/Makefile | 1 + drivers/pinctrl/stm32/pinctrl-stm32h7rs.c | 1849 +++++++++++++++++++++ 3 files changed, 1861 insertions(+) create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32h7rs.c diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig index d6a171523..74f151d6c 100644 --- a/drivers/pinctrl/stm32/Kconfig +++ b/drivers/pinctrl/stm32/Kconfig @@ -40,6 +40,17 @@ config PINCTRL_STM32H743 default MACH_STM32H743 select PINCTRL_STM32 +config PINCTRL_STM32H7RS + bool "STMicroelectronics STM32H7RS pin control" if COMPILE_TEST && !MACH_STM32H7R7 + depends on OF && HAS_IOMEM + default MACH_STM32H7R7 + select PINCTRL_STM32 + help + Say yes here to enable the pin controller and GPIO support for + STM32H7RS microcontrollers. The driver handles pin multiplexing, + pin configuration and the GPIO banks exposed by these devices. + It is required on STM32H7R7-based boards. + config PINCTRL_STM32MP135 bool "STMicroelectronics STM32MP135 pin control" if COMPILE_TEST && !MACH_STM32MP13 depends on OF && HAS_IOMEM diff --git a/drivers/pinctrl/stm32/Makefile b/drivers/pinctrl/stm32/Makefile index 98a1bbc7e..14ac5970b 100644 --- a/drivers/pinctrl/stm32/Makefile +++ b/drivers/pinctrl/stm32/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_STM32F469) += pinctrl-stm32f469.o obj-$(CONFIG_PINCTRL_STM32F746) += pinctrl-stm32f746.o obj-$(CONFIG_PINCTRL_STM32F769) += pinctrl-stm32f769.o obj-$(CONFIG_PINCTRL_STM32H743) += pinctrl-stm32h743.o +obj-$(CONFIG_PINCTRL_STM32H7RS) += pinctrl-stm32h7rs.o obj-$(CONFIG_PINCTRL_STM32MP135) += pinctrl-stm32mp135.o obj-$(CONFIG_PINCTRL_STM32MP157) += pinctrl-stm32mp157.o obj-$(CONFIG_PINCTRL_STM32MP257) += pinctrl-stm32mp257.o diff --git a/drivers/pinctrl/stm32/pinctrl-stm32h7rs.c b/drivers/pinctrl/stm32/pinctrl-stm32h7rs.c new file mode 100644 index 000000000..bdf3d61f1 --- /dev/null +++ b/drivers/pinctrl/stm32/pinctrl-stm32h7rs.c @@ -0,0 +1,1849 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * STM32H7RS pin controller driver. + * + * Copyright (C) 2026 Liu Changjie <liucj1228@outlook.com> + */ +#include <linux/init.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-stm32.h" + +static const struct stm32_desc_pin stm32h7rs_pins[] = { + STM32_PIN( + PINCTRL_PIN(0, "PA0"), + STM32_FUNCTION(0, "GPIOA0"), + STM32_FUNCTION(2, "TIM2_CH1"), + STM32_FUNCTION(3, "TIM5_CH1"), + STM32_FUNCTION(4, "TIM9_CH1"), + STM32_FUNCTION(5, "TIM15_BKIN"), + STM32_FUNCTION(6, "I2S6_WS SPI6_NSS"), + STM32_FUNCTION(8, "USART2_CTS"), + STM32_FUNCTION(9, "UART4_TX"), + STM32_FUNCTION(10, "SDMMC2_CMD"), + STM32_FUNCTION(11, "SAI2_SD_B"), + STM32_FUNCTION(13, "FMC_D7"), + STM32_FUNCTION(14, "LTDC_G3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(1, "PA1"), + STM32_FUNCTION(0, "GPIOA1"), + STM32_FUNCTION(2, "TIM2_CH2"), + STM32_FUNCTION(3, "TIM5_CH2"), + STM32_FUNCTION(4, "LPTIM3_IN1"), + STM32_FUNCTION(5, "TIM15_CH1N"), + STM32_FUNCTION(6, "DCMIPP_D0"), + STM32_FUNCTION(8, "USART2_DE USART2_RTS"), + STM32_FUNCTION(9, "UART4_RX"), + STM32_FUNCTION(11, "SAI2_MCLK_B"), + STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"), + STM32_FUNCTION(13, "FMC_D6"), + STM32_FUNCTION(14, "LTDC_G2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(2, "PA2"), + STM32_FUNCTION(0, "GPIOA2"), + STM32_FUNCTION(2, "TIM2_CH3"), + STM32_FUNCTION(3, "TIM5_CH3"), + STM32_FUNCTION(4, "LPTIM3_IN2"), + STM32_FUNCTION(5, "TIM15_CH1"), + STM32_FUNCTION(8, "USART2_TX"), + STM32_FUNCTION(9, "SAI2_SCK_B"), + STM32_FUNCTION(12, "ETH_MDIO"), + STM32_FUNCTION(13, "FMC_D5"), + STM32_FUNCTION(14, "LTDC_B7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(3, "PA3"), + STM32_FUNCTION(0, "GPIOA3"), + STM32_FUNCTION(2, "TIM2_CH4"), + STM32_FUNCTION(3, "TIM5_CH4"), + STM32_FUNCTION(4, "LPTIM3_CH1"), + STM32_FUNCTION(5, "TIM15_CH2"), + STM32_FUNCTION(6, "I2S6_MCK"), + STM32_FUNCTION(8, "USART2_RX"), + STM32_FUNCTION(12, "ETH_MII_COL"), + STM32_FUNCTION(14, "LTDC_DE"), + STM32_FUNCTION(15, "TIM1_CH3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(4, "PA4"), + STM32_FUNCTION(0, "GPIOA4"), + STM32_FUNCTION(4, "LPTIM3_CH2"), + STM32_FUNCTION(6, "I2S1_WS SPI1_NSS"), + STM32_FUNCTION(7, "I2S3_WS SPI3_NSS"), + STM32_FUNCTION(9, "I2S6_WS SPI6_NSS"), + STM32_FUNCTION(11, "USB_OTG_HS_SOF"), + STM32_FUNCTION(12, "ETH_MDIO"), + STM32_FUNCTION(13, "LTDC_R3"), + STM32_FUNCTION(14, "DCMIPP_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(5, "PA5"), + STM32_FUNCTION(0, "GPIOA5"), + STM32_FUNCTION(2, "TIM2_CH1"), + STM32_FUNCTION(4, "TIM9_CH2"), + STM32_FUNCTION(6, "I2S1_CK SPI1_SCK"), + STM32_FUNCTION(9, "I2S6_CK SPI6_SCK"), + STM32_FUNCTION(13, "FMC_NOE"), + STM32_FUNCTION(14, "DCMIPP_D8"), + STM32_FUNCTION(15, "LTDC_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(6, "PA6"), + STM32_FUNCTION(0, "GPIOA6"), + STM32_FUNCTION(2, "TIM1_BKIN"), + STM32_FUNCTION(3, "TIM3_CH1"), + STM32_FUNCTION(4, "LPTIM3_ETR"), + STM32_FUNCTION(6, "SPI1_MISO"), + STM32_FUNCTION(9, "SPI6_MISO"), + STM32_FUNCTION(10, "TIM13_CH1"), + STM32_FUNCTION(13, "LTDC_B7"), + STM32_FUNCTION(14, "DCMIPP_PIXCLK"), + STM32_FUNCTION(15, "LTDC_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(7, "PA7"), + STM32_FUNCTION(0, "GPIOA7"), + STM32_FUNCTION(2, "TIM1_CH1N"), + STM32_FUNCTION(3, "TIM3_CH2"), + STM32_FUNCTION(6, "SPI1_MOSI"), + STM32_FUNCTION(9, "SPI6_MOSI"), + STM32_FUNCTION(10, "TIM14_CH1"), + STM32_FUNCTION(11, "LTDC_R4"), + STM32_FUNCTION(12, "ETH_MII_RX_DV ETH_RMII_CRS_DV"), + STM32_FUNCTION(13, "FMC_INT"), + STM32_FUNCTION(14, "LTDC_B1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(8, "PA8"), + STM32_FUNCTION(0, "GPIOA8"), + STM32_FUNCTION(1, "RCC_MCO_1"), + STM32_FUNCTION(2, "TIM1_CH1"), + STM32_FUNCTION(5, "I2C3_SCL"), + STM32_FUNCTION(11, "USB_OTG_FS_SOF"), + STM32_FUNCTION(12, "UART7_RX"), + STM32_FUNCTION(13, "FMC_D4"), + STM32_FUNCTION(14, "LTDC_B6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(9, "PA9"), + STM32_FUNCTION(0, "GPIOA9"), + STM32_FUNCTION(2, "TIM1_CH2"), + STM32_FUNCTION(4, "LPUART1_TX"), + STM32_FUNCTION(5, "I2C3_SDA"), + STM32_FUNCTION(6, "I2S2_CK SPI2_SCK"), + STM32_FUNCTION(8, "USART1_TX"), + STM32_FUNCTION(13, "FMC_D3"), + STM32_FUNCTION(14, "DCMIPP_D0"), + STM32_FUNCTION(15, "LTDC_B5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(10, "PA10"), + STM32_FUNCTION(0, "GPIOA10"), + STM32_FUNCTION(2, "TIM1_CH3"), + STM32_FUNCTION(4, "LPUART1_RX"), + STM32_FUNCTION(8, "USART1_RX"), + STM32_FUNCTION(13, "FMC_D2"), + STM32_FUNCTION(14, "DCMIPP_D1"), + STM32_FUNCTION(15, "LTDC_B4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(11, "PA11"), + STM32_FUNCTION(0, "GPIOA11"), + STM32_FUNCTION(2, "TIM1_CH4"), + STM32_FUNCTION(4, "LPUART1_CTS"), + STM32_FUNCTION(6, "I2S2_WS SPI2_NSS"), + STM32_FUNCTION(7, "UART4_RX"), + STM32_FUNCTION(8, "USART1_CTS"), + STM32_FUNCTION(10, "FDCAN1_RX"), + STM32_FUNCTION(13, "FMC_D1"), + STM32_FUNCTION(14, "LTDC_B3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(12, "PA12"), + STM32_FUNCTION(0, "GPIOA12"), + STM32_FUNCTION(4, "LPUART1_DE LPUART1_RTS"), + STM32_FUNCTION(6, "I2S2_CK SPI2_SCK"), + STM32_FUNCTION(7, "UART4_TX"), + STM32_FUNCTION(8, "USART1_DE USART1_RTS"), + STM32_FUNCTION(9, "SAI2_FS_B"), + STM32_FUNCTION(10, "FDCAN1_TX"), + STM32_FUNCTION(13, "FMC_D0"), + STM32_FUNCTION(14, "LTDC_B2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(13, "PA13"), + STM32_FUNCTION(0, "GPIOA13"), + STM32_FUNCTION(1, "DEBUG_JTMS_SWDIO"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(14, "PA14"), + STM32_FUNCTION(0, "GPIOA14"), + STM32_FUNCTION(1, "DEBUG_JTCK_SWCLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(15, "PA15"), + STM32_FUNCTION(0, "GPIOA15"), + STM32_FUNCTION(1, "DEBUG_JTDI"), + STM32_FUNCTION(2, "TIM2_CH1"), + STM32_FUNCTION(6, "I2S1_WS SPI1_NSS"), + STM32_FUNCTION(7, "I2S3_WS SPI3_NSS"), + STM32_FUNCTION(8, "I2S6_WS SPI6_NSS"), + STM32_FUNCTION(9, "UART4_DE UART4_RTS"), + STM32_FUNCTION(12, "UART7_TX"), + STM32_FUNCTION(13, "FMC_D15"), + STM32_FUNCTION(14, "LTDC_R5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(16, "PB0"), + STM32_FUNCTION(0, "GPIOB0"), + STM32_FUNCTION(2, "TIM1_CH2N"), + STM32_FUNCTION(3, "TIM3_CH3"), + STM32_FUNCTION(4, "TIM9_CH1"), + STM32_FUNCTION(6, "I2S1_CK SPI1_SCK"), + STM32_FUNCTION(9, "UART4_CTS"), + STM32_FUNCTION(12, "ETH_MII_TXD0 ETH_RMII_TXD0"), + STM32_FUNCTION(15, "LTDC_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(17, "PB1"), + STM32_FUNCTION(0, "GPIOB1"), + STM32_FUNCTION(2, "TIM1_CH3N"), + STM32_FUNCTION(3, "TIM3_CH4"), + STM32_FUNCTION(4, "TIM9_CH2"), + STM32_FUNCTION(10, "FDCAN2_TX"), + STM32_FUNCTION(11, "LTDC_G2"), + STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"), + STM32_FUNCTION(13, "FMC_NOE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(18, "PB2"), + STM32_FUNCTION(0, "GPIOB2"), + STM32_FUNCTION(3, "SAI1_D1"), + STM32_FUNCTION(7, "SAI1_SD_A"), + STM32_FUNCTION(8, "SPI3_MOSI"), + STM32_FUNCTION(11, "LTDC_B2"), + STM32_FUNCTION(13, "FMC_NWE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(19, "PB3"), + STM32_FUNCTION(0, "GPIOB3"), + STM32_FUNCTION(1, "DEBUG_JTDO_SWO"), + STM32_FUNCTION(2, "TIM2_CH2"), + STM32_FUNCTION(4, "LPTIM4_IN1"), + STM32_FUNCTION(5, "DCMIPP_HSYNC"), + STM32_FUNCTION(6, "I2S1_CK SPI1_SCK"), + STM32_FUNCTION(7, "I2S3_CK SPI3_SCK"), + STM32_FUNCTION(9, "I2S6_CK SPI6_SCK"), + STM32_FUNCTION(10, "SDMMC2_D2"), + STM32_FUNCTION(12, "UART7_RX"), + STM32_FUNCTION(13, "FMC_D14"), + STM32_FUNCTION(14, "LTDC_R4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(20, "PB4"), + STM32_FUNCTION(0, "GPIOB4"), + STM32_FUNCTION(1, "DEBUG_NJTRST"), + STM32_FUNCTION(2, "TIM16_BKIN"), + STM32_FUNCTION(3, "TIM3_CH1"), + STM32_FUNCTION(4, "LPTIM4_ETR"), + STM32_FUNCTION(5, "DCMIPP_VSYNC"), + STM32_FUNCTION(6, "SPI1_MISO"), + STM32_FUNCTION(7, "SPI3_MISO"), + STM32_FUNCTION(8, "I2S2_WS SPI2_NSS"), + STM32_FUNCTION(9, "SPI6_MISO"), + STM32_FUNCTION(10, "SDMMC2_D3"), + STM32_FUNCTION(12, "UART7_TX"), + STM32_FUNCTION(13, "FMC_D13"), + STM32_FUNCTION(14, "LTDC_R3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(21, "PB5"), + STM32_FUNCTION(0, "GPIOB5"), + STM32_FUNCTION(2, "TIM17_BKIN"), + STM32_FUNCTION(3, "TIM3_CH2"), + STM32_FUNCTION(4, "LPTIM4_OUT"), + STM32_FUNCTION(5, "I2C1_SMBA"), + STM32_FUNCTION(6, "SPI1_MOSI"), + STM32_FUNCTION(8, "SPI3_MOSI"), + STM32_FUNCTION(9, "SPI6_MOSI"), + STM32_FUNCTION(10, "FDCAN2_RX"), + STM32_FUNCTION(11, "LTDC_R2"), + STM32_FUNCTION(12, "ETH_PPS_OUT"), + STM32_FUNCTION(13, "FMC_D12"), + STM32_FUNCTION(14, "DCMIPP_D10"), + STM32_FUNCTION(15, "UART5_RX"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(22, "PB6"), + STM32_FUNCTION(0, "GPIOB6"), + STM32_FUNCTION(2, "TIM16_CH1N"), + STM32_FUNCTION(3, "TIM4_CH1"), + STM32_FUNCTION(5, "I2C1_SCL I3C1_SCL"), + STM32_FUNCTION(8, "USART1_TX"), + STM32_FUNCTION(9, "LPUART1_TX"), + STM32_FUNCTION(10, "FDCAN2_TX"), + STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"), + STM32_FUNCTION(13, "FMC_SDNE1"), + STM32_FUNCTION(14, "DCMIPP_D5"), + STM32_FUNCTION(15, "UART5_TX"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(23, "PB7"), + STM32_FUNCTION(0, "GPIOB7"), + STM32_FUNCTION(2, "TIM17_CH1N"), + STM32_FUNCTION(3, "TIM4_CH2"), + STM32_FUNCTION(5, "I2C1_SDA I3C1_SDA"), + STM32_FUNCTION(6, "DCMIPP_D1"), + STM32_FUNCTION(8, "USART1_RX"), + STM32_FUNCTION(9, "LPUART1_RX"), + STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"), + STM32_FUNCTION(13, "FMC_SDCKE1"), + STM32_FUNCTION(14, "DCMIPP_VSYNC"), + STM32_FUNCTION(15, "UART5_TX"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(24, "PB8"), + STM32_FUNCTION(0, "GPIOB8"), + STM32_FUNCTION(2, "TIM16_CH1"), + STM32_FUNCTION(3, "TIM4_CH3"), + STM32_FUNCTION(5, "I2C1_SCL I3C1_SCL"), + STM32_FUNCTION(8, "SDMMC1_CKIN"), + STM32_FUNCTION(9, "UART4_RX"), + STM32_FUNCTION(10, "FDCAN1_RX"), + STM32_FUNCTION(11, "SDMMC2_D4"), + STM32_FUNCTION(12, "ETH_MII_TXD3"), + STM32_FUNCTION(13, "SDMMC1_D4"), + STM32_FUNCTION(14, "DCMIPP_D6"), + STM32_FUNCTION(15, "FMC_D9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(25, "PB9"), + STM32_FUNCTION(0, "GPIOB9"), + STM32_FUNCTION(2, "TIM17_CH1"), + STM32_FUNCTION(3, "TIM4_CH4"), + STM32_FUNCTION(5, "I2C1_SDA I3C1_SDA"), + STM32_FUNCTION(6, "I2S2_WS SPI2_NSS"), + STM32_FUNCTION(8, "SDMMC1_CDIR"), + STM32_FUNCTION(9, "UART4_TX"), + STM32_FUNCTION(10, "FDCAN1_TX"), + STM32_FUNCTION(11, "SDMMC2_D5"), + STM32_FUNCTION(13, "SDMMC1_D5"), + STM32_FUNCTION(14, "DCMIPP_D7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(26, "PB10"), + STM32_FUNCTION(0, "GPIOB10"), + STM32_FUNCTION(2, "TIM2_CH3"), + STM32_FUNCTION(4, "LPTIM2_IN1"), + STM32_FUNCTION(5, "I2C2_SCL"), + STM32_FUNCTION(6, "I2S2_CK SPI2_SCK"), + STM32_FUNCTION(8, "USART3_TX"), + STM32_FUNCTION(12, "ETH_MII_RX_ER"), + STM32_FUNCTION(13, "FMC_D11"), + STM32_FUNCTION(14, "LTDC_G7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(27, "PB11"), + STM32_FUNCTION(0, "GPIOB11"), + STM32_FUNCTION(2, "TIM2_CH4"), + STM32_FUNCTION(4, "LPTIM2_ETR"), + STM32_FUNCTION(5, "I2C2_SDA"), + STM32_FUNCTION(8, "USART3_RX"), + STM32_FUNCTION(12, "ETH_MII_TX_EN ETH_RMII_TX_EN"), + STM32_FUNCTION(13, "FMC_D10"), + STM32_FUNCTION(14, "LTDC_G6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(28, "PB12"), + STM32_FUNCTION(0, "GPIOB12"), + STM32_FUNCTION(2, "TIM1_BKIN"), + STM32_FUNCTION(4, "LPTIM2_IN2"), + STM32_FUNCTION(5, "I2C2_SMBA"), + STM32_FUNCTION(6, "I2S2_WS SPI2_NSS"), + STM32_FUNCTION(10, "FDCAN2_RX"), + STM32_FUNCTION(13, "FMC_D9"), + STM32_FUNCTION(14, "LTDC_G5"), + STM32_FUNCTION(15, "UART5_RX"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(29, "PB13"), + STM32_FUNCTION(0, "GPIOB13"), + STM32_FUNCTION(2, "TIM1_CH1N"), + STM32_FUNCTION(4, "LPTIM2_CH1"), + STM32_FUNCTION(6, "I2S2_CK SPI2_SCK"), + STM32_FUNCTION(7, "SDMMC1_D0"), + STM32_FUNCTION(8, "USART3_CTS"), + STM32_FUNCTION(10, "FDCAN2_TX"), + STM32_FUNCTION(11, "LTDC_G4"), + STM32_FUNCTION(12, "ETH_MII_RXD3"), + STM32_FUNCTION(13, "FMC_D8"), + STM32_FUNCTION(14, "DCMIPP_D2"), + STM32_FUNCTION(15, "UART5_TX"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(30, "PB14"), + STM32_FUNCTION(0, "GPIOB14"), + STM32_FUNCTION(2, "TIM1_CH2N"), + STM32_FUNCTION(3, "TIM12_CH1"), + STM32_FUNCTION(4, "LPTIM2_CH2"), + STM32_FUNCTION(5, "USART1_TX"), + STM32_FUNCTION(6, "SPI2_MISO"), + STM32_FUNCTION(8, "USART3_DE USART3_RTS"), + STM32_FUNCTION(9, "UART4_DE UART4_RTS"), + STM32_FUNCTION(10, "SDMMC2_D0"), + STM32_FUNCTION(13, "FMC_NE1"), + STM32_FUNCTION(14, "LTDC_DE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(31, "PB15"), + STM32_FUNCTION(0, "GPIOB15"), + STM32_FUNCTION(2, "TIM1_CH3N"), + STM32_FUNCTION(3, "TIM12_CH2"), + STM32_FUNCTION(5, "USART1_RX"), + STM32_FUNCTION(6, "SPI2_MOSI"), + STM32_FUNCTION(9, "UART4_CTS"), + STM32_FUNCTION(10, "SDMMC2_D1"), + STM32_FUNCTION(11, "LTDC_G7"), + STM32_FUNCTION(13, "FMC_A20"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(32, "PC0"), + STM32_FUNCTION(0, "GPIOC0"), + STM32_FUNCTION(9, "SAI2_FS_B"), + STM32_FUNCTION(13, "FMC_NBL1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(33, "PC1"), + STM32_FUNCTION(0, "GPIOC1"), + STM32_FUNCTION(1, "TRACED0"), + STM32_FUNCTION(3, "SAI1_D1"), + STM32_FUNCTION(6, "SPI2_MOSI"), + STM32_FUNCTION(7, "SAI1_SD_A"), + STM32_FUNCTION(8, "FMC_A16"), + STM32_FUNCTION(10, "SDMMC2_CK"), + STM32_FUNCTION(12, "ETH_MDC"), + STM32_FUNCTION(13, "FMC_A0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(34, "PC2"), + STM32_FUNCTION(0, "GPIOC2"), + STM32_FUNCTION(2, "TIM1_CH1"), + STM32_FUNCTION(6, "SPI2_MISO"), + STM32_FUNCTION(10, "FMC_A17"), + STM32_FUNCTION(12, "ETH_MII_TXD2"), + STM32_FUNCTION(13, "FMC_A1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(35, "PC3"), + STM32_FUNCTION(0, "GPIOC3"), + STM32_FUNCTION(2, "TIM1_CH2"), + STM32_FUNCTION(6, "SPI2_MOSI"), + STM32_FUNCTION(8, "FMC_A18"), + STM32_FUNCTION(12, "ETH_MII_TX_CLK"), + STM32_FUNCTION(13, "FMC_A2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(36, "PC4"), + STM32_FUNCTION(0, "GPIOC4"), + STM32_FUNCTION(6, "I2S1_MCK"), + STM32_FUNCTION(8, "FMC_A19"), + STM32_FUNCTION(12, "ETH_MII_RXD0 ETH_RMII_RXD0"), + STM32_FUNCTION(13, "FMC_A3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(37, "PC5"), + STM32_FUNCTION(0, "GPIOC5"), + STM32_FUNCTION(3, "SAI1_D3"), + STM32_FUNCTION(5, "DCMIPP_D15"), + STM32_FUNCTION(8, "FMC_A21"), + STM32_FUNCTION(12, "ETH_MII_RXD1 ETH_RMII_RXD1"), + STM32_FUNCTION(13, "FMC_A5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(38, "PC6"), + STM32_FUNCTION(0, "GPIOC6"), + STM32_FUNCTION(3, "TIM3_CH1"), + STM32_FUNCTION(4, "TIM9_CH1"), + STM32_FUNCTION(6, "I2S2_MCK"), + STM32_FUNCTION(9, "SDMMC1_D0DIR"), + STM32_FUNCTION(11, "SDMMC2_D6"), + STM32_FUNCTION(12, "SDMMC1_D6"), + STM32_FUNCTION(14, "DCMIPP_D0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(39, "PC7"), + STM32_FUNCTION(0, "GPIOC7"), + STM32_FUNCTION(3, "TIM3_CH2"), + STM32_FUNCTION(4, "TIM9_CH2"), + STM32_FUNCTION(7, "I2S3_MCK"), + STM32_FUNCTION(9, "SDMMC1_D123DIR"), + STM32_FUNCTION(11, "SDMMC2_D7"), + STM32_FUNCTION(12, "SDMMC1_D7"), + STM32_FUNCTION(14, "DCMIPP_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(40, "PC8"), + STM32_FUNCTION(0, "GPIOC8"), + STM32_FUNCTION(1, "TRACED1"), + STM32_FUNCTION(3, "TIM3_CH3"), + STM32_FUNCTION(5, "I2C3_SMBA"), + STM32_FUNCTION(9, "UART5_DE UART5_RTS"), + STM32_FUNCTION(12, "SDMMC1_D0"), + STM32_FUNCTION(14, "DCMIPP_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(41, "PC9"), + STM32_FUNCTION(0, "GPIOC9"), + STM32_FUNCTION(1, "RCC_MCO_2"), + STM32_FUNCTION(3, "TIM3_CH4"), + STM32_FUNCTION(5, "I2C3_SDA"), + STM32_FUNCTION(9, "UART5_CTS"), + STM32_FUNCTION(12, "SDMMC1_D1"), + STM32_FUNCTION(14, "DCMIPP_D3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(42, "PC10"), + STM32_FUNCTION(0, "GPIOC10"), + STM32_FUNCTION(2, "TIM1_BKIN"), + STM32_FUNCTION(7, "I2S3_CK SPI3_SCK"), + STM32_FUNCTION(8, "USART3_TX"), + STM32_FUNCTION(9, "UART4_TX"), + STM32_FUNCTION(13, "SDMMC1_D2"), + STM32_FUNCTION(14, "DCMIPP_D14"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(43, "PC11"), + STM32_FUNCTION(0, "GPIOC11"), + STM32_FUNCTION(7, "SPI3_MISO"), + STM32_FUNCTION(8, "USART3_RX"), + STM32_FUNCTION(9, "UART4_RX"), + STM32_FUNCTION(12, "SDMMC1_D3"), + STM32_FUNCTION(14, "DCMIPP_D4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(44, "PC12"), + STM32_FUNCTION(0, "GPIOC12"), + STM32_FUNCTION(1, "TRACED3"), + STM32_FUNCTION(2, "TIM1_CH4"), + STM32_FUNCTION(3, "TIM15_CH1"), + STM32_FUNCTION(6, "I2S6_CK SPI6_SCK"), + STM32_FUNCTION(7, "SPI3_MOSI"), + STM32_FUNCTION(9, "UART5_TX"), + STM32_FUNCTION(12, "SDMMC1_CK"), + STM32_FUNCTION(14, "DCMIPP_D9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(45, "PC13"), + STM32_FUNCTION(0, "GPIOC13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(46, "PC14"), + STM32_FUNCTION(0, "GPIOC14"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(47, "PC15"), + STM32_FUNCTION(0, "GPIOC15"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(48, "PD0"), + STM32_FUNCTION(0, "GPIOD0"), + STM32_FUNCTION(8, "FMC_A22"), + STM32_FUNCTION(9, "UART4_RX"), + STM32_FUNCTION(10, "FDCAN1_RX"), + STM32_FUNCTION(13, "FMC_A6"), + STM32_FUNCTION(14, "DCMIPP_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(49, "PD1"), + STM32_FUNCTION(0, "GPIOD1"), + STM32_FUNCTION(8, "FMC_A23"), + STM32_FUNCTION(9, "UART4_TX"), + STM32_FUNCTION(10, "FDCAN1_TX"), + STM32_FUNCTION(13, "FMC_A7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(50, "PD2"), + STM32_FUNCTION(0, "GPIOD2"), + STM32_FUNCTION(1, "TRACED2"), + STM32_FUNCTION(5, "TIM15_BKIN"), + STM32_FUNCTION(9, "UART5_RX"), + STM32_FUNCTION(12, "SDMMC1_CMD"), + STM32_FUNCTION(14, "DCMIPP_D11"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(51, "PD3"), + STM32_FUNCTION(0, "GPIOD3"), + STM32_FUNCTION(2, "TIM1_CH3N"), + STM32_FUNCTION(6, "I2S2_CK SPI2_SCK"), + STM32_FUNCTION(8, "USART2_CTS"), + STM32_FUNCTION(13, "FMC_NWAIT"), + STM32_FUNCTION(14, "DCMIPP_D5"), + STM32_FUNCTION(15, "LTDC_B1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(52, "PD4"), + STM32_FUNCTION(0, "GPIOD4"), + STM32_FUNCTION(6, "DCMIPP_HSYNC"), + STM32_FUNCTION(8, "USART2_DE USART2_RTS"), + STM32_FUNCTION(13, "FMC_NL"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(53, "PD5"), + STM32_FUNCTION(0, "GPIOD5"), + STM32_FUNCTION(2, "TIM1_CH4N"), + STM32_FUNCTION(6, "DCMIPP_PIXCLK"), + STM32_FUNCTION(8, "USART2_TX"), + STM32_FUNCTION(11, "FMC_NCE"), + STM32_FUNCTION(13, "FMC_NE2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(54, "PD6"), + STM32_FUNCTION(0, "GPIOD6"), + STM32_FUNCTION(3, "SAI1_D1"), + STM32_FUNCTION(6, "SPI3_MOSI"), + STM32_FUNCTION(7, "SAI1_SCK_A"), + STM32_FUNCTION(8, "USART2_RX"), + STM32_FUNCTION(11, "FMC_INT"), + STM32_FUNCTION(12, "SDMMC2_CK"), + STM32_FUNCTION(13, "FMC_NE3"), + STM32_FUNCTION(14, "DCMIPP_D10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(55, "PD7"), + STM32_FUNCTION(0, "GPIOD7"), + STM32_FUNCTION(5, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"), + STM32_FUNCTION(6, "SPI1_MOSI"), + STM32_FUNCTION(12, "SDMMC2_CMD"), + STM32_FUNCTION(13, "FMC_D8"), + STM32_FUNCTION(14, "DCMIPP_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(56, "PD8"), + STM32_FUNCTION(0, "GPIOD8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(57, "PD9"), + STM32_FUNCTION(0, "GPIOD9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(58, "PD10"), + STM32_FUNCTION(0, "GPIOD10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(59, "PD11"), + STM32_FUNCTION(0, "GPIOD11"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(60, "PD12"), + STM32_FUNCTION(0, "GPIOD12"), + STM32_FUNCTION(2, "LPTIM1_IN1"), + STM32_FUNCTION(3, "TIM4_CH1"), + STM32_FUNCTION(4, "LPTIM2_IN1"), + STM32_FUNCTION(8, "USART3_DE USART3_RTS"), + STM32_FUNCTION(11, "SAI2_FS_A"), + STM32_FUNCTION(13, "FMC_NE1"), + STM32_FUNCTION(14, "DCMIPP_D12"), + STM32_FUNCTION(15, "LTDC_DE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(61, "PD13"), + STM32_FUNCTION(0, "GPIOD13"), + STM32_FUNCTION(2, "LPTIM1_CH1"), + STM32_FUNCTION(3, "TIM4_CH2"), + STM32_FUNCTION(9, "SAI2_SCK_A"), + STM32_FUNCTION(11, "FMC_INT"), + STM32_FUNCTION(14, "DCMIPP_D13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(62, "PD14"), + STM32_FUNCTION(0, "GPIOD14"), + STM32_FUNCTION(2, "LPTIM1_CH2"), + STM32_FUNCTION(3, "TIM4_CH3"), + STM32_FUNCTION(4, "LPTIM2_CH1"), + STM32_FUNCTION(6, "DCMIPP_D7"), + STM32_FUNCTION(9, "UART8_CTS"), + STM32_FUNCTION(13, "FMC_D17"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(63, "PD15"), + STM32_FUNCTION(0, "GPIOD15"), + STM32_FUNCTION(3, "TIM4_CH4"), + STM32_FUNCTION(4, "LPTIM5_OUT"), + STM32_FUNCTION(6, "DCMIPP_D9"), + STM32_FUNCTION(9, "UART8_DE UART8_RTS"), + STM32_FUNCTION(13, "FMC_D18"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(64, "PE0"), + STM32_FUNCTION(0, "GPIOE0"), + STM32_FUNCTION(2, "LPTIM1_ETR"), + STM32_FUNCTION(4, "LPTIM2_ETR"), + STM32_FUNCTION(9, "UART8_RX"), + STM32_FUNCTION(11, "SAI2_MCLK_A"), + STM32_FUNCTION(13, "FMC_D9"), + STM32_FUNCTION(14, "DCMIPP_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(65, "PE1"), + STM32_FUNCTION(0, "GPIOE1"), + STM32_FUNCTION(2, "LPTIM1_IN2"), + STM32_FUNCTION(4, "LPTIM2_CH2"), + STM32_FUNCTION(9, "UART8_TX"), + STM32_FUNCTION(13, "FMC_D10"), + STM32_FUNCTION(14, "DCMIPP_D3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(66, "PE2"), + STM32_FUNCTION(0, "GPIOE2"), + STM32_FUNCTION(1, "TRACECLK"), + STM32_FUNCTION(3, "SAI1_CK1"), + STM32_FUNCTION(4, "LPTIM5_IN1"), + STM32_FUNCTION(6, "SPI4_SCK"), + STM32_FUNCTION(7, "SAI1_MCLK_A"), + STM32_FUNCTION(12, "ETH_MII_TXD3"), + STM32_FUNCTION(13, "FMC_D11"), + STM32_FUNCTION(15, "TIM1_CH2N"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(67, "PE3"), + STM32_FUNCTION(0, "GPIOE3"), + STM32_FUNCTION(1, "TRACED0"), + STM32_FUNCTION(4, "LPTIM5_ETR"), + STM32_FUNCTION(5, "TIM15_BKIN"), + STM32_FUNCTION(7, "SAI1_SD_B"), + STM32_FUNCTION(12, "ETH_MII_RXD3"), + STM32_FUNCTION(13, "FMC_D12"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(68, "PE4"), + STM32_FUNCTION(0, "GPIOE4"), + STM32_FUNCTION(1, "TRACED1"), + STM32_FUNCTION(3, "SAI1_D2"), + STM32_FUNCTION(5, "TIM15_CH1N"), + STM32_FUNCTION(6, "SPI4_NSS"), + STM32_FUNCTION(7, "SAI1_FS_A"), + STM32_FUNCTION(13, "FMC_D13"), + STM32_FUNCTION(14, "DCMIPP_D4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(69, "PE5"), + STM32_FUNCTION(0, "GPIOE5"), + STM32_FUNCTION(1, "TRACED2"), + STM32_FUNCTION(3, "SAI1_CK2"), + STM32_FUNCTION(5, "TIM15_CH1"), + STM32_FUNCTION(6, "SPI4_MISO"), + STM32_FUNCTION(7, "SAI1_SCK_A"), + STM32_FUNCTION(13, "FMC_D14"), + STM32_FUNCTION(14, "DCMIPP_D6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(70, "PE6"), + STM32_FUNCTION(0, "GPIOE6"), + STM32_FUNCTION(1, "TRACED3"), + STM32_FUNCTION(2, "TIM1_BKIN2"), + STM32_FUNCTION(3, "SAI1_D1"), + STM32_FUNCTION(5, "TIM15_CH2"), + STM32_FUNCTION(6, "SPI4_MOSI"), + STM32_FUNCTION(7, "SAI1_SD_A"), + STM32_FUNCTION(11, "SAI2_MCLK_B"), + STM32_FUNCTION(13, "FMC_D15"), + STM32_FUNCTION(14, "DCMIPP_D7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(71, "PE7"), + STM32_FUNCTION(0, "GPIOE7"), + STM32_FUNCTION(8, "UART7_RX"), + STM32_FUNCTION(10, "FMC_A20"), + STM32_FUNCTION(11, "SAI2_SD_B"), + STM32_FUNCTION(13, "FMC_A4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(72, "PE8"), + STM32_FUNCTION(0, "GPIOE8"), + STM32_FUNCTION(2, "TIM1_CH1N"), + STM32_FUNCTION(8, "UART7_TX"), + STM32_FUNCTION(13, "FMC_A12"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(73, "PE9"), + STM32_FUNCTION(0, "GPIOE9"), + STM32_FUNCTION(2, "TIM1_CH1"), + STM32_FUNCTION(8, "UART7_DE UART7_RTS"), + STM32_FUNCTION(13, "FMC_A14"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(74, "PE10"), + STM32_FUNCTION(0, "GPIOE10"), + STM32_FUNCTION(2, "TIM1_CH2N"), + STM32_FUNCTION(8, "UART7_CTS"), + STM32_FUNCTION(13, "FMC_A15"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(75, "PE11"), + STM32_FUNCTION(0, "GPIOE11"), + STM32_FUNCTION(2, "TIM1_CH2"), + STM32_FUNCTION(6, "SPI4_NSS"), + STM32_FUNCTION(11, "SAI2_SD_B"), + STM32_FUNCTION(12, "LTDC_VSYNC"), + STM32_FUNCTION(13, "FMC_SDNWE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(76, "PE12"), + STM32_FUNCTION(0, "GPIOE12"), + STM32_FUNCTION(2, "TIM1_CH3N"), + STM32_FUNCTION(6, "SPI4_SCK"), + STM32_FUNCTION(11, "SAI2_SCK_B"), + STM32_FUNCTION(13, "FMC_SDNRAS"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(77, "PE13"), + STM32_FUNCTION(0, "GPIOE13"), + STM32_FUNCTION(2, "TIM1_CH3"), + STM32_FUNCTION(6, "SPI4_MISO"), + STM32_FUNCTION(11, "SAI2_FS_B"), + STM32_FUNCTION(13, "FMC_SDNCAS"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(78, "PE14"), + STM32_FUNCTION(0, "GPIOE14"), + STM32_FUNCTION(2, "TIM1_CH4"), + STM32_FUNCTION(6, "SPI4_MOSI"), + STM32_FUNCTION(11, "SAI2_MCLK_B"), + STM32_FUNCTION(13, "FMC_SDNE0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(79, "PE15"), + STM32_FUNCTION(0, "GPIOE15"), + STM32_FUNCTION(2, "TIM1_BKIN"), + STM32_FUNCTION(13, "FMC_SDCKE0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(80, "PF0"), + STM32_FUNCTION(0, "GPIOF0"), + STM32_FUNCTION(5, "I2C2_SDA"), + STM32_FUNCTION(12, "LTDC_R2"), + STM32_FUNCTION(13, "FMC_A8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(81, "PF1"), + STM32_FUNCTION(0, "GPIOF1"), + STM32_FUNCTION(5, "I2C2_SCL"), + STM32_FUNCTION(13, "FMC_A9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(82, "PF2"), + STM32_FUNCTION(0, "GPIOF2"), + STM32_FUNCTION(5, "I2C2_SMBA"), + STM32_FUNCTION(6, "DCMIPP_D14"), + STM32_FUNCTION(13, "FMC_A10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(83, "PF3"), + STM32_FUNCTION(0, "GPIOF3"), + STM32_FUNCTION(6, "DCMIPP_D9"), + STM32_FUNCTION(12, "ETH_MII_CRS"), + STM32_FUNCTION(13, "FMC_A11"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(84, "PF4"), + STM32_FUNCTION(0, "GPIOF4"), + STM32_FUNCTION(6, "DCMIPP_D8"), + STM32_FUNCTION(13, "FMC_A13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(85, "PF5"), + STM32_FUNCTION(0, "GPIOF5"), + STM32_FUNCTION(6, "DCMIPP_D15"), + STM32_FUNCTION(11, "FMC_CLE"), + STM32_FUNCTION(12, "ETH_MII_RXD2"), + STM32_FUNCTION(13, "FMC_A16"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(86, "PF6"), + STM32_FUNCTION(0, "GPIOF6"), + STM32_FUNCTION(2, "TIM16_CH1"), + STM32_FUNCTION(6, "SPI5_NSS"), + STM32_FUNCTION(7, "SAI1_SD_B"), + STM32_FUNCTION(8, "UART7_RX"), + STM32_FUNCTION(11, "FMC_ALE"), + STM32_FUNCTION(13, "FMC_A17"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(87, "PF7"), + STM32_FUNCTION(0, "GPIOF7"), + STM32_FUNCTION(2, "TIM17_CH1"), + STM32_FUNCTION(6, "SPI5_SCK"), + STM32_FUNCTION(7, "SAI1_MCLK_B"), + STM32_FUNCTION(8, "UART7_TX"), + STM32_FUNCTION(13, "FMC_A18"), + STM32_FUNCTION(14, "LTDC_G0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(88, "PF8"), + STM32_FUNCTION(0, "GPIOF8"), + STM32_FUNCTION(2, "TIM16_CH1N"), + STM32_FUNCTION(5, "DCMIPP_PIXCLK"), + STM32_FUNCTION(6, "SPI5_MISO"), + STM32_FUNCTION(7, "SAI1_SCK_B"), + STM32_FUNCTION(8, "UART7_DE UART7_RTS"), + STM32_FUNCTION(10, "TIM13_CH1"), + STM32_FUNCTION(13, "FMC_A19"), + STM32_FUNCTION(14, "LTDC_G1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(89, "PF9"), + STM32_FUNCTION(0, "GPIOF9"), + STM32_FUNCTION(2, "TIM17_CH1N"), + STM32_FUNCTION(6, "SPI5_MOSI"), + STM32_FUNCTION(7, "SAI1_FS_B"), + STM32_FUNCTION(8, "UART7_CTS"), + STM32_FUNCTION(10, "TIM14_CH1"), + STM32_FUNCTION(13, "FMC_A21"), + STM32_FUNCTION(14, "LTDC_R0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(90, "PF10"), + STM32_FUNCTION(0, "GPIOF10"), + STM32_FUNCTION(2, "TIM16_BKIN"), + STM32_FUNCTION(3, "SAI1_D3"), + STM32_FUNCTION(5, "DCMIPP_D15"), + STM32_FUNCTION(13, "FMC_A22"), + STM32_FUNCTION(14, "DCMIPP_D11"), + STM32_FUNCTION(15, "LTDC_R1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(91, "PF11"), + STM32_FUNCTION(0, "GPIOF11"), + STM32_FUNCTION(6, "SPI5_MOSI"), + STM32_FUNCTION(11, "SAI2_SD_B"), + STM32_FUNCTION(13, "FMC_A23"), + STM32_FUNCTION(14, "DCMIPP_D12"), + STM32_FUNCTION(15, "LTDC_B0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(92, "PF12"), + STM32_FUNCTION(0, "GPIOF12"), + STM32_FUNCTION(5, "USART1_RX"), + STM32_FUNCTION(6, "SPI5_MISO"), + STM32_FUNCTION(13, "FMC_D19"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(93, "PF13"), + STM32_FUNCTION(0, "GPIOF13"), + STM32_FUNCTION(5, "USART1_TX"), + STM32_FUNCTION(6, "SPI5_NSS"), + STM32_FUNCTION(13, "FMC_D20"), + STM32_FUNCTION(14, "DCMIPP_D10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(94, "PF14"), + STM32_FUNCTION(0, "GPIOF14"), + STM32_FUNCTION(5, "USART1_CTS"), + STM32_FUNCTION(6, "SPI5_MOSI"), + STM32_FUNCTION(13, "FMC_A24"), + STM32_FUNCTION(14, "LTDC_G0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(95, "PF15"), + STM32_FUNCTION(0, "GPIOF15"), + STM32_FUNCTION(5, "USART1_DE USART1_RTS"), + STM32_FUNCTION(6, "SPI5_SCK"), + STM32_FUNCTION(13, "FMC_A25"), + STM32_FUNCTION(14, "LTDC_G1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(96, "PG0"), + STM32_FUNCTION(0, "GPIOG0"), + STM32_FUNCTION(2, "TIM1_CH4N"), + STM32_FUNCTION(14, "LTDC_R7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(97, "PG1"), + STM32_FUNCTION(0, "GPIOG1"), + STM32_FUNCTION(14, "LTDC_R6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(98, "PG2"), + STM32_FUNCTION(0, "GPIOG2"), + STM32_FUNCTION(14, "LTDC_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(99, "PG3"), + STM32_FUNCTION(0, "GPIOG3"), + STM32_FUNCTION(6, "DCMIPP_HSYNC"), + STM32_FUNCTION(12, "ETH_PPS_OUT"), + STM32_FUNCTION(13, "FMC_D21"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(100, "PG4"), + STM32_FUNCTION(0, "GPIOG4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(101, "PG5"), + STM32_FUNCTION(0, "GPIOG5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(102, "PG6"), + STM32_FUNCTION(0, "GPIOG6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(103, "PG7"), + STM32_FUNCTION(0, "GPIOG7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(104, "PG8"), + STM32_FUNCTION(0, "GPIOG8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(105, "PG9"), + STM32_FUNCTION(0, "GPIOG9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(106, "PG10"), + STM32_FUNCTION(0, "GPIOG10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(107, "PG11"), + STM32_FUNCTION(0, "GPIOG11"), + STM32_FUNCTION(2, "LPTIM1_IN2"), + STM32_FUNCTION(6, "I2S1_CK SPI1_SCK"), + STM32_FUNCTION(11, "SDMMC2_D2"), + STM32_FUNCTION(12, "ETH_MII_TX_EN ETH_RMII_TX_EN"), + STM32_FUNCTION(13, "FMC_D28"), + STM32_FUNCTION(14, "DCMIPP_D3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(108, "PG12"), + STM32_FUNCTION(0, "GPIOG12"), + STM32_FUNCTION(2, "LPTIM1_IN1"), + STM32_FUNCTION(6, "SPI6_MISO"), + STM32_FUNCTION(11, "SDMMC2_D3"), + STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"), + STM32_FUNCTION(13, "FMC_D29"), + STM32_FUNCTION(14, "LTDC_G1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(109, "PG13"), + STM32_FUNCTION(0, "GPIOG13"), + STM32_FUNCTION(1, "TRACED0"), + STM32_FUNCTION(2, "LPTIM1_CH1"), + STM32_FUNCTION(6, "I2S6_CK SPI6_SCK"), + STM32_FUNCTION(11, "SDMMC2_D6"), + STM32_FUNCTION(12, "ETH_MII_TXD0 ETH_RMII_TXD0"), + STM32_FUNCTION(13, "FMC_D30"), + STM32_FUNCTION(14, "LTDC_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(110, "PG14"), + STM32_FUNCTION(0, "GPIOG14"), + STM32_FUNCTION(1, "TRACED1"), + STM32_FUNCTION(2, "LPTIM1_ETR"), + STM32_FUNCTION(6, "SPI6_MOSI"), + STM32_FUNCTION(11, "SDMMC2_D7"), + STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"), + STM32_FUNCTION(13, "FMC_D31"), + STM32_FUNCTION(14, "LTDC_B1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(111, "PG15"), + STM32_FUNCTION(0, "GPIOG15"), + STM32_FUNCTION(2, "LPTIM1_CH2"), + STM32_FUNCTION(13, "FMC_NBL3"), + STM32_FUNCTION(14, "DCMIPP_D13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(112, "PH0"), + STM32_FUNCTION(0, "GPIOH0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(113, "PH1"), + STM32_FUNCTION(0, "GPIOH1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(114, "PH2"), + STM32_FUNCTION(0, "GPIOH2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(115, "PH3"), + STM32_FUNCTION(0, "GPIOH3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(116, "PH4"), + STM32_FUNCTION(0, "GPIOH4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(117, "PH5"), + STM32_FUNCTION(0, "GPIOH5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(118, "PH6"), + STM32_FUNCTION(0, "GPIOH6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(119, "PH7"), + STM32_FUNCTION(0, "GPIOH7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(120, "PH8"), + STM32_FUNCTION(0, "GPIOH8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(121, "PH9"), + STM32_FUNCTION(0, "GPIOH9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(122, "PH10"), + STM32_FUNCTION(0, "GPIOH10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(123, "PH11"), + STM32_FUNCTION(0, "GPIOH11"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(124, "PH12"), + STM32_FUNCTION(0, "GPIOH12"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(125, "PH13"), + STM32_FUNCTION(0, "GPIOH13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(126, "PH14"), + STM32_FUNCTION(0, "GPIOH14"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(127, "PH15"), + STM32_FUNCTION(0, "GPIOH15"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(192, "PM0"), + STM32_FUNCTION(0, "GPIOM0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(193, "PM1"), + STM32_FUNCTION(0, "GPIOM1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(194, "PM2"), + STM32_FUNCTION(0, "GPIOM2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(195, "PM3"), + STM32_FUNCTION(0, "GPIOM3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(196, "PM4"), + STM32_FUNCTION(0, "GPIOM4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(197, "PM5"), + STM32_FUNCTION(0, "GPIOM5"), + STM32_FUNCTION(11, "USB_OTG_HS_DM"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(198, "PM6"), + STM32_FUNCTION(0, "GPIOM6"), + STM32_FUNCTION(11, "USB_OTG_HS_DP"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(199, "PM7"), + STM32_FUNCTION(0, "GPIOM7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(200, "PM8"), + STM32_FUNCTION(0, "GPIOM8"), + STM32_FUNCTION(8, "UART7_RX"), + STM32_FUNCTION(11, "USB_OTG_HS_VBUS"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(201, "PM9"), + STM32_FUNCTION(0, "GPIOM9"), + STM32_FUNCTION(8, "UART7_TX"), + STM32_FUNCTION(11, "USB_OTG_HS_ID"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(202, "PM10"), + STM32_FUNCTION(0, "GPIOM10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(203, "PM11"), + STM32_FUNCTION(0, "GPIOM11"), + STM32_FUNCTION(6, "SPI5_SCK"), + STM32_FUNCTION(11, "USB_OTG_FS_DP"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(204, "PM12"), + STM32_FUNCTION(0, "GPIOM12"), + STM32_FUNCTION(6, "SPI5_NSS"), + STM32_FUNCTION(11, "USB_OTG_FS_DM"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(205, "PM13"), + STM32_FUNCTION(0, "GPIOM13"), + STM32_FUNCTION(6, "SPI5_MOSI"), + STM32_FUNCTION(11, "USB_OTG_FS_ID"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(206, "PM14"), + STM32_FUNCTION(0, "GPIOM14"), + STM32_FUNCTION(6, "SPI5_MISO"), + STM32_FUNCTION(11, "USB_OTG_FS_VBUS"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(207, "PM15"), + STM32_FUNCTION(0, "GPIOM15"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(208, "PN0"), + STM32_FUNCTION(0, "GPION0"), + STM32_FUNCTION(10, "XSPIM_P2_DQS0"), + STM32_FUNCTION(13, "FMC_NE4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(209, "PN1"), + STM32_FUNCTION(0, "GPION1"), + STM32_FUNCTION(10, "XSPIM_P2_NCS1"), + STM32_FUNCTION(13, "FMC_NBL0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(210, "PN2"), + STM32_FUNCTION(0, "GPION2"), + STM32_FUNCTION(10, "XSPIM_P2_IO0"), + STM32_FUNCTION(13, "FMC_D0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(211, "PN3"), + STM32_FUNCTION(0, "GPION3"), + STM32_FUNCTION(10, "XSPIM_P2_IO1"), + STM32_FUNCTION(13, "FMC_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(212, "PN4"), + STM32_FUNCTION(0, "GPION4"), + STM32_FUNCTION(10, "XSPIM_P2_IO2"), + STM32_FUNCTION(13, "FMC_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(213, "PN5"), + STM32_FUNCTION(0, "GPION5"), + STM32_FUNCTION(10, "XSPIM_P2_IO3"), + STM32_FUNCTION(13, "FMC_D3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(214, "PN6"), + STM32_FUNCTION(0, "GPION6"), + STM32_FUNCTION(10, "XSPIM_P2_CLK"), + STM32_FUNCTION(13, "FMC_SDCLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(215, "PN7"), + STM32_FUNCTION(0, "GPION7"), + STM32_FUNCTION(10, "XSPIM_P2_NCLK"), + STM32_FUNCTION(13, "FMC_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(216, "PN8"), + STM32_FUNCTION(0, "GPION8"), + STM32_FUNCTION(10, "XSPIM_P2_IO4"), + STM32_FUNCTION(13, "FMC_D4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(217, "PN9"), + STM32_FUNCTION(0, "GPION9"), + STM32_FUNCTION(10, "XSPIM_P2_IO5"), + STM32_FUNCTION(13, "FMC_D5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(218, "PN10"), + STM32_FUNCTION(0, "GPION10"), + STM32_FUNCTION(10, "XSPIM_P2_IO6"), + STM32_FUNCTION(13, "FMC_D6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(219, "PN11"), + STM32_FUNCTION(0, "GPION11"), + STM32_FUNCTION(10, "XSPIM_P2_IO7"), + STM32_FUNCTION(13, "FMC_D7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(220, "PN12"), + STM32_FUNCTION(0, "GPION12"), + STM32_FUNCTION(10, "XSPIM_P2_NCS2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(221, "PN13"), + STM32_FUNCTION(0, "GPION13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(222, "PN14"), + STM32_FUNCTION(0, "GPION14"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(223, "PN15"), + STM32_FUNCTION(0, "GPION15"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(224, "PO0"), + STM32_FUNCTION(0, "GPIOO0"), + STM32_FUNCTION(10, "XSPIM_P1_NCS1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(225, "PO1"), + STM32_FUNCTION(0, "GPIOO1"), + STM32_FUNCTION(10, "XSPIM_P1_NCS2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(226, "PO2"), + STM32_FUNCTION(0, "GPIOO2"), + STM32_FUNCTION(10, "XSPIM_P1_DQS0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(227, "PO3"), + STM32_FUNCTION(0, "GPIOO3"), + STM32_FUNCTION(10, "XSPIM_P1_DQS1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(228, "PO4"), + STM32_FUNCTION(0, "GPIOO4"), + STM32_FUNCTION(10, "XSPIM_P1_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(229, "PO5"), + STM32_FUNCTION(0, "GPIOO5"), + STM32_FUNCTION(10, "XSPIM_P1_NCLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(230, "PO6"), + STM32_FUNCTION(0, "GPIOO6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(231, "PO7"), + STM32_FUNCTION(0, "GPIOO7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(232, "PO8"), + STM32_FUNCTION(0, "GPIOO8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(233, "PO9"), + STM32_FUNCTION(0, "GPIOO9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(234, "PO10"), + STM32_FUNCTION(0, "GPIOO10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(235, "PO11"), + STM32_FUNCTION(0, "GPIOO11"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(236, "PO12"), + STM32_FUNCTION(0, "GPIOO12"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(237, "PO13"), + STM32_FUNCTION(0, "GPIOO13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(238, "PO14"), + STM32_FUNCTION(0, "GPIOO14"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(239, "PO15"), + STM32_FUNCTION(0, "GPIOO15"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(240, "PP0"), + STM32_FUNCTION(0, "GPIOP0"), + STM32_FUNCTION(10, "XSPIM_P1_IO0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(241, "PP1"), + STM32_FUNCTION(0, "GPIOP1"), + STM32_FUNCTION(10, "XSPIM_P1_IO1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(242, "PP2"), + STM32_FUNCTION(0, "GPIOP2"), + STM32_FUNCTION(10, "XSPIM_P1_IO2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(243, "PP3"), + STM32_FUNCTION(0, "GPIOP3"), + STM32_FUNCTION(10, "XSPIM_P1_IO3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(244, "PP4"), + STM32_FUNCTION(0, "GPIOP4"), + STM32_FUNCTION(10, "XSPIM_P1_IO4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(245, "PP5"), + STM32_FUNCTION(0, "GPIOP5"), + STM32_FUNCTION(10, "XSPIM_P1_IO5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(246, "PP6"), + STM32_FUNCTION(0, "GPIOP6"), + STM32_FUNCTION(10, "XSPIM_P1_IO6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(247, "PP7"), + STM32_FUNCTION(0, "GPIOP7"), + STM32_FUNCTION(10, "XSPIM_P1_IO7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(248, "PP8"), + STM32_FUNCTION(0, "GPIOP8"), + STM32_FUNCTION(10, "XSPIM_P1_IO8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(249, "PP9"), + STM32_FUNCTION(0, "GPIOP9"), + STM32_FUNCTION(10, "XSPIM_P1_IO9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(250, "PP10"), + STM32_FUNCTION(0, "GPIOP10"), + STM32_FUNCTION(10, "XSPIM_P1_IO10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(251, "PP11"), + STM32_FUNCTION(0, "GPIOP11"), + STM32_FUNCTION(10, "XSPIM_P1_IO11"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(252, "PP12"), + STM32_FUNCTION(0, "GPIOP12"), + STM32_FUNCTION(10, "XSPIM_P1_IO12"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(253, "PP13"), + STM32_FUNCTION(0, "GPIOP13"), + STM32_FUNCTION(10, "XSPIM_P1_IO13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(254, "PP14"), + STM32_FUNCTION(0, "GPIOP14"), + STM32_FUNCTION(10, "XSPIM_P1_IO14"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(255, "PP15"), + STM32_FUNCTION(0, "GPIOP15"), + STM32_FUNCTION(10, "XSPIM_P1_IO15"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), +}; + +static struct stm32_pinctrl_match_data stm32h7rs_match_data = { + .pins = stm32h7rs_pins, + .npins = ARRAY_SIZE(stm32h7rs_pins), +}; + +static const struct of_device_id stm32h7rs_pctrl_match[] = { + { + .compatible = "st,stm32h7rs-pinctrl", + .data = &stm32h7rs_match_data, + }, + { } +}; + +static struct platform_driver stm32h7rs_pinctrl_driver = { + .probe = stm32_pctl_probe, + .driver = { + .name = "stm32h7rs-pinctrl", + .of_match_table = stm32h7rs_pctrl_match, + }, +}; + +static int __init stm32h7rs_pinctrl_init(void) +{ + return platform_driver_register(&stm32h7rs_pinctrl_driver); +} +arch_initcall(stm32h7rs_pinctrl_init); -- 2.55.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 6/9] ARM: stm32: add STM32H7R7 platform support 2026-07-31 10:44 [PATCH v2 0/9] ARM: stm32: add STM32H7R7 and ART-Pi2 support Liu Changjie ` (4 preceding siblings ...) 2026-07-23 15:49 ` [PATCH v2 5/9] pinctrl: stm32: add STM32H7RS support Liu Changjie @ 2026-07-23 15:49 ` Liu Changjie 2026-07-23 15:49 ` [PATCH v2 7/9] ARM: dts: stm32: add STM32H7R7 SoC Liu Changjie ` (2 subsequent siblings) 8 siblings, 0 replies; 12+ messages in thread From: Liu Changjie @ 2026-07-23 15:49 UTC (permalink / raw) To: Russell King, Maxime Coquelin, Alexandre Torgue Cc: linux-arm-kernel, linux-kernel, linux-stm32 Enable STM32H7R7 in the STM32 machine selection and compatible table. Add low-level UART4 debug output using the register layout shared by the STM32F7 and STM32H7 USART block. Signed-off-by: Liu Changjie <liucj1228@outlook.com> --- Changes in v2: - Expand the MACH_STM32H7R7 help text to mention noMMU operation and execution from external memory. arch/arm/Kconfig.debug | 12 ++++++++++++ arch/arm/include/debug/stm32.S | 2 +- arch/arm/mach-stm32/Kconfig | 9 +++++++++ arch/arm/mach-stm32/board-dt.c | 1 + 4 files changed, 23 insertions(+), 1 deletion(-) diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 366f162e1..e76750d9e 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -1202,6 +1202,17 @@ choice If unsure, say N. + config STM32H7RS_DEBUG_UART + bool "Use STM32H7RS UART for low-level debug" + depends on MACH_STM32H7R7 + select DEBUG_STM32_UART + help + Say Y here if you want kernel low-level debugging support on + STM32H7RS platforms. The ART-Pi2 debug console is UART4 at + physical address 0x40004c00. + + If unsure, say N. + config STM32MP1_DEBUG_UART bool "Use STM32MP1 UART for low-level debug" depends on MACH_STM32MP157 @@ -1582,6 +1593,7 @@ config DEBUG_UART_PHYS default 0x20201000 if DEBUG_BCM2835 default 0x3e000000 if DEBUG_BCM_KONA_UART default 0x3f201000 if DEBUG_BCM2836 + default 0x40004c00 if STM32H7RS_DEBUG_UART default 0x40010000 if STM32MP1_DEBUG_UART default 0x40011000 if STM32F4_DEBUG_UART || STM32F7_DEBUG_UART || \ STM32H7_DEBUG_UART diff --git a/arch/arm/include/debug/stm32.S b/arch/arm/include/debug/stm32.S index b6d9df30e..2a8c25ede 100644 --- a/arch/arm/include/debug/stm32.S +++ b/arch/arm/include/debug/stm32.S @@ -10,7 +10,7 @@ #endif #if defined(CONFIG_STM32F7_DEBUG_UART) || defined(CONFIG_STM32H7_DEBUG_UART) || \ - defined(CONFIG_STM32MP1_DEBUG_UART) + defined(CONFIG_STM32H7RS_DEBUG_UART) || defined(CONFIG_STM32MP1_DEBUG_UART) #define STM32_USART_SR_OFF 0x1C #define STM32_USART_TDR_OFF 0x28 #endif diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig index 630b992f3..7bc52fe5a 100644 --- a/arch/arm/mach-stm32/Kconfig +++ b/arch/arm/mach-stm32/Kconfig @@ -40,6 +40,15 @@ config MACH_STM32H743 bool "STMicroelectronics STM32H743" default y +config MACH_STM32H7R7 + bool "STMicroelectronics STM32H7R7" + default y + help + Support for STMicroelectronics STM32H7R7 Cortex-M7 + microcontrollers. This enables support for boards based on the + STM32H7R7 SoC, such as the RT-Thread ART-Pi2. These devices run + Linux without an MMU and may execute from external memory. + endif # ARMv7-M if ARCH_MULTI_V7 diff --git a/arch/arm/mach-stm32/board-dt.c b/arch/arm/mach-stm32/board-dt.c index e6233c872..d1207b84a 100644 --- a/arch/arm/mach-stm32/board-dt.c +++ b/arch/arm/mach-stm32/board-dt.c @@ -19,6 +19,7 @@ static const char *const stm32_compat[] __initconst = { "st,stm32h743", "st,stm32h747", "st,stm32h750", + "st,stm32h7r7", "st,stm32mp131", "st,stm32mp133", "st,stm32mp135", -- 2.55.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 7/9] ARM: dts: stm32: add STM32H7R7 SoC 2026-07-31 10:44 [PATCH v2 0/9] ARM: stm32: add STM32H7R7 and ART-Pi2 support Liu Changjie ` (5 preceding siblings ...) 2026-07-23 15:49 ` [PATCH v2 6/9] ARM: stm32: add STM32H7R7 platform support Liu Changjie @ 2026-07-23 15:49 ` Liu Changjie 2026-07-23 15:49 ` [PATCH v2 8/9] ARM: dts: stm32: add Ruiside ART-Pi2 board Liu Changjie 2026-07-23 15:49 ` [PATCH v2 9/9] ARM: stm32: document STM32H7R7 support Liu Changjie 8 siblings, 0 replies; 12+ messages in thread From: Liu Changjie @ 2026-07-23 15:49 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel Describe the Cortex-M7 CPU, clocks, TIM5 clockevent, UART4, SDMMC1, EXTI, system configuration controller and GPIO banks available on STM32H7R7 devices. Expose the RCC reset controller for peripheral consumers. Signed-off-by: Liu Changjie <liucj1228@outlook.com> --- Changes in v2: - Clock TIM5 from a DT fixed-clock instead of the RCC provider, since the timer is initialized via TIMER_OF_DECLARE() before the RCC platform driver; the rate is guaranteed by the first-stage firmware. - Use a single "st,stm32h7rs-rcc" compatible for the RCC node. - Switch the GPIO bank unit-addresses to the pinctrl "ranges" offsets (gpio@0, gpio@400 ... gpio@3c00) to fix the dtc unit-address/reg warnings reported by the kernel test robot. arch/arm/boot/dts/st/stm32h7r7.dtsi | 261 ++++++++++++++++++++++++++++ 1 file changed, 261 insertions(+) create mode 100644 arch/arm/boot/dts/st/stm32h7r7.dtsi diff --git a/arch/arm/boot/dts/st/stm32h7r7.dtsi b/arch/arm/boot/dts/st/stm32h7r7.dtsi new file mode 100644 index 000000000..4e29dc2dd --- /dev/null +++ b/arch/arm/boot/dts/st/stm32h7r7.dtsi @@ -0,0 +1,261 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +#include "../armv7-m.dtsi" +#include <dt-bindings/clock/stm32h7rs-clks.h> +#include <dt-bindings/mfd/stm32h7rs-rcc.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-m7"; + device_type = "cpu"; + reg = <0>; + clocks = <&rcc STM32H7RS_SYS_CK>; + }; + }; + + clocks { + clk_hse: clock-hse { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + clk_lse: clock-lse { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + clk_tim5: clock-tim5 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + }; + + soc { + timer5: timer@40000c00 { + compatible = "st,stm32-timer"; + reg = <0x40000c00 0x400>; + interrupts = <54>; + clocks = <&clk_tim5>; + }; + + uart4: serial@40004c00 { + compatible = "st,stm32h7-uart"; + reg = <0x40004c00 0x400>; + interrupts = <85>; + clocks = <&rcc STM32H7RS_UART4_CK>; + status = "disabled"; + }; + + sdmmc1: mmc@52007000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", + "arm,primecell"; + arm,primecell-periphid = <0x00253180>; + reg = <0x52007000 0x1000>; + interrupts = <108>; + clocks = <&rcc STM32H7RS_SDMMC1_CK>; + clock-names = "apb_pclk"; + resets = <&rcc STM32H7RS_AHB5_RESET(SDMMC1)>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + status = "disabled"; + }; + + exti: interrupt-controller@58000000 { + compatible = "st,stm32h7-exti"; + reg = <0x58000000 0x400>; + interrupts = <16>, <17>, <18>, <19>, + <20>, <21>, <22>, <23>, + <24>, <25>, <26>, <27>, + <28>, <29>, <30>, <31>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + syscfg: syscon@58000400 { + compatible = "st,stm32-syscfg", "syscon"; + reg = <0x58000400 0x400>; + }; + + pinctrl: pinctrl@58020000 { + compatible = "st,stm32h7rs-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x58020000 0x4000>; + interrupt-parent = <&exti>; + st,syscfg = <&syscfg 0x130>; + + gpioa: gpio@0 { + reg = <0x0 0x400>; + clocks = <&rcc STM32H7RS_GPIOA_CK>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + st,bank-name = "GPIOA"; + }; + + gpiob: gpio@400 { + reg = <0x400 0x400>; + clocks = <&rcc STM32H7RS_GPIOB_CK>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + st,bank-name = "GPIOB"; + }; + + gpioc: gpio@800 { + reg = <0x800 0x400>; + clocks = <&rcc STM32H7RS_GPIOC_CK>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 32 16>; + st,bank-name = "GPIOC"; + }; + + gpiod: gpio@c00 { + reg = <0xc00 0x400>; + clocks = <&rcc STM32H7RS_GPIOD_CK>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + st,bank-name = "GPIOD"; + }; + + gpioe: gpio@1000 { + reg = <0x1000 0x400>; + clocks = <&rcc STM32H7RS_GPIOE_CK>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + st,bank-name = "GPIOE"; + }; + + gpiof: gpio@1400 { + reg = <0x1400 0x400>; + clocks = <&rcc STM32H7RS_GPIOF_CK>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + st,bank-name = "GPIOF"; + }; + + gpiog: gpio@1800 { + reg = <0x1800 0x400>; + clocks = <&rcc STM32H7RS_GPIOG_CK>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + st,bank-name = "GPIOG"; + }; + + gpioh: gpio@1c00 { + reg = <0x1c00 0x400>; + clocks = <&rcc STM32H7RS_GPIOH_CK>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 112 16>; + st,bank-name = "GPIOH"; + }; + + gpiom: gpio@3000 { + reg = <0x3000 0x400>; + clocks = <&rcc STM32H7RS_GPIOM_CK>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 192 16>; + st,bank-name = "GPIOM"; + }; + + gpion: gpio@3400 { + reg = <0x3400 0x400>; + clocks = <&rcc STM32H7RS_GPION_CK>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 208 16>; + st,bank-name = "GPION"; + }; + + gpioo: gpio@3800 { + reg = <0x3800 0x400>; + clocks = <&rcc STM32H7RS_GPIOO_CK>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 224 16>; + st,bank-name = "GPIOO"; + }; + + gpiop: gpio@3c00 { + reg = <0x3c00 0x400>; + clocks = <&rcc STM32H7RS_GPIOP_CK>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 240 16>; + st,bank-name = "GPIOP"; + }; + }; + + rcc: reset-clock-controller@58024400 { + compatible = "st,stm32h7rs-rcc"; + reg = <0x58024400 0x400>; + clocks = <&clk_hse>, <&clk_lse>; + clock-names = "hse", "lse"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; + +&systick { + clock-frequency = <250000000>; + status = "okay"; +}; -- 2.55.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 8/9] ARM: dts: stm32: add Ruiside ART-Pi2 board 2026-07-31 10:44 [PATCH v2 0/9] ARM: stm32: add STM32H7R7 and ART-Pi2 support Liu Changjie ` (6 preceding siblings ...) 2026-07-23 15:49 ` [PATCH v2 7/9] ARM: dts: stm32: add STM32H7R7 SoC Liu Changjie @ 2026-07-23 15:49 ` Liu Changjie 2026-08-09 10:23 ` sashiko-bot 2026-07-23 15:49 ` [PATCH v2 9/9] ARM: stm32: document STM32H7R7 support Liu Changjie 8 siblings, 1 reply; 12+ messages in thread From: Liu Changjie @ 2026-07-23 15:49 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue Cc: devicetree, linux-kernel, linux-stm32, linux-arm-kernel Add the STM32H7R7-based ART-Pi2 with 32 MiB of external HyperRAM, UART4 console pin configuration, user LEDs on PO1 and PO5, and the user button on PC13. Enable the four-bit microSD slot and reserve a coherent DMA pool for noMMU DMA allocations. Signed-off-by: Liu Changjie <liucj1228@outlook.com> --- arch/arm/boot/dts/st/Makefile | 1 + arch/arm/boot/dts/st/stm32h7r7l8-art-pi2.dts | 100 +++++++++++++++++++ arch/arm/boot/dts/st/stm32h7rs-pinctrl.dtsi | 63 ++++++++++++ 3 files changed, 164 insertions(+) create mode 100644 arch/arm/boot/dts/st/stm32h7r7l8-art-pi2.dts create mode 100644 arch/arm/boot/dts/st/stm32h7rs-pinctrl.dtsi diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile index 10c5d75f6..ae27a4ef9 100644 --- a/arch/arm/boot/dts/st/Makefile +++ b/arch/arm/boot/dts/st/Makefile @@ -113,6 +113,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32h743i-disco.dtb \ stm32h747i-disco.dtb \ stm32h750i-art-pi.dtb \ + stm32h7r7l8-art-pi2.dtb \ stm32mp133c-prihmb.dtb \ stm32mp135f-dhcor-dhsbc.dtb \ stm32mp13xx-dhcor-dhsbc-overlay-rb-tft32-v2.dtb \ diff --git a/arch/arm/boot/dts/st/stm32h7r7l8-art-pi2.dts b/arch/arm/boot/dts/st/stm32h7r7l8-art-pi2.dts new file mode 100644 index 000000000..ead141817 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32h7r7l8-art-pi2.dts @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +/dts-v1/; + +#include "stm32h7r7.dtsi" +#include "stm32h7rs-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "RT-Thread ART-Pi2 STM32H7R7 board"; + compatible = "ruiside,art-pi2", "st,stm32h7r7"; + + chosen { + bootargs = "earlycon console=ttySTM0,115200"; + stdout-path = "serial0:115200n8"; + }; + + memory@90000000 { + device_type = "memory"; + reg = <0x90000000 0x02000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dma_pool: dma-pool { + compatible = "shared-dma-pool"; + no-map; + size = <0x00200000>; + linux,dma-default; + }; + }; + + aliases { + mmc0 = &sdmmc1; + serial0 = &uart4; + }; + + v3v3: regulator-v3v3 { + compatible = "regulator-fixed"; + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + leds { + compatible = "gpio-leds"; + + led_red: led-red { + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpioo 1 GPIO_ACTIVE_HIGH>; + }; + + led_blue: led-blue { + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpioo 5 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-user { + label = "User"; + linux,code = <KEY_WAKEUP>; + gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&uart4 { + pinctrl-0 = <&uart4_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + max-frequency = <50000000>; + status = "okay"; +}; + +&clk_hse { + clock-frequency = <24000000>; +}; diff --git a/arch/arm/boot/dts/st/stm32h7rs-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32h7rs-pinctrl.dtsi new file mode 100644 index 000000000..08f09f562 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32h7rs-pinctrl.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (C) 2026 Liu Changjie <liucj1228@outlook.com> + */ + +#include <dt-bindings/pinctrl/stm32-pinfunc.h> + +&pinctrl { + sdmmc1_b4_pins_a: sdmmc1-b4-0 { + pins { + pinmux = <STM32_PINMUX('C', 8, AF11)>, /* SDMMC1_D0 */ + <STM32_PINMUX('C', 9, AF11)>, /* SDMMC1_D1 */ + <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ + <STM32_PINMUX('C', 11, AF11)>, /* SDMMC1_D3 */ + <STM32_PINMUX('C', 12, AF11)>, /* SDMMC1_CK */ + <STM32_PINMUX('D', 2, AF11)>; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { + pins1 { + pinmux = <STM32_PINMUX('C', 8, AF11)>, /* SDMMC1_D0 */ + <STM32_PINMUX('C', 9, AF11)>, /* SDMMC1_D1 */ + <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ + <STM32_PINMUX('C', 11, AF11)>, /* SDMMC1_D3 */ + <STM32_PINMUX('C', 12, AF11)>; /* SDMMC1_CK */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + + pins2 { + pinmux = <STM32_PINMUX('D', 2, AF11)>; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { + pins { + pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ + <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */ + <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */ + <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */ + <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */ + <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */ + }; + }; + + uart4_pins_a: uart4-0 { + pins { + pinmux = <STM32_PINMUX('D', 0, AF8)>, /* UART4_RX */ + <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; +}; -- 2.55.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v2 8/9] ARM: dts: stm32: add Ruiside ART-Pi2 board 2026-07-23 15:49 ` [PATCH v2 8/9] ARM: dts: stm32: add Ruiside ART-Pi2 board Liu Changjie @ 2026-08-09 10:23 ` sashiko-bot 0 siblings, 0 replies; 12+ messages in thread From: sashiko-bot @ 2026-08-09 10:23 UTC (permalink / raw) To: Liu Changjie; +Cc: devicetree, conor+dt, robh Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: - [High] Inconsistent Alternate Function (AF) mapping for SDMMC1_D2 pin - [High] Missing alignment constraint for no-map DMA pool causes MPU region exhaustion -- --- Patch [8]: [PATCH v2 8/9] ARM: dts: stm32: add Ruiside ART-Pi2 board --- commit 7778d903d666ebc7aafa183daaea78a638999301 Author: Liu Changjie <liucj1228@outlook.com> ARM: dts: stm32: add Ruiside ART-Pi2 board Adds the ART-Pi2 board based on the STM32H7R7 SoC. Includes configuration for external HyperRAM, UART4, user LEDs, button, and the microSD slot with a coherent DMA pool. [ ... ] > diff --git a/arch/arm/boot/dts/st/stm32h7r7l8-art-pi2.dts b/arch/arm/boot/dts/st/stm32h7r7l8-art-pi2.dts > new file mode 100644 > index 0000000000000..ead1418178af7 > --- /dev/null > +++ b/arch/arm/boot/dts/st/stm32h7r7l8-art-pi2.dts [ ... ] > + reserved-memory { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + dma_pool: dma-pool { > + compatible = "shared-dma-pool"; > + no-map; > + size = <0x00200000>; > + linux,dma-default; > + }; [Severity: High] Does this no-map memory region require an alignment constraint to prevent MPU region exhaustion? Without an alignment property, memblock may allocate this 2MiB hole at a default alignment. On ARM Cortex-M7 (PMSAv7), MPU regions require power-of-2 sizes and aligned base addresses. An unaligned hole can force the MPU to use many small regions to cover the remaining RAM, quickly exhausting the typical 8-region limit and silently truncating system memory. Could we add an alignment = <0x00200000> property here? > + }; [ ... ] > diff --git a/arch/arm/boot/dts/st/stm32h7rs-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32h7rs-pinctrl.dtsi > new file mode 100644 > index 0000000000000..08f09f5621964 > --- /dev/null > +++ b/arch/arm/boot/dts/st/stm32h7rs-pinctrl.dtsi [ ... ] > +&pinctrl { > + sdmmc1_b4_pins_a: sdmmc1-b4-0 { > + pins { > + pinmux = <STM32_PINMUX('C', 8, AF11)>, /* SDMMC1_D0 */ > + <STM32_PINMUX('C', 9, AF11)>, /* SDMMC1_D1 */ > + <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ [Severity: High] Is it intentional that SDMMC1_D2 uses AF12 while the surrounding SDMMC1 pins in this group use AF11? If this is an oversight, the D2 data line will not be routed to the SDMMC1 controller when initialized in 4-bit mode, leading to communication failure with the SD card. > + <STM32_PINMUX('C', 11, AF11)>, /* SDMMC1_D3 */ > + <STM32_PINMUX('C', 12, AF11)>, /* SDMMC1_CK */ > + <STM32_PINMUX('D', 2, AF11)>; /* SDMMC1_CMD */ > + slew-rate = <3>; > + drive-push-pull; > + bias-disable; > + }; > + }; > + > + sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { > + pins1 { > + pinmux = <STM32_PINMUX('C', 8, AF11)>, /* SDMMC1_D0 */ > + <STM32_PINMUX('C', 9, AF11)>, /* SDMMC1_D1 */ > + <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ [Severity: High] The same AF12 mapping appears here for SDMMC1_D2 in the open-drain configuration group. Should this also be AF11? > + <STM32_PINMUX('C', 11, AF11)>, /* SDMMC1_D3 */ > + <STM32_PINMUX('C', 12, AF11)>; /* SDMMC1_CK */ > + slew-rate = <3>; > + drive-push-pull; > + bias-disable; > + }; [ ... ] -- Sashiko AI review · https://sashiko.dev/#/patchset/MN0PR19MB6091DB524E7A07E16D108F52ACDF2@MN0PR19MB6091.namprd19.prod.outlook.com?part=8 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 9/9] ARM: stm32: document STM32H7R7 support 2026-07-31 10:44 [PATCH v2 0/9] ARM: stm32: add STM32H7R7 and ART-Pi2 support Liu Changjie ` (7 preceding siblings ...) 2026-07-23 15:49 ` [PATCH v2 8/9] ARM: dts: stm32: add Ruiside ART-Pi2 board Liu Changjie @ 2026-07-23 15:49 ` Liu Changjie 8 siblings, 0 replies; 12+ messages in thread From: Liu Changjie @ 2026-07-23 15:49 UTC (permalink / raw) To: Jonathan Corbet, Shuah Khan, Maxime Coquelin, Alexandre Torgue Cc: linux-doc, linux-kernel, linux-stm32, linux-arm-kernel Describe the STM32H7R7 features and note the ART-Pi2 as the currently supported development board. Signed-off-by: Liu Changjie <liucj1228@outlook.com> --- Changes in v2: - Add F: entries for the new clk driver, bindings, dt-bindings headers and documentation to the STM32 section of MAINTAINERS. Documentation/arch/arm/index.rst | 1 + .../arch/arm/stm32/stm32h7r7-overview.rst | 28 +++++++++++++++++++ MAINTAINERS | 6 ++++ 3 files changed, 35 insertions(+) create mode 100644 Documentation/arch/arm/stm32/stm32h7r7-overview.rst diff --git a/Documentation/arch/arm/index.rst b/Documentation/arch/arm/index.rst index b15621093..1e33535e5 100644 --- a/Documentation/arch/arm/index.rst +++ b/Documentation/arch/arm/index.rst @@ -55,6 +55,7 @@ SoC-specific documents stm32/overview stm32/stm32h743-overview stm32/stm32h750-overview + stm32/stm32h7r7-overview stm32/stm32f769-overview stm32/stm32f429-overview stm32/stm32mp13-overview diff --git a/Documentation/arch/arm/stm32/stm32h7r7-overview.rst b/Documentation/arch/arm/stm32/stm32h7r7-overview.rst new file mode 100644 index 000000000..7856b4319 --- /dev/null +++ b/Documentation/arch/arm/stm32/stm32h7r7-overview.rst @@ -0,0 +1,28 @@ +================== +STM32H7R7 Overview +================== + +Introduction +------------ + +The STM32H7R7 is a Cortex-M7 microcontroller running at up to 600 MHz. It +features: + +- 64 Kbytes of user boot flash and 620 Kbytes of internal SRAM +- 32 Kbytes of instruction cache and 32 Kbytes of data cache +- Two serial xSPI interfaces and an FMC parallel memory interface +- SD/MMC, Ethernet, USB and FD-CAN controllers +- I2C, SPI, I3C and serial interfaces +- NeoChrom graphics accelerator, JPEG codec and LCD-TFT controller + +The RT-Thread ART-Pi2 development board is supported. + +Resources +--------- + +Datasheet and reference manual are publicly available on the STMicroelectronics +website (STM32H7R7_). + +.. _STM32H7R7: https://www.st.com/en/microcontrollers-microprocessors/stm32h7r7-7s7.html + +:Authors: Liu Changjie <liucj1228@outlook.com> diff --git a/MAINTAINERS b/MAINTAINERS index 1ab873685..bd86eab10 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3667,10 +3667,16 @@ L: linux-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32.git stm32-next +F: Documentation/arch/arm/stm32/stm32h7r7-overview.rst +F: Documentation/devicetree/bindings/arm/stm32/ +F: Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml F: arch/arm/boot/dts/st/stm32* F: arch/arm/mach-stm32/ F: arch/arm64/boot/dts/st/ +F: drivers/clk/clk-stm32h7rs.c F: drivers/clocksource/armv7m_systick.c +F: include/dt-bindings/clock/stm32h7rs-clks.h +F: include/dt-bindings/mfd/stm32h7rs-rcc.h N: stm32 N: stm -- 2.55.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
end of thread, other threads:[~2026-08-09 10:23 UTC | newest] Thread overview: 12+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-07-31 10:44 [PATCH v2 0/9] ARM: stm32: add STM32H7R7 and ART-Pi2 support Liu Changjie 2026-07-23 15:48 ` [PATCH v2 1/9] dt-bindings: arm: stm32: add Ruiside ART-Pi2 Liu Changjie 2026-07-23 15:48 ` [PATCH v2 2/9] dt-bindings: clock: stm32: add STM32H7RS RCC Liu Changjie 2026-08-09 10:15 ` sashiko-bot 2026-07-23 15:48 ` [PATCH v2 3/9] clk: stm32: add STM32H7RS RCC driver Liu Changjie 2026-07-23 15:49 ` [PATCH v2 4/9] dt-bindings: pinctrl: stm32: add STM32H7RS Liu Changjie 2026-07-23 15:49 ` [PATCH v2 5/9] pinctrl: stm32: add STM32H7RS support Liu Changjie 2026-07-23 15:49 ` [PATCH v2 6/9] ARM: stm32: add STM32H7R7 platform support Liu Changjie 2026-07-23 15:49 ` [PATCH v2 7/9] ARM: dts: stm32: add STM32H7R7 SoC Liu Changjie 2026-07-23 15:49 ` [PATCH v2 8/9] ARM: dts: stm32: add Ruiside ART-Pi2 board Liu Changjie 2026-08-09 10:23 ` sashiko-bot 2026-07-23 15:49 ` [PATCH v2 9/9] ARM: stm32: document STM32H7R7 support Liu Changjie
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