From: James Lin <PingLei.Lin@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Harry Wentland <harry.wentland@amd.com>,
Leo Li <sunpeng.li@amd.com>,
Aurabindo Pillai <aurabindo.pillai@amd.com>,
Roman Li <roman.li@amd.com>, Wayne Lin <wayne.lin@amd.com>,
Tom Chung <chiahsuan.chung@amd.com>,
"Fangzhi Zuo" <jerry.zuo@amd.com>,
Dan Wheeler <daniel.wheeler@amd.com>, Ray Wu <Ray.Wu@amd.com>,
Ivan Lipski <ivan.lipski@amd.com>, Alex Hung <alex.hung@amd.com>,
James Lin <PingLei.Lin@amd.com>,
Chenyu Chen <Chen-Yu.Chen@amd.com>,
Karthi Kandasamy <karthi.kandasamy@amd.com>,
"James Lin" <pinglei.lin@amd.com>
Subject: [PATCH 18/24] drm/amd/display: Skip eDP teardown while forced PSR is active
Date: Tue, 11 Aug 2026 05:28:52 +0800 [thread overview]
Message-ID: <20260810213010.1703162-19-PingLei.Lin@amd.com> (raw)
In-Reply-To: <20260810213010.1703162-1-PingLei.Lin@amd.com>
From: Karthi Kandasamy <karthi.kandasamy@amd.com>
[Why & How]
During the HDR<->SDR toggle when the eDP link is held in a forced PSR
(freeze) state,
the normal stream/link teardown re-programming the panel would blank the
frozen frame
and disrupt the freeze; to prevent this, gate the eDP teardown path,
keeping the link
and PSR/Replay state intact for the duration of the forced PSR hold.
The blank_stream and disable_link_output gates already exist.
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Karthi Kandasamy <karthi.kandasamy@amd.com>
Signed-off-by: James Lin <pinglei.lin@amd.com>
---
.../amd/display/dc/hwss/dce110/dce110_hwseq.c | 7 +++++--
.../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 19 +++++++++++++------
.../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 17 ++++++++++++-----
.../amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 8 +++++---
.../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 7 +++++--
.../amd/display/dc/hwss/dcn60/dcn60_hwseq.c | 8 ++++++--
6 files changed, 46 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index 8b47cdeeb1fb..ff0c6e64c2b4 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -3605,8 +3605,11 @@ void dce110_disable_link_output(struct dc_link *link,
else if (dmcu != NULL && dmcu->funcs->lock_phy)
dmcu->funcs->lock_phy(dmcu);
- link_hwss->disable_link_output(link, link_res, signal);
- link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
+ if (!(signal == SIGNAL_TYPE_EDP &&
+ link->forced_psr_active)) {
+ link_hwss->disable_link_output(link, link_res, signal);
+ link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
+ }
/*
* Add the logic to extract BOTH power up and power down sequences
* from enable/disable link output and only call edp panel control
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
index 850639b6fd9b..2739f7acce98 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
@@ -1346,7 +1346,12 @@ static void dcn10_reset_back_end_for_pipe(
* screen only, the dpms_off would be true but
* VBIOS lit up eDP, so check link status too.
*/
- if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)
+ if (link->connector_signal == SIGNAL_TYPE_EDP &&
+ link->forced_psr_active) {
+ /* forced psr is active for seamless switch; skip dpms-off. */
+ if (pipe_ctx->stream_res.audio)
+ dc->hwss.disable_audio_stream(pipe_ctx);
+ } else if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)
dc->link_srv->set_dpms_off(pipe_ctx);
else if (pipe_ctx->stream_res.audio)
dc->hwss.disable_audio_stream(pipe_ctx);
@@ -1370,13 +1375,15 @@ static void dcn10_reset_back_end_for_pipe(
* parent pipe.
*/
if (pipe_ctx->top_pipe == NULL) {
+ if (!(link->connector_signal == SIGNAL_TYPE_EDP &&
+ link->forced_psr_active)) {
+ if (pipe_ctx->stream_res.abm)
+ dc->hwss.set_abm_immediate_disable(pipe_ctx);
- if (pipe_ctx->stream_res.abm)
- dc->hwss.set_abm_immediate_disable(pipe_ctx);
+ pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
- pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
-
- pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
+ pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
+ }
set_drr_and_clear_adjust_pending(pipe_ctx, pipe_ctx->stream, NULL);
if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 0;
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index 16bb6f678567..66e2a6eb41c0 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -2849,7 +2849,12 @@ void dcn20_reset_back_end_for_pipe(
* screen only, the dpms_off would be true but
* VBIOS lit up eDP, so check link status too.
*/
- if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)
+ if (link->connector_signal == SIGNAL_TYPE_EDP &&
+ link->forced_psr_active) {
+ /* forced psr is active for seamless switch; skip dpms-off. */
+ if (pipe_ctx->stream_res.audio)
+ dc->hwss.disable_audio_stream(pipe_ctx);
+ } else if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)
dc->link_srv->set_dpms_off(pipe_ctx);
else if (pipe_ctx->stream_res.audio)
dc->hwss.disable_audio_stream(pipe_ctx);
@@ -2874,12 +2879,14 @@ void dcn20_reset_back_end_for_pipe(
* parent pipe.
*/
if (pipe_ctx->top_pipe == NULL) {
+ if (!(link->connector_signal == SIGNAL_TYPE_EDP &&
+ link->forced_psr_active)) {
+ dc->hwss.set_abm_immediate_disable(pipe_ctx);
- dc->hwss.set_abm_immediate_disable(pipe_ctx);
-
- pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
+ pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
- pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
+ pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
+ }
if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
index 6ddc678bacf9..56d41c6fa3ee 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
@@ -517,9 +517,11 @@ void dcn314_disable_link_output(struct dc_link *link,
link->dc->hwss.edp_backlight_control(link, false);
else if (dmcu != NULL && dmcu->funcs->lock_phy)
dmcu->funcs->lock_phy(dmcu);
-
- link_hwss->disable_link_output(link, link_res, signal);
- link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
+ if (!(signal == SIGNAL_TYPE_EDP &&
+ link->forced_psr_active)) {
+ link_hwss->disable_link_output(link, link_res, signal);
+ link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
+ }
/*
* Add the logic to extract BOTH power up and power down sequences
* from enable/disable link output and only call edp panel control
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index 51fd2b3fe106..e188796cf272 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -1432,8 +1432,11 @@ void dcn32_disable_link_output(struct dc_link *link,
else if (dmcu != NULL && dmcu->funcs->lock_phy)
dmcu->funcs->lock_phy(dmcu);
- link_hwss->disable_link_output(link, link_res, signal);
- link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
+ if (!(signal == SIGNAL_TYPE_EDP &&
+ link->forced_psr_active)) {
+ link_hwss->disable_link_output(link, link_res, signal);
+ link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
+ }
/*
* Add the logic to extract BOTH power up and power down sequences
* from enable/disable link output and only call edp panel control
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.c
index b9a046584740..8ee9791b2c46 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.c
@@ -291,7 +291,9 @@ enum dc_status dcn60_apply_single_controller_ctx_to_hw(
dc_is_virtual_signal(pipe_ctx->stream->signal)))
dc->link_srv->set_dsc_enable(pipe_ctx, true);
}
- if (!stream->dpms_off)
+ if (!stream->dpms_off &&
+ !(link->connector_signal == SIGNAL_TYPE_EDP &&
+ link->forced_psr_active))
dc->link_srv->set_dpms_on(context, pipe_ctx);
/* DCN3.1 FPGA Workaround
@@ -310,7 +312,9 @@ enum dc_status dcn60_apply_single_controller_ctx_to_hw(
* is constructed with the same sink). Make sure not to override
* and link programming on the main.
*/
- if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {
+ if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM &&
+ !(link->connector_signal == SIGNAL_TYPE_EDP &&
+ link->forced_psr_active)) {
pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false;
pipe_ctx->stream->link->replay_settings.replay_feature_enabled = false;
}
--
2.43.0
next prev parent reply other threads:[~2026-08-11 15:51 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-10 21:28 [PATCH 00/24] DC Patches Aug 17 2026 James Lin
2026-08-10 21:28 ` [PATCH 01/24] drm/amd/display: Add CACP ACE curve area debugfs for IGT validation James Lin
2026-08-10 21:28 ` [PATCH 02/24] drm/amd/display: Move periodic interrupt calculations to HWSS James Lin
2026-08-10 21:28 ` [PATCH 03/24] drm/amd/display: Add missing prototype for amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags James Lin
2026-08-10 21:28 ` [PATCH 04/24] drm/amd/display: Rename carried dce clock manager functions for dcn10 James Lin
2026-08-10 21:28 ` [PATCH 05/24] drm/amd/display: Add utm_support capability flag James Lin
2026-08-10 21:28 ` [PATCH 06/24] drm/amd/display: Guard against empty DCN6 UTM QoS table James Lin
2026-08-10 21:28 ` [PATCH 07/24] drm/amd/display: Add DC_BLS command James Lin
2026-08-10 21:28 ` [PATCH 08/24] drm/amd/display: Notify DMU to allow DCHVM<->rIOMMU SDP port disconnection for DCN42 James Lin
2026-08-10 21:28 ` [PATCH 09/24] drm/amd/display: Send DPM0 clock values to DMU James Lin
2026-08-10 21:28 ` [PATCH 10/24] drm/amd/display: Refactor HUBP_WAIT_FOR_DCC_META_PROP to drop pipe_ctx James Lin
2026-08-10 21:28 ` [PATCH 11/24] drm/amd/display: add wait stream regen event James Lin
2026-08-10 21:28 ` [PATCH 12/24] drm/amd/display: Use mpcc_id instead of hubp instance James Lin
2026-08-10 21:28 ` [PATCH 13/24] drm/amd/display: Add opt-out for DCN6 OutstandingRequests mode-support check James Lin
2026-08-10 21:28 ` [PATCH 14/24] drm/amd/display: Make Struct In DCN42 SOC BB Header Static James Lin
2026-08-10 21:28 ` [PATCH 15/24] drm/amd/display: Refactor Per-DPM Derate Logic James Lin
2026-08-10 21:28 ` [PATCH 16/24] drm/amd/display: Update Derates And Set Default Per-DPM Derates James Lin
2026-08-10 21:28 ` [PATCH 17/24] drm/amd/display: Unify CalculateFlipSchedule Logic James Lin
2026-08-10 21:28 ` James Lin [this message]
2026-08-10 21:28 ` [PATCH 19/24] drm/amd/display: Update soc_and_ip_translator To Use Updated Per-DPM Derate Organization James Lin
2026-08-10 21:28 ` [PATCH 20/24] drm/amd/display: Relax frame size limit for dcn5/6 DML core funcs files James Lin
2026-08-10 21:28 ` [PATCH 21/24] drm/amd/display: [FW Promotion] Release 0.1.71.0 James Lin
2026-08-10 21:28 ` [PATCH 22/24] drm/amd/display: set base.enable in cursor mode tests James Lin
2026-08-10 21:28 ` [PATCH 23/24] drm/amd/display: test native cursor mode on a disabled CRTC James Lin
2026-08-10 21:28 ` [PATCH 24/24] drm/amd/display: Promote DC to 3.2.394 James Lin
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