[RFC PATCH v3 0/3] dt-bindings: riscv: Add RISC-V Worlds and SiFive WorldGuard DT bindings

[Yu-Chien Peter Lin <peter.lin@sifive.com>]

This series introduces device tree bindings for the RISC-V Worlds ISA
extensions and the SiFive WorldGuard Checker hardware.

RISC-V Worlds is a set of standard ISA extensions (Smwid, Smlwid,
Smlwidlist, Smwiddeleg, Sswid) that enable hardware-enforced context
isolation by tagging each system transaction with a World ID (WID).
The extensions allow platform firmware to assign WIDs to privilege
levels, execution contexts, or isolation domains, and delegatable WID
management across privilege boundaries.

The SiFive WorldGuard Checker (wgChecker) is a hardware firewall
positioned in the system interconnect fabric. It inspects the WID
of every transaction and enforces access control policies on memory
regions and memory-mapped I/O devices. The wgChecker is based on the
access-controllers framework, allowing protected devices to declare
their access requirements via standard phandle references.

This is submitted as [RFC] because the RISC-V Worlds specification
is not yet ratified. The extension descriptions in extensions.yaml
carry placeholder "TBD" commit references; these will be updated
to the actual ratification commit before the series is merged.

Yu-Chien Peter Lin (3):
  dt-bindings: riscv: Add Worlds ISA extensions
  dt-bindings: riscv: Add Worlds per-hart properties
  dt-bindings: access-controllers: Add SiFive WorldGuard Checker

 .../access-controllers/sifive,wgchecker2.yaml | 178 ++++++++++++++++++
 .../devicetree/bindings/riscv/cpus.yaml       |  44 +++++
 .../devicetree/bindings/riscv/extensions.yaml |  53 ++++++
 3 files changed, 275 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/access-controllers/sifive,wgchecker2.yaml

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