* [PATCH v8 01/11] spacemit: k1: select boot device via config registers
2026-08-01 16:40 [PATCH v8 00/11] spacemit mmc driver Eric Chung
@ 2026-08-01 16:40 ` Eric Chung
2026-08-01 16:40 ` [PATCH v8 02/11] pinctrl: k1: fix drive strength configuration Eric Chung
` (9 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Eric Chung @ 2026-08-01 16:40 UTC (permalink / raw)
To: u-boot-spacemit, u-boot, u-boot
Cc: Tom Rini, Tim Ouyang, Leo Liang, Peng Fan, Huan Zhou, Raymond Mao,
Jaehoon Chung, Bhimeswararao Matsa, Tanmay Kathpalia,
Kaustabh Chakraborty, Han Xu, Yanir Levin, Christoph Stoidner,
Balsundar Ponnusamy, Daniel Palmer, Anshul Dalal,
Bastien Curutchet, Angelo Dureghello, Johan Jonker, Sam Protsenko,
Guodong Xu, Yao Zi, Rick Chen, Leo, Eric Chung
Add logic to determine the current boot device by reading the
SoC's configuration registers, rather than using a hardcoded
default.
Signed-off-by: Eric Chung <eric.chung@riscstar.com>
Reviewed-by: Yao Zi <me@ziyao.cc>
---
v5:
- Add blank lines around the switch statement.
v2:
- Use FIELD_GET() to parse boot strap mode.
- Remove comments on hacking. Since the sequence between eMMC
and SD device is exchanged in the upstream DTS. So it isn't
a hacking any more.
---
board/spacemit/k1/spl.c | 71 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 70 insertions(+), 1 deletion(-)
diff --git a/board/spacemit/k1/spl.c b/board/spacemit/k1/spl.c
index d749e21a2d57..613e8c4cf02a 100644
--- a/board/spacemit/k1/spl.c
+++ b/board/spacemit/k1/spl.c
@@ -13,6 +13,7 @@
#include <dm/device.h>
#include <dm/uclass.h>
#include <i2c.h>
+#include <linux/bitfield.h>
#include <linux/ctype.h>
#include <linux/delay.h>
#include <log.h>
@@ -22,6 +23,17 @@
#include <tlv_eeprom.h>
#include "tlv_codes.h"
+/* boot mode configs */
+#define BOOT_DEV_FLAG_REG 0xd4282d10
+#define BOOT_PIN_SEL_REG 0xd4282c20
+
+#define BOOT_STRAP_MODE_OFFSET 9
+#define BOOT_STRAP_MODE_MASK 3
+#define BOOT_STRAP_MODE_EMMC 0
+#define BOOT_STRAP_MODE_SPI 1
+#define BOOT_STRAP_MODE_NAND 2
+#define BOOT_STRAP_MODE_SD 3
+
#define MUX_MODE4 4
#define EDGE_NONE BIT(6)
#define PULL_UP (6 << 13) /* bit[15:13] 110 */
@@ -46,6 +58,17 @@ typedef void (*puts_func_t)(const char *s);
typedef int (*ddr_init_func_t)(u64 ddr_base, u32 cs_num, u32 data_rate,
puts_func_t puts);
+enum board_boot_mode {
+ BOOT_MODE_NONE = 0,
+ BOOT_MODE_USB = 0x55a,
+ BOOT_MODE_EMMC,
+ BOOT_MODE_NAND,
+ BOOT_MODE_SPI,
+ BOOT_MODE_SD,
+ BOOT_MODE_SHELL = 0x55f,
+ BOOT_MODE_BOOTSTRAP,
+};
+
struct ddr_cfg {
u32 data_rate;
u32 cs_num;
@@ -354,7 +377,53 @@ void board_init_f(ulong dummy)
u32 spl_boot_device(void)
{
- return BOOT_DEVICE_SPI;
+ void __iomem *boot_dev = (void __iomem *)BOOT_DEV_FLAG_REG;
+ void __iomem *boot_strap = (void __iomem *)BOOT_PIN_SEL_REG;
+ u32 mode, sel, ret = 0;
+
+ mode = readl(boot_dev);
+ if (mode == BOOT_MODE_NONE || mode > BOOT_MODE_SD) {
+ sel = FIELD_GET(BOOT_STRAP_MODE_MASK << BOOT_STRAP_MODE_OFFSET,
+ readl(boot_strap));
+ switch (sel) {
+ case BOOT_STRAP_MODE_EMMC:
+ mode = BOOT_MODE_EMMC;
+ break;
+ case BOOT_STRAP_MODE_NAND:
+ mode = BOOT_MODE_NAND;
+ break;
+ case BOOT_STRAP_MODE_SPI:
+ mode = BOOT_MODE_SPI;
+ break;
+ case BOOT_STRAP_MODE_SD:
+ default:
+ mode = BOOT_MODE_SD;
+ break;
+ }
+ }
+
+ switch (mode) {
+ case BOOT_MODE_EMMC:
+ ret = BOOT_DEVICE_MMC1;
+ break;
+ case BOOT_MODE_NAND:
+ ret = BOOT_DEVICE_NAND;
+ break;
+ case BOOT_MODE_SPI:
+ ret = BOOT_DEVICE_SPI;
+ break;
+ case BOOT_MODE_USB:
+ ret = BOOT_DEVICE_USB;
+ break;
+ case BOOT_MODE_SD:
+ ret = BOOT_DEVICE_MMC2;
+ break;
+ default:
+ ret = BOOT_DEVICE_MMC1;
+ break;
+ }
+
+ return ret;
}
void spl_board_init(void)
--
2.51.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v8 02/11] pinctrl: k1: fix drive strength configuration
2026-08-01 16:40 [PATCH v8 00/11] spacemit mmc driver Eric Chung
2026-08-01 16:40 ` [PATCH v8 01/11] spacemit: k1: select boot device via config registers Eric Chung
@ 2026-08-01 16:40 ` Eric Chung
2026-08-01 16:40 ` [PATCH v8 03/11] pinctrl: k1: fix pull-up/pull-down configuration Eric Chung
` (8 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Eric Chung @ 2026-08-01 16:40 UTC (permalink / raw)
To: u-boot-spacemit, u-boot, u-boot
Cc: Tom Rini, Tim Ouyang, Leo Liang, Peng Fan, Huan Zhou, Raymond Mao,
Jaehoon Chung, Bhimeswararao Matsa, Tanmay Kathpalia,
Kaustabh Chakraborty, Han Xu, Yanir Levin, Christoph Stoidner,
Balsundar Ponnusamy, Daniel Palmer, Anshul Dalal,
Bastien Curutchet, Angelo Dureghello, Johan Jonker, Sam Protsenko,
Guodong Xu, Yao Zi, Rick Chen, Leo, Eric Chung
Fix drive strength configuration by:
- Using FIELD_PREP() to properly set the PAD_DRIVE mask bits
- Not overriding io_type with IO_TYPE_EXTERNAL for external pins
- Returning the pin number instead of 0 from pinmux_property_set
- Removing redundant zero-initialization of the mask variable
Signed-off-by: Eric Chung <eric.chung@riscstar.com>
---
v6:
- Fix drive strength configuration.
---
drivers/pinctrl/spacemit/pinctrl-k1.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c
index a6a22eacac7b..6ed511879daf 100644
--- a/drivers/pinctrl/spacemit/pinctrl-k1.c
+++ b/drivers/pinctrl/spacemit/pinctrl-k1.c
@@ -9,6 +9,7 @@
#include <dm/device_compat.h>
#include <dm/pinctrl.h>
#include <dm/read.h>
+#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/errno.h>
#include <linux/io.h>
@@ -386,10 +387,12 @@ static int spacemit_pinmux_set(struct udevice *dev, unsigned int pin,
static int spacemit_pinmux_property_set(struct udevice *dev, u32 pinmux_group)
{
u32 pin, mux;
+ int ret;
pin = spacemit_dt_get_pin(pinmux_group);
mux = spacemit_dt_get_pin_mux(pinmux_group);
- return spacemit_pinmux_set(dev, pin, mux);
+ ret = spacemit_pinmux_set(dev, pin, mux);
+ return ret ? ret : pin;
}
static const struct pinconf_param spacemit_pinconf_params[] = {
@@ -406,7 +409,7 @@ static int spacemit_pinconf_set(struct udevice *dev, unsigned int pin_selector,
struct spacemit_pinctrl_data *data;
struct spacemit_pinctrl_priv *priv = dev_get_priv(dev);
void __iomem *addr;
- u32 mask = 0;
+ u32 mask;
unsigned int io_type;
u8 ds;
bool found;
@@ -433,7 +436,8 @@ static int spacemit_pinconf_set(struct udevice *dev, unsigned int pin_selector,
for (i = 0; i < priv->nr_io_pins; i++) {
if (priv->io_pins[i].pin != pin_selector)
continue;
- io_type = priv->io_pins[i].io_type;
+ if (priv->io_pins[i].io_type != IO_TYPE_EXTERNAL)
+ io_type = priv->io_pins[i].io_type;
break;
}
if (io_type != IO_TYPE_3V3 && io_type != IO_TYPE_1V8) {
@@ -441,7 +445,7 @@ static int spacemit_pinconf_set(struct udevice *dev, unsigned int pin_selector,
return -EINVAL;
}
ds = spacemit_get_drive_strength(io_type, argument);
- clrsetbits_le32(addr, PAD_DRIVE, ds);
+ clrsetbits_le32(addr, PAD_DRIVE, FIELD_PREP(PAD_DRIVE, ds));
break;
case PIN_CONFIG_POWER_SOURCE:
for (i = 0, found = false; i < priv->nr_io_pins; i++) {
--
2.51.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v8 03/11] pinctrl: k1: fix pull-up/pull-down configuration
2026-08-01 16:40 [PATCH v8 00/11] spacemit mmc driver Eric Chung
2026-08-01 16:40 ` [PATCH v8 01/11] spacemit: k1: select boot device via config registers Eric Chung
2026-08-01 16:40 ` [PATCH v8 02/11] pinctrl: k1: fix drive strength configuration Eric Chung
@ 2026-08-01 16:40 ` Eric Chung
2026-08-01 16:40 ` [PATCH v8 04/11] pinctrl: k1: add IO power domain configuration support Eric Chung
` (7 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Eric Chung @ 2026-08-01 16:40 UTC (permalink / raw)
To: u-boot-spacemit, u-boot, u-boot
Cc: Tom Rini, Tim Ouyang, Leo Liang, Peng Fan, Huan Zhou, Raymond Mao,
Jaehoon Chung, Bhimeswararao Matsa, Tanmay Kathpalia,
Kaustabh Chakraborty, Han Xu, Yanir Levin, Christoph Stoidner,
Balsundar Ponnusamy, Daniel Palmer, Anshul Dalal,
Bastien Curutchet, Angelo Dureghello, Johan Jonker, Sam Protsenko,
Guodong Xu, Yao Zi, Rick Chen, Leo, Eric Chung
Fix pull-up/pull-down configuration to honor the argument parameter:
when argument is non-zero, enable the requested pull direction;
when argument is zero, clear all pull bits to disable.
Signed-off-by: Eric Chung <eric.chung@riscstar.com>
---
v7:
- Simplify pull-up/pull-down configuration by using a single
clrsetbits_le32() call.
v6:
- Fix pull-up/pull-down configuration.
---
drivers/pinctrl/spacemit/pinctrl-k1.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c
index 6ed511879daf..4e65fad1e8c5 100644
--- a/drivers/pinctrl/spacemit/pinctrl-k1.c
+++ b/drivers/pinctrl/spacemit/pinctrl-k1.c
@@ -409,7 +409,6 @@ static int spacemit_pinconf_set(struct udevice *dev, unsigned int pin_selector,
struct spacemit_pinctrl_data *data;
struct spacemit_pinctrl_priv *priv = dev_get_priv(dev);
void __iomem *addr;
- u32 mask;
unsigned int io_type;
u8 ds;
bool found;
@@ -424,12 +423,12 @@ static int spacemit_pinconf_set(struct udevice *dev, unsigned int pin_selector,
clrbits_le32(addr, PAD_PULLUP | PAD_PULLDOWN | PAD_PULL_EN);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
- mask = PAD_PULLDOWN | PAD_PULLUP | PAD_PULL_EN;
- clrsetbits_le32(addr, mask, PAD_PULLDOWN | PAD_PULL_EN);
+ clrsetbits_le32(addr, PAD_PULLDOWN | PAD_PULLUP | PAD_PULL_EN,
+ argument ? PAD_PULLDOWN | PAD_PULL_EN : 0);
break;
case PIN_CONFIG_BIAS_PULL_UP:
- mask = PAD_PULLDOWN | PAD_PULLUP | PAD_PULL_EN;
- clrsetbits_le32(addr, mask, PAD_PULLUP | PAD_PULL_EN);
+ clrsetbits_le32(addr, PAD_PULLDOWN | PAD_PULLUP | PAD_PULL_EN,
+ argument ? PAD_PULLUP | PAD_PULL_EN : 0);
break;
case PIN_CONFIG_DRIVE_STRENGTH:
io_type = IO_TYPE_1V8;
--
2.51.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v8 04/11] pinctrl: k1: add IO power domain configuration support
2026-08-01 16:40 [PATCH v8 00/11] spacemit mmc driver Eric Chung
` (2 preceding siblings ...)
2026-08-01 16:40 ` [PATCH v8 03/11] pinctrl: k1: fix pull-up/pull-down configuration Eric Chung
@ 2026-08-01 16:40 ` Eric Chung
2026-08-01 16:40 ` [PATCH v8 05/11] mmc: k1: add sdhci platform driver Eric Chung
` (6 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Eric Chung @ 2026-08-01 16:40 UTC (permalink / raw)
To: u-boot-spacemit, u-boot, u-boot
Cc: Tom Rini, Tim Ouyang, Leo Liang, Peng Fan, Huan Zhou, Raymond Mao,
Jaehoon Chung, Bhimeswararao Matsa, Tanmay Kathpalia,
Kaustabh Chakraborty, Han Xu, Yanir Levin, Christoph Stoidner,
Balsundar Ponnusamy, Daniel Palmer, Anshul Dalal,
Bastien Curutchet, Angelo Dureghello, Johan Jonker, Sam Protsenko,
Guodong Xu, Yao Zi, Rick Chen, Leo, Eric Chung
Dual-voltage GPIO banks default to 3.3V, but when externally supplied
with 1.8V the internal logic must be explicitly reconfigured to match.
Add the ability to program IO power domain control registers through the
APBC block. These registers require unlocking the AIB Secure Access
Register (ASAR) before every read/write, since configuring a 1.8V domain
while 3.3V is externally supplied can cause back-powering and pin damage.
Signed-off-by: Eric Chung <eric.chung@riscstar.com>
Reviewed-by: Yao Zi <me@ziyao.cc>
---
v7:
- Remove the dependency on SYSCON.
v6:
- Use dev_read_phandle_with_args() to fetch "spacemit,apbc" instead.
v5:
- Use tabs for macro definition alignment.
- Fix the missing power source argument.
v3:
- Add SYSCON dependency in Kconfig.
- Fix not sorted issue in the driver.
---
drivers/pinctrl/spacemit/pinctrl-k1.c | 95 +++++++++++++++++++++++++++++++++--
1 file changed, 92 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c
index 4e65fad1e8c5..9c0fa4badc25 100644
--- a/drivers/pinctrl/spacemit/pinctrl-k1.c
+++ b/drivers/pinctrl/spacemit/pinctrl-k1.c
@@ -13,6 +13,7 @@
#include <linux/bitops.h>
#include <linux/errno.h>
#include <linux/io.h>
+#include <regmap.h>
/*
* +---------+----------+-----------+--------+--------+----------+--------+
@@ -35,8 +36,23 @@
#define PAD_PULLUP BIT(14)
#define PAD_PULL_EN BIT(15)
-#define PIN_POWER_STATE_1V8 1800
-#define PIN_POWER_STATE_3V3 3300
+#define IO_PWR_DOMAIN_OFFSET 0x800
+
+#define IO_PWR_DOMAIN_GPIO2_Kx 0x0c
+#define IO_PWR_DOMAIN_GPIO3_K1 0x10
+#define IO_PWR_DOMAIN_MMC_Kx 0x1c
+#define IO_PWR_DOMAIN_QSPI_K1 0x20
+
+#define IO_PWR_DOMAIN_V18EN BIT(2)
+
+#define APBC_ASFAR 0x50
+#define APBC_ASSAR 0x54
+
+#define APBC_ASFAR_AKEY 0xbaba
+#define APBC_ASSAR_AKEY 0xeb10
+
+#define PIN_POWER_STATE_1V8 1800
+#define PIN_POWER_STATE_3V3 3300
enum spacemit_pin_io_type {
IO_TYPE_NONE = 0,
@@ -61,12 +77,14 @@ struct spacemit_pinctrl_data {
int (*get_pins)(struct udevice *dev);
int (*get_functions)(struct udevice *dev);
int (*get_io_type)(struct udevice *dev, unsigned int pin);
+ unsigned int (*pin_to_io_pd_offset)(unsigned int pin);
};
struct spacemit_pinctrl_priv {
void __iomem *regs;
struct spacemit_pin_io *io_pins;
int nr_io_pins;
+ struct regmap *regmap;
};
struct spacemit_pin_mux_config {
@@ -197,6 +215,28 @@ static int k1_get_io_type(struct udevice *dev, unsigned int selector)
return -EINVAL;
}
+static unsigned int spacemit_k1_pin_to_io_pd_offset(unsigned int pin)
+{
+ unsigned int offset = 0;
+
+ switch (pin) {
+ case 47 ... 52:
+ offset = IO_PWR_DOMAIN_GPIO3_K1;
+ break;
+ case 75 ... 80:
+ offset = IO_PWR_DOMAIN_GPIO2_Kx;
+ break;
+ case 98 ... 103:
+ offset = IO_PWR_DOMAIN_QSPI_K1;
+ break;
+ case 104 ... 109:
+ offset = IO_PWR_DOMAIN_MMC_Kx;
+ break;
+ }
+
+ return offset;
+}
+
/* use IO high level output current as the table */
static struct spacemit_pin_drv_strength spacemit_ds_1v8_tbl[4] = {
{ 0, 11 },
@@ -403,6 +443,35 @@ static const struct pinconf_param spacemit_pinconf_params[] = {
{ "power-source", PIN_CONFIG_POWER_SOURCE, U32_MAX },
};
+static void spacemit_set_io_power_domain(struct udevice *dev,
+ unsigned int pin,
+ unsigned int io_type)
+{
+ struct spacemit_pinctrl_priv *priv = dev_get_priv(dev);
+ struct spacemit_pinctrl_data *data;
+ unsigned int offset;
+ u32 val = 0;
+
+ if (!priv->regmap)
+ return;
+
+ data = (struct spacemit_pinctrl_data *)dev_get_driver_data(dev);
+ if (!data || !data->pin_to_io_pd_offset)
+ return;
+
+ offset = data->pin_to_io_pd_offset(pin);
+ if (!offset)
+ return;
+
+ if (io_type == IO_TYPE_1V8)
+ val = IO_PWR_DOMAIN_V18EN;
+
+ regmap_write(priv->regmap, APBC_ASFAR, APBC_ASFAR_AKEY);
+ regmap_write(priv->regmap, APBC_ASSAR, APBC_ASSAR_AKEY);
+
+ writel(val, priv->regs + IO_PWR_DOMAIN_OFFSET + offset);
+}
+
static int spacemit_pinconf_set(struct udevice *dev, unsigned int pin_selector,
unsigned int param, unsigned int argument)
{
@@ -417,6 +486,7 @@ static int spacemit_pinconf_set(struct udevice *dev, unsigned int pin_selector,
data = (struct spacemit_pinctrl_data *)dev_get_driver_data(dev);
if (!data || !data->pin_to_reg)
return -EINVAL;
+
addr = data->pin_to_reg(dev, pin_selector);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
@@ -459,10 +529,14 @@ static int spacemit_pinconf_set(struct udevice *dev, unsigned int pin_selector,
}
break;
}
- if (!found && argument != PIN_POWER_STATE_1V8) {
+ if (!found && argument != PIN_POWER_STATE_1V8 &&
+ argument != PIN_POWER_STATE_3V3) {
dev_err(dev, "Invalid power source (%d)\n", argument);
return -EINVAL;
}
+ if (found)
+ spacemit_set_io_power_domain(dev, pin_selector,
+ priv->io_pins[i].io_type);
break;
default:
return -EOPNOTSUPP;
@@ -475,6 +549,7 @@ static int spacemit_pinctrl_probe(struct udevice *dev)
struct spacemit_pinctrl_data *data;
struct spacemit_pinctrl_priv *priv;
struct clk_bulk clks;
+ struct ofnode_phandle_args args;
size_t size;
int ret;
@@ -492,6 +567,19 @@ static int spacemit_pinctrl_probe(struct udevice *dev)
dev_err(dev, "Fail to allocate memory\n");
return -ENOMEM;
}
+ ret = dev_read_phandle_with_args(dev, "spacemit,apbc",
+ NULL, 0, 0, &args);
+ if (ret) {
+ dev_warn(dev, "no APBC phandle found, disable IO power domain switching\n");
+ priv->regmap = NULL;
+ } else {
+ ret = regmap_init_mem(args.node, &priv->regmap);
+ if (ret) {
+ dev_warn(dev, "failed to get APBC regmap,"
+ " disable IO power domain switching\n");
+ priv->regmap = NULL;
+ }
+ }
ret = clk_get_bulk(dev, &clks);
if (ret) {
@@ -519,6 +607,7 @@ static const struct spacemit_pinctrl_data k1_pinctrl_data = {
.get_pins = k1_get_pins,
.get_functions = k1_get_functions,
.get_io_type = k1_get_io_type,
+ .pin_to_io_pd_offset = spacemit_k1_pin_to_io_pd_offset,
};
static const struct udevice_id spacemit_pinctrl_ids[] = {
--
2.51.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v8 05/11] mmc: k1: add sdhci platform driver
2026-08-01 16:40 [PATCH v8 00/11] spacemit mmc driver Eric Chung
` (3 preceding siblings ...)
2026-08-01 16:40 ` [PATCH v8 04/11] pinctrl: k1: add IO power domain configuration support Eric Chung
@ 2026-08-01 16:40 ` Eric Chung
2026-08-01 16:40 ` [PATCH v8 06/11] dts: k1: add SD card support in u-boot overlay Eric Chung
` (5 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Eric Chung @ 2026-08-01 16:40 UTC (permalink / raw)
To: u-boot-spacemit, u-boot, u-boot
Cc: Tom Rini, Tim Ouyang, Leo Liang, Peng Fan, Huan Zhou, Raymond Mao,
Jaehoon Chung, Bhimeswararao Matsa, Tanmay Kathpalia,
Kaustabh Chakraborty, Han Xu, Yanir Levin, Christoph Stoidner,
Balsundar Ponnusamy, Daniel Palmer, Anshul Dalal,
Bastien Curutchet, Angelo Dureghello, Johan Jonker, Sam Protsenko,
Guodong Xu, Yao Zi, Rick Chen, Leo, Eric Chung
Add SDHCI platform driver support for SpacemiT K1 SoC. This driver
implements the necessary platform-specific operations for the SDHCI
controller, enabling MMC/SD card functionality on K1-based platforms.
Signed-off-by: Eric Chung <eric.chung@riscstar.com>
---
v6:
- Remove ".data = 0" in spacemit_sdhci_ids[].
v5:
- Remove MMC_CAP_CMD23 as the CMD23 support is now a separate series.
- Use tabs for macro definition alignment.
- Use read_poll_timeout().
- Set pinctrl state based on selected timing mode.
- Add the definition of SDHC_DLL_REG1_HS400_VAL.
- Remove the condition based on quirks.
v4:
- Add bulk release operations on reset and clock.
v3:
- Enable CMD23 in capability.
v2:
- Enable ADMA mode support.
- Use CMD23 for multi-block read/write.
- Move ASR/AIB register into pinctrl driver.
- Correct pinctrl state from "fast" to "uhs".
- Migrate tuning support from the spacemit linux driver.
---
drivers/mmc/Kconfig | 7 +
drivers/mmc/Makefile | 1 +
drivers/mmc/spacemit_sdhci.c | 673 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 681 insertions(+)
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index f9f7aa5cf97d..b991a5931c0b 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -722,6 +722,13 @@ config MMC_SDHCI_SNPS
If unsure, say N.
+config MMC_SDHCI_SPACEMIT
+ bool "Spacemit SDHCI controller"
+ depends on MMC_SDHCI
+ help
+ Support for Secure Digital Host Controller Interface (SDHCI) on
+ Spacemit K1 SoC.
+
config MMC_SDHCI_STI
bool "SDHCI support for STMicroelectronics SoC"
depends on MMC_SDHCI && OF_CONTROL && ARCH_STI
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index a23336d7d8d7..aa05cec23be7 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -71,6 +71,7 @@ obj-$(CONFIG_MMC_SDHCI_ROCKCHIP) += rockchip_sdhci.o
obj-$(CONFIG_MMC_SDHCI_ADI) += adi_sdhci.o
obj-$(CONFIG_MMC_SDHCI_S5P) += s5p_sdhci.o
obj-$(CONFIG_MMC_SDHCI_SNPS) += snps_sdhci.o
+obj-$(CONFIG_MMC_SDHCI_SPACEMIT) += spacemit_sdhci.o
obj-$(CONFIG_MMC_SDHCI_STI) += sti_sdhci.o
obj-$(CONFIG_MMC_SDHCI_TANGIER) += tangier_sdhci.o
obj-$(CONFIG_MMC_SDHCI_TEGRA) += tegra_mmc.o
diff --git a/drivers/mmc/spacemit_sdhci.c b/drivers/mmc/spacemit_sdhci.c
new file mode 100644
index 000000000000..3e1948eb3e57
--- /dev/null
+++ b/drivers/mmc/spacemit_sdhci.c
@@ -0,0 +1,673 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Driver for Spacemit K1 Mobile Storage Host Controller
+ *
+ * Copyright (C) 2023-2026 Spacemit Inc.
+ * Copyright (C) 2026 RISCstar Ltd.
+ */
+
+#define LOG_CATEGORY UCLASS_MMC
+
+#include <clk.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <log.h>
+#include <malloc.h>
+#include <sdhci.h>
+#include <reset-uclass.h>
+#include <mapmem.h>
+#include <dm/pinctrl.h>
+#include <linux/bitfield.h>
+#include <linux/iopoll.h>
+#include <linux/libfdt.h>
+#include <linux/delay.h>
+#include <power/regulator.h>
+
+/* SDH register definitions */
+#define SPACEMIT_SDHC_OP_EXT_REG 0x108
+#define SDHC_OVRRD_CLK_OEN BIT(11)
+#define SDHC_FORCE_CLK_ON BIT(12)
+
+#define SPACEMIT_SDHC_LEGACY_CTRL_REG 0x10C
+#define SDHC_GEN_PAD_CLK_ON BIT(6)
+
+#define SPACEMIT_SDHC_MMC_CTRL_REG 0x114
+#define SDHC_MISC_INT_EN BIT(1)
+#define SDHC_MISC_INT BIT(2)
+#define SDHC_ENHANCE_STROBE_EN BIT(8)
+#define SDHC_MMC_HS400 BIT(9)
+#define SDHC_MMC_HS200 BIT(10)
+#define SDHC_MMC_CARD_MODE BIT(12)
+
+#define SPACEMIT_SDHC_TX_CFG_REG 0x11C
+#define SDHC_TX_INT_CLK_SEL BIT(30)
+#define SDHC_TX_MUX_SEL BIT(31)
+
+#define SPACEMIT_SDHC_PHY_CTRL_REG 0x160
+#define SDHC_PHY_FUNC_EN BIT(0)
+#define SDHC_PHY_PLL_LOCK BIT(1)
+#define SDHC_HOST_LEGACY_MODE BIT(31)
+
+#define SPACEMIT_SDHC_PHY_FUNC_REG 0x164
+#define SDHC_PHY_TEST_EN BIT(7)
+#define SDHC_HS200_USE_RFIFO BIT(15)
+
+#define SPACEMIT_SDHC_PHY_DLLCFG 0x168
+#define SDHC_DLL_PREDLY_NUM GENMASK(3, 2)
+#define SDHC_DLL_FULLDLY_RANGE GENMASK(5, 4)
+#define SDHC_DLL_VREG_CTRL GENMASK(7, 6)
+#define SDHC_DLL_ENABLE BIT(31)
+
+#define SPACEMIT_SDHC_PHY_DLLCFG1 0x16C
+#define SDHC_DLL_REG1_CTRL GENMASK(7, 0)
+#define SDHC_DLL_REG2_CTRL GENMASK(15, 8)
+#define SDHC_DLL_REG3_CTRL GENMASK(23, 16)
+#define SDHC_DLL_REG4_CTRL GENMASK(31, 24)
+#define SDHC_DLL_REG1_HS400_VAL 0x92
+
+#define SPACEMIT_SDHC_PHY_DLLSTS 0x170
+#define SDHC_DLL_LOCK_STATE BIT(0)
+
+#define SPACEMIT_SDHC_PHY_PADCFG_REG 0x178
+#define SDHC_PHY_DRIVE_SEL GENMASK(2, 0)
+#define SDHC_RX_BIAS_CTRL BIT(5)
+
+#define SPACEMIT_SDHC_RX_CFG_REG 0x118
+#define SDHC_RX_SDCLK_SEL0_MASK GENMASK(1, 0)
+#define SDHC_RX_SDCLK_SEL1_MASK GENMASK(3, 2)
+#define SDHC_RX_SDCLK_SEL1 FIELD_PREP(SDHC_RX_SDCLK_SEL1_MASK, 1)
+
+#define SPACEMIT_SDHC_DLINE_CTRL_REG 0x130
+#define SDHC_DLINE_PU BIT(0)
+#define SDHC_RX_DLINE_CODE_MASK GENMASK(23, 16)
+#define SDHC_TX_DLINE_CODE_MASK GENMASK(31, 24)
+
+#define SPACEMIT_SDHC_DLINE_CFG_REG 0x134
+#define SDHC_RX_DLINE_REG_MASK GENMASK(7, 0)
+#define SDHC_RX_DLINE_GAIN BIT(8)
+#define SDHC_TX_DLINE_REG_MASK GENMASK(23, 16)
+
+#define SPACEMIT_RX_DLINE_REG 9
+#define SPACEMIT_RX_TUNE_DELAY_MIN 0x0
+#define SPACEMIT_RX_TUNE_DELAY_MAX 0xFF
+
+#define SPACEMIT_TX_TUNING_DLINE_REG 0x00
+#define SPACEMIT_TX_TUNING_DELAYCODE 127
+
+struct spacemit_sdhci_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+ struct reset_ctl_bulk resets;
+ struct clk_bulk clks;
+};
+
+struct spacemit_sdhci_priv {
+ struct sdhci_host host;
+};
+
+/* All helper functions will update clr/set while preserve rest bits */
+static inline void spacemit_sdhci_setbits(struct sdhci_host *host, u32 val,
+ int reg)
+{
+ sdhci_writel(host, sdhci_readl(host, reg) | val, reg);
+}
+
+static inline void spacemit_sdhci_clrbits(struct sdhci_host *host, u32 val,
+ int reg)
+{
+ sdhci_writel(host, sdhci_readl(host, reg) & ~val, reg);
+}
+
+static inline void spacemit_sdhci_clrsetbits(struct sdhci_host *host, u32 clr,
+ u32 set, int reg)
+{
+ u32 val = sdhci_readl(host, reg);
+
+ val = (val & ~clr) | set;
+ sdhci_writel(host, val, reg);
+}
+
+#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
+static void spacemit_sdhci_set_rx_delay(struct sdhci_host *host, u8 delay)
+{
+ spacemit_sdhci_clrsetbits(host, SDHC_RX_DLINE_CODE_MASK,
+ FIELD_PREP(SDHC_RX_DLINE_CODE_MASK, delay),
+ SPACEMIT_SDHC_DLINE_CTRL_REG);
+}
+
+static void spacemit_sdhci_set_tx_delay(struct sdhci_host *host, u8 delay)
+{
+ spacemit_sdhci_clrsetbits(host, SDHC_TX_DLINE_CODE_MASK,
+ FIELD_PREP(SDHC_TX_DLINE_CODE_MASK, delay),
+ SPACEMIT_SDHC_DLINE_CTRL_REG);
+}
+
+static void spacemit_sdhci_set_tx_dline_reg(struct sdhci_host *host,
+ u8 dline_reg)
+{
+ spacemit_sdhci_clrsetbits(host, SDHC_TX_DLINE_REG_MASK,
+ FIELD_PREP(SDHC_TX_DLINE_REG_MASK, dline_reg),
+ SPACEMIT_SDHC_DLINE_CFG_REG);
+}
+
+static void spacemit_sdhci_tx_tuning_prepare(struct sdhci_host *host)
+{
+ spacemit_sdhci_setbits(host, SDHC_TX_MUX_SEL, SPACEMIT_SDHC_TX_CFG_REG);
+ spacemit_sdhci_setbits(host, SDHC_DLINE_PU,
+ SPACEMIT_SDHC_DLINE_CTRL_REG);
+ udelay(5);
+}
+
+static void spacemit_sdhci_prepare_tuning(struct sdhci_host *host)
+{
+ spacemit_sdhci_clrsetbits(host, SDHC_RX_DLINE_REG_MASK,
+ FIELD_PREP(SDHC_RX_DLINE_REG_MASK, SPACEMIT_RX_DLINE_REG),
+ SPACEMIT_SDHC_DLINE_CFG_REG);
+
+ spacemit_sdhci_setbits(host, SDHC_DLINE_PU,
+ SPACEMIT_SDHC_DLINE_CTRL_REG);
+ udelay(5);
+
+ spacemit_sdhci_clrsetbits(host, SDHC_RX_SDCLK_SEL1_MASK,
+ SDHC_RX_SDCLK_SEL1,
+ SPACEMIT_SDHC_RX_CFG_REG);
+
+ if (host->mmc->selected_mode == MMC_HS_200)
+ spacemit_sdhci_setbits(host, SDHC_HS200_USE_RFIFO,
+ SPACEMIT_SDHC_PHY_FUNC_REG);
+}
+#endif /* MMC_SUPPORTS_TUNING */
+
+/*
+ * Reference: PMU_SDH0_CLK_RES_CTRL (0x054), SDH0_CLK_SEL=0x0,
+ * SDH0_CLK_DIV=0x1. The default clock source is 204.8 MHz
+ * (pll1_d6_409p6Mhz / 2).
+ *
+ * During start-up, use a 200 kHz frequency.
+ */
+#define SDHC_MIN_CLOCK (200 * 1000)
+
+static void spacemit_sdhci_phy_init(struct udevice *dev,
+ struct sdhci_host *host)
+{
+ u32 reg = 0;
+
+ if (dev_read_bool(dev, "no-sd") && dev_read_bool(dev, "no-sdio")) {
+ /* MMC card mode */
+ reg = sdhci_readl(host, SPACEMIT_SDHC_MMC_CTRL_REG);
+ reg |= SDHC_MMC_CARD_MODE;
+ sdhci_writel(host, reg, SPACEMIT_SDHC_MMC_CTRL_REG);
+
+ /* Use PHY functional mode */
+ reg = sdhci_readl(host, SPACEMIT_SDHC_PHY_CTRL_REG);
+ reg |= (SDHC_PHY_FUNC_EN | SDHC_PHY_PLL_LOCK);
+ sdhci_writel(host, reg, SPACEMIT_SDHC_PHY_CTRL_REG);
+
+ reg = sdhci_readl(host, SPACEMIT_SDHC_PHY_PADCFG_REG);
+ reg |= SDHC_RX_BIAS_CTRL;
+ sdhci_writel(host, reg, SPACEMIT_SDHC_PHY_PADCFG_REG);
+ } else {
+ reg = sdhci_readl(host, SPACEMIT_SDHC_TX_CFG_REG);
+ reg |= SDHC_TX_INT_CLK_SEL;
+ sdhci_writel(host, reg, SPACEMIT_SDHC_TX_CFG_REG);
+ }
+
+ reg = sdhci_readl(host, SPACEMIT_SDHC_MMC_CTRL_REG);
+ reg &= ~SDHC_ENHANCE_STROBE_EN;
+ sdhci_writel(host, reg, SPACEMIT_SDHC_MMC_CTRL_REG);
+}
+
+static int spacemit_sdhci_set_vqmmc_voltage(struct mmc *mmc, int voltage)
+{
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ int ret;
+
+ if (!mmc->vqmmc_supply)
+ return 0;
+
+ ret = regulator_set_value(mmc->vqmmc_supply, voltage);
+ if (ret)
+ return ret;
+ ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
+ if (ret)
+ return ret;
+#endif
+ return 0;
+}
+
+static void spacemit_sdhci_set_voltage(struct sdhci_host *host)
+{
+ if (IS_ENABLED(CONFIG_MMC_IO_VOLTAGE)) {
+ struct mmc *mmc = host->mmc;
+ u32 ctrl;
+
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+
+ switch (mmc->signal_voltage) {
+ case MMC_SIGNAL_VOLTAGE_330:
+ case MMC_SIGNAL_VOLTAGE_180: {
+ bool to_180 = mmc->signal_voltage ==
+ MMC_SIGNAL_VOLTAGE_180;
+ bool ok;
+ int voltage_mv = to_180 ? 1800000 : 3300000;
+
+ if (spacemit_sdhci_set_vqmmc_voltage(mmc, voltage_mv))
+ return;
+ if (!IS_SD(mmc))
+ return;
+ if (to_180)
+ ctrl |= SDHCI_CTRL_VDD_180;
+ else
+ ctrl &= ~SDHCI_CTRL_VDD_180;
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+
+ mdelay(5);
+
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ ok = !!(ctrl & SDHCI_CTRL_VDD_180) == to_180;
+ if (ok)
+ return;
+
+ log_err("%d.%dV regulator output not stable\n",
+ voltage_mv / 1000000,
+ (voltage_mv / 100000) % 10);
+ break;
+ }
+ default:
+ /* No signal voltage switch required */
+ return;
+ }
+ }
+}
+
+static void spacemit_sdhci_set_clk_gate(struct sdhci_host *host, int auto_gate)
+{
+ u32 reg;
+
+ reg = sdhci_readl(host, SPACEMIT_SDHC_OP_EXT_REG);
+ if (auto_gate)
+ reg &= ~(SDHC_OVRRD_CLK_OEN | SDHC_FORCE_CLK_ON);
+ else
+ reg |= (SDHC_OVRRD_CLK_OEN | SDHC_FORCE_CLK_ON);
+ sdhci_writel(host, reg, SPACEMIT_SDHC_OP_EXT_REG);
+}
+
+static bool spacemit_sdhci_is_voltage_switch_cmd(struct sdhci_host *host)
+{
+ struct mmc *mmc = host->mmc;
+ u32 cmd;
+
+ if (!IS_SD(mmc))
+ return false;
+
+ cmd = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
+ return cmd == SD_CMD_SWITCH_UHS18V &&
+ mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180;
+}
+
+static int spacemit_sdhci_wait_dat0(struct udevice *dev, int state,
+ int timeout_us)
+{
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+ struct sdhci_host *host = mmc->priv;
+ u32 tmp;
+ int ret;
+
+ ret = read_poll_timeout(sdhci_readl, tmp,
+ !!(tmp & SDHCI_DATA_0_LVL_MASK) == !!state,
+ 0, timeout_us, host, SDHCI_PRESENT_STATE);
+ if (ret)
+ return ret;
+
+ if (spacemit_sdhci_is_voltage_switch_cmd(host))
+ spacemit_sdhci_set_clk_gate(host, 1);
+ return 0;
+}
+
+static void spacemit_sdhci_set_control_reg(struct sdhci_host *host)
+{
+ struct mmc *mmc = host->mmc;
+ u32 reg;
+
+ spacemit_sdhci_set_voltage(host);
+
+ if (spacemit_sdhci_is_voltage_switch_cmd(host))
+ spacemit_sdhci_set_clk_gate(host, 0);
+
+ /*
+ * Set TX_INT_CLK_SEL to guarantee hold time at default speed,
+ * HS, SDR12/SDR25/SDR50 modes. See SDHC_TX_CFG_REG (0x11c).
+ */
+ reg = sdhci_readl(host, SPACEMIT_SDHC_TX_CFG_REG);
+ if (mmc->selected_mode == MMC_LEGACY ||
+ mmc->selected_mode == MMC_HS ||
+ mmc->selected_mode == SD_HS ||
+ mmc->selected_mode == UHS_SDR12 ||
+ mmc->selected_mode == UHS_SDR25 ||
+ mmc->selected_mode == UHS_SDR50) {
+ reg |= SDHC_TX_INT_CLK_SEL;
+ } else {
+ reg &= ~SDHC_TX_INT_CLK_SEL;
+ }
+ sdhci_writel(host, reg, SPACEMIT_SDHC_TX_CFG_REG);
+
+ /* Set pinctrl state based on selected timing mode */
+ if (IS_ENABLED(CONFIG_PINCTRL)) {
+ switch (mmc->selected_mode) {
+ case UHS_SDR12:
+ case UHS_SDR25:
+ case UHS_SDR50:
+ case UHS_SDR104:
+ pinctrl_select_state(mmc->dev, "uhs");
+ break;
+ default:
+ pinctrl_select_state(mmc->dev, "default");
+ break;
+ }
+ }
+
+ if (mmc->selected_mode == MMC_HS_200 ||
+ mmc->selected_mode == MMC_HS_400 ||
+ mmc->selected_mode == MMC_HS_400_ES) {
+ reg = sdhci_readw(host, SPACEMIT_SDHC_MMC_CTRL_REG);
+ if (mmc->selected_mode == MMC_HS_200)
+ reg |= SDHC_MMC_HS200;
+ else
+ reg |= SDHC_MMC_HS400;
+ sdhci_writew(host, reg, SPACEMIT_SDHC_MMC_CTRL_REG);
+ } else {
+ reg = sdhci_readw(host, SPACEMIT_SDHC_MMC_CTRL_REG);
+ reg &= ~(SDHC_MMC_HS200 | SDHC_MMC_HS400 | SDHC_ENHANCE_STROBE_EN);
+ sdhci_writew(host, reg, SPACEMIT_SDHC_MMC_CTRL_REG);
+ }
+
+ sdhci_set_uhs_timing(host);
+}
+
+#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
+static int spacemit_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
+{
+ struct sdhci_host *host = mmc->priv;
+ int current_len = 0, current_start = 0;
+ int max_pass_len = 0, max_pass_start = 0;
+ u8 final_delay;
+ int ret = 0;
+ int i;
+
+ /*
+ * Tuning is required for SDR50/SDR104, HS200/HS400 cards and
+ * if clock frequency is greater than 100MHz in these modes.
+ */
+ if (host->clock < 100 * 1000 * 1000 ||
+ !(mmc->selected_mode == MMC_HS_200 ||
+ mmc->selected_mode == UHS_SDR50 ||
+ mmc->selected_mode == UHS_SDR104))
+ return 0;
+
+ if (IS_SD(host->mmc)) {
+ spacemit_sdhci_set_tx_dline_reg(host, SPACEMIT_TX_TUNING_DLINE_REG);
+ spacemit_sdhci_set_tx_delay(host, SPACEMIT_TX_TUNING_DELAYCODE);
+ spacemit_sdhci_tx_tuning_prepare(host);
+
+ log_debug("TX tuning: dline_reg=%d, delaycode=%d\n",
+ SPACEMIT_TX_TUNING_DLINE_REG, SPACEMIT_TX_TUNING_DELAYCODE);
+ }
+
+ spacemit_sdhci_prepare_tuning(host);
+
+ for (i = SPACEMIT_RX_TUNE_DELAY_MIN; i <= SPACEMIT_RX_TUNE_DELAY_MAX; i++) {
+ spacemit_sdhci_set_rx_delay(host, i);
+ ret = mmc_send_tuning(host->mmc, opcode);
+
+ log_debug("RX delay %d: %s\n",
+ i, ret == 0 ? "pass" : "fail");
+
+ if (ret == 0) {
+ /* Test passed - extend current window */
+ if (current_len == 0)
+ current_start = i;
+ current_len++;
+ } else {
+ /* Test failed - check if current window is best so far */
+ if (current_len > max_pass_len) {
+ max_pass_len = current_len;
+ max_pass_start = current_start;
+ }
+ current_len = 0;
+ }
+ }
+
+ if (current_len > max_pass_len) {
+ max_pass_len = current_len;
+ max_pass_start = current_start;
+ }
+
+ if (max_pass_len < 3) {
+ log_err("Tuning failed: no stable window found\n");
+ return -EIO;
+ }
+
+ final_delay = max_pass_start + max_pass_len / 2;
+ spacemit_sdhci_set_rx_delay(host, final_delay);
+ ret = mmc_send_tuning(host->mmc, opcode);
+ if (ret) {
+ u8 retry_delays[] = {
+ max_pass_start + max_pass_len / 4,
+ max_pass_start + (3 * max_pass_len) / 4,
+ max_pass_start,
+ max_pass_start + max_pass_len - 1
+ };
+ int retry_count = ARRAY_SIZE(retry_delays);
+
+ log_warning("Primary delay %d failed, trying alternatives\n",
+ final_delay);
+
+ for (i = 0; i < retry_count; i++) {
+ if (retry_delays[i] >= SPACEMIT_RX_TUNE_DELAY_MIN &&
+ retry_delays[i] <= SPACEMIT_RX_TUNE_DELAY_MAX) {
+ spacemit_sdhci_set_rx_delay(host, retry_delays[i]);
+ ret = mmc_send_tuning(host->mmc, opcode);
+ if (!ret) {
+ final_delay = retry_delays[i];
+ log_info("Retry successful with delay %d\n",
+ final_delay);
+ break;
+ }
+ }
+ }
+
+ if (ret) {
+ log_err("All retry attempts failed\n");
+ return -EIO;
+ }
+ }
+
+ log_debug("Tuning successful: window %d-%d, using delay %d\n",
+ max_pass_start, max_pass_start + max_pass_len - 1, final_delay);
+
+ return 0;
+}
+#endif /* MMC_SUPPORTS_TUNING */
+
+#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
+static int spacemit_sdhci_phy_dll_init(struct sdhci_host *host)
+{
+ u32 reg, val;
+ int ret;
+
+ /* Configure DLL predly, fulldly, and vreg */
+ spacemit_sdhci_clrsetbits(host, SDHC_DLL_PREDLY_NUM |
+ SDHC_DLL_FULLDLY_RANGE |
+ SDHC_DLL_VREG_CTRL,
+ FIELD_PREP(SDHC_DLL_PREDLY_NUM, 1) |
+ FIELD_PREP(SDHC_DLL_FULLDLY_RANGE, 1) |
+ FIELD_PREP(SDHC_DLL_VREG_CTRL, 1),
+ SPACEMIT_SDHC_PHY_DLLCFG);
+
+ reg = sdhci_readl(host, SPACEMIT_SDHC_PHY_DLLCFG1);
+ reg |= FIELD_PREP(SDHC_DLL_REG1_CTRL, SDHC_DLL_REG1_HS400_VAL);
+ sdhci_writel(host, reg, SPACEMIT_SDHC_PHY_DLLCFG1);
+
+ /* Enable DLL */
+ reg = sdhci_readl(host, SPACEMIT_SDHC_PHY_DLLCFG);
+ reg |= SDHC_DLL_ENABLE;
+ sdhci_writel(host, reg, SPACEMIT_SDHC_PHY_DLLCFG);
+
+ /* Wait for DLL lock */
+ ret = read_poll_timeout(sdhci_readl, val, val & SDHC_DLL_LOCK_STATE,
+ 10, 1000, host, SPACEMIT_SDHC_PHY_DLLSTS);
+ if (ret) {
+ log_err("%s: phy dll lock timeout\n", host->name);
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static int spacemit_sdhci_hs400_enhanced_strobe(struct sdhci_host *host)
+{
+ u32 reg;
+
+ reg = sdhci_readl(host, SPACEMIT_SDHC_MMC_CTRL_REG);
+ reg |= SDHC_ENHANCE_STROBE_EN;
+ sdhci_writel(host, reg, SPACEMIT_SDHC_MMC_CTRL_REG);
+
+ return spacemit_sdhci_phy_dll_init(host);
+}
+#endif
+
+const struct sdhci_ops spacemit_sdhci_ops = {
+ .set_control_reg = spacemit_sdhci_set_control_reg,
+#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
+ .platform_execute_tuning = spacemit_sdhci_execute_tuning,
+#endif
+#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
+ .set_enhanced_strobe = spacemit_sdhci_hs400_enhanced_strobe,
+#endif
+};
+
+static struct dm_mmc_ops spacemit_mmc_ops;
+
+static int spacemit_sdhci_probe(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct spacemit_sdhci_priv *priv = dev_get_priv(dev);
+ struct spacemit_sdhci_plat *plat = dev_get_plat(dev);
+ struct sdhci_host *host = &priv->host;
+ struct clk clk;
+ int ret = 0;
+
+ host->mmc = &plat->mmc;
+ host->mmc->priv = host;
+ host->mmc->dev = dev;
+ upriv->mmc = host->mmc;
+
+ spacemit_mmc_ops = sdhci_ops;
+ spacemit_mmc_ops.wait_dat0 = spacemit_sdhci_wait_dat0;
+
+ ret = clk_get_bulk(dev, &plat->clks);
+ if (ret) {
+ log_err("Can't get clk: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_enable_bulk(&plat->clks);
+ if (ret) {
+ log_err("Failed to enable clk: %d\n", ret);
+ goto err_clk;
+ }
+
+ ret = reset_get_bulk(dev, &plat->resets);
+ if (ret) {
+ log_err("Can't get reset: %d\n", ret);
+ goto err_clk;
+ }
+
+ ret = reset_deassert_bulk(&plat->resets);
+ if (ret) {
+ log_err("Failed to reset: %d\n", ret);
+ goto err_reset;
+ }
+
+ ret = clk_get_by_index(dev, 1, &clk);
+ if (ret) {
+ log_err("Can't get io clk: %d\n", ret);
+ goto err_reset;
+ }
+
+ ret = clk_set_rate(&clk, plat->cfg.f_max);
+ if (ret) {
+ log_err("Failed to set io clk: %d\n", ret);
+ goto err_reset;
+ }
+
+ /* Set quirks */
+ host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
+ SDHCI_QUIRK_32BIT_DMA_ADDR;
+ host->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz;
+ host->max_clk = plat->cfg.f_max;
+
+ plat->cfg.f_min = SDHC_MIN_CLOCK;
+ host->ops = &spacemit_sdhci_ops;
+
+ ret = sdhci_setup_cfg(&plat->cfg, host, plat->cfg.f_max,
+ SDHC_MIN_CLOCK);
+ if (ret)
+ goto err_reset;
+
+ ret = sdhci_probe(dev);
+ if (ret)
+ goto err_reset;
+
+ spacemit_sdhci_phy_init(dev, host);
+ return 0;
+
+err_reset:
+ reset_release_bulk(&plat->resets);
+err_clk:
+ clk_release_bulk(&plat->clks);
+ return ret;
+}
+
+static int spacemit_sdhci_of_to_plat(struct udevice *dev)
+{
+ struct spacemit_sdhci_plat *plat = dev_get_plat(dev);
+ struct spacemit_sdhci_priv *priv = dev_get_priv(dev);
+ struct sdhci_host *host = &priv->host;
+ int ret = 0;
+
+ host->name = dev->name;
+ host->ioaddr = (void *)dev_read_addr(dev);
+
+ ret = mmc_of_parse(dev, &plat->cfg);
+
+ return ret;
+}
+
+static int spacemit_sdhci_bind(struct udevice *dev)
+{
+ struct spacemit_sdhci_plat *drv_data;
+ struct spacemit_sdhci_plat *plat = dev_get_plat(dev);
+
+ drv_data = (struct spacemit_sdhci_plat *)dev_get_driver_data(dev);
+ if (drv_data)
+ memcpy(plat, drv_data, sizeof(struct spacemit_sdhci_plat));
+ return sdhci_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+static const struct udevice_id spacemit_sdhci_ids[] = {
+ { .compatible = "spacemit,k1-sdhci" },
+ { }
+};
+
+U_BOOT_DRIVER(spacemit_sdhci_drv) = {
+ .name = "spacemit_sdhci",
+ .id = UCLASS_MMC,
+ .of_match = spacemit_sdhci_ids,
+ .of_to_plat = spacemit_sdhci_of_to_plat,
+ .ops = &spacemit_mmc_ops,
+ .bind = spacemit_sdhci_bind,
+ .probe = spacemit_sdhci_probe,
+ .priv_auto = sizeof(struct spacemit_sdhci_priv),
+ .plat_auto = sizeof(struct spacemit_sdhci_plat),
+};
--
2.51.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v8 06/11] dts: k1: add SD card support in u-boot overlay
2026-08-01 16:40 [PATCH v8 00/11] spacemit mmc driver Eric Chung
` (4 preceding siblings ...)
2026-08-01 16:40 ` [PATCH v8 05/11] mmc: k1: add sdhci platform driver Eric Chung
@ 2026-08-01 16:40 ` Eric Chung
2026-08-16 4:15 ` Yixun Lan
2026-08-01 16:40 ` [PATCH v8 07/11] configs: k1: enable SD and eMMC support Eric Chung
` (4 subsequent siblings)
10 siblings, 1 reply; 13+ messages in thread
From: Eric Chung @ 2026-08-01 16:40 UTC (permalink / raw)
To: u-boot-spacemit, u-boot, u-boot
Cc: Tom Rini, Tim Ouyang, Leo Liang, Peng Fan, Huan Zhou, Raymond Mao,
Jaehoon Chung, Bhimeswararao Matsa, Tanmay Kathpalia,
Kaustabh Chakraborty, Han Xu, Yanir Levin, Christoph Stoidner,
Balsundar Ponnusamy, Daniel Palmer, Anshul Dalal,
Bastien Curutchet, Angelo Dureghello, Johan Jonker, Sam Protsenko,
Guodong Xu, Yao Zi, Rick Chen, Leo, Eric Chung
Add the SDH0 controller node and its pinctrl groups to the u-boot
overlay. The upstream DTS only contains the eMMC node; the SD card
controller (sdhci@d4280000) and its MMC1 pinctrl configuration are
missing. Place the new node inside the storage-bus via path-based
merge so it inherits the dma-ranges from the parent bus.
Signed-off-by: Eric Chung <eric.chung@riscstar.com>
---
v5:
- Append power source field on eMMC/SD pinctrl.
v3:
- Fix SD pinctrl as uhs.
v2:
- Use vmmc-supply as vqmmc-supply on SD node.
- Add alias of mmc0 and mmc1.
---
arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi | 91 ++++++++++++++++++++++++++++++-
arch/riscv/dts/k1-musepi-pro-u-boot.dtsi | 86 ++++++++++++++++++++++++++++-
2 files changed, 173 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi b/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi
index 7f9443d69510..4823cbc1f339 100644
--- a/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi
+++ b/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi
@@ -6,6 +6,11 @@
#include "binman.dtsi"
/ {
+ aliases {
+ mmc0 = &emmc;
+ mmc1 = &sdhci0;
+ };
+
memory@0 {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
@@ -76,12 +81,14 @@
bootph-pre-ram;
};
- buck3 {
+ buck3_1v8: buck3 {
regulator-name = "vdd_1v8";
bootph-pre-ram;
};
- aldo1 {
+ buck4_3v3: buck4 { };
+
+ aldo1: aldo1 {
regulator-name = "vdd_1v8_mmc";
bootph-pre-ram;
};
@@ -89,6 +96,86 @@
};
};
+/ {
+ soc {
+ storage-bus {
+ sdhci0: mmc@d4280000 {
+ bootph-pre-ram;
+ compatible = "spacemit,k1-sdhci";
+ reg = <0x0 0xd4280000 0x0 0x200>;
+ clocks = <&syscon_apmu CLK_SDH_AXI>,
+ <&syscon_apmu CLK_SDH0>;
+ clock-names = "core", "io";
+ interrupts = <99>;
+ resets = <&syscon_apmu RESET_SDH_AXI>,
+ <&syscon_apmu RESET_SDH0>;
+ reset-names = "sdh_axi", "sdh0";
+ bus-width = <4>;
+ max-frequency = <204800000>;
+ cd-gpios = <&gpio K1_GPIO(80) GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default", "uhs";
+ pinctrl-0 = <&sdhci0_0_cfg>;
+ pinctrl-1 = <&sdhci0_1_cfg>;
+ status = "okay";
+ };
+ };
+ };
+};
+
+/* SD card pinctrl groups -- not present in upstream k1-pinctrl.dtsi */
+&pinctrl {
+ sdhci0_0_cfg: sdhci0-0-cfg {
+ grp_cmd_data {
+ pinmux = <K1_PADCONF(104, 0)>, /* MMC1_DAT3 */
+ <K1_PADCONF(105, 0)>, /* MMC1_DAT2 */
+ <K1_PADCONF(106, 0)>, /* MMC1_DAT1 */
+ <K1_PADCONF(107, 0)>, /* MMC1_DAT0 */
+ <K1_PADCONF(108, 0)>; /* MMC1_CMD */
+ bias-pull-up = <1>;
+ drive-strength = <19>;
+ power-source = <3300>;
+ };
+ grp_clk {
+ pinmux = <K1_PADCONF(109, 0)>; /* MMC1_CLK */
+ bias-pull-down = <1>;
+ drive-strength = <19>;
+ power-source = <3300>;
+ };
+ };
+
+ sdhci0_1_cfg: sdhci0-1-cfg { /* uhs */
+ grp_cmd_data {
+ pinmux = <K1_PADCONF(104, 0)>, /* MMC1_DAT3 */
+ <K1_PADCONF(105, 0)>, /* MMC1_DAT2 */
+ <K1_PADCONF(106, 0)>, /* MMC1_DAT1 */
+ <K1_PADCONF(107, 0)>, /* MMC1_DAT0 */
+ <K1_PADCONF(108, 0)>; /* MMC1_CMD */
+ bias-pull-up = <1>;
+ drive-strength = <42>;
+ power-source = <1800>;
+ };
+ grp_clk {
+ pinmux = <K1_PADCONF(109, 0)>; /* MMC1_CLK */
+ bias-pull-down = <1>;
+ drive-strength = <42>;
+ power-source = <1800>;
+ };
+ };
+};
+
+&emmc {
+ bootph-pre-ram;
+ resets = <&syscon_apmu RESET_SDH_AXI>, <&syscon_apmu RESET_SDH2>;
+ reset-names = "sdh_axi", "sdh2";
+ vqmmc-supply = <&buck3_1v8>;
+ vmmc-supply = <&aldo1>;
+ max-frequency = <204800000>;
+};
+
+&sdhci0 {
+ vmmc-supply = <&buck4_3v3>;
+};
+
&binman {
u-boot-spl-ddr {
type = "section";
diff --git a/arch/riscv/dts/k1-musepi-pro-u-boot.dtsi b/arch/riscv/dts/k1-musepi-pro-u-boot.dtsi
index 8a9a2a09de99..f730f79e3e7a 100644
--- a/arch/riscv/dts/k1-musepi-pro-u-boot.dtsi
+++ b/arch/riscv/dts/k1-musepi-pro-u-boot.dtsi
@@ -10,6 +10,8 @@
aliases {
console = &uart0;
serial0 = &uart0;
+ mmc0 = &emmc;
+ mmc1 = &sdhci0;
};
chosen {
@@ -147,7 +149,7 @@
regulator-always-on;
};
- buck4 {
+ buck4_3v3: buck4 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <5000>;
@@ -168,7 +170,7 @@
regulator-always-on;
};
- aldo1 {
+ aldo1: aldo1 {
bootph-pre-ram;
regulator-name = "vdd_1v8_mmc";
regulator-min-microvolt = <500000>;
@@ -249,6 +251,86 @@
};
};
+/ {
+ soc {
+ storage-bus {
+ sdhci0: mmc@d4280000 {
+ bootph-pre-ram;
+ compatible = "spacemit,k1-sdhci";
+ reg = <0x0 0xd4280000 0x0 0x200>;
+ clocks = <&syscon_apmu CLK_SDH_AXI>,
+ <&syscon_apmu CLK_SDH0>;
+ clock-names = "core", "io";
+ interrupts = <99>;
+ resets = <&syscon_apmu RESET_SDH_AXI>,
+ <&syscon_apmu RESET_SDH0>;
+ reset-names = "sdh_axi", "sdh0";
+ bus-width = <4>;
+ max-frequency = <204800000>;
+ cd-gpios = <&gpio K1_GPIO(80) GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default", "uhs";
+ pinctrl-0 = <&sdhci0_0_cfg>;
+ pinctrl-1 = <&sdhci0_1_cfg>;
+ status = "okay";
+ };
+ };
+ };
+};
+
+/* SD card pinctrl groups -- not present in upstream k1-pinctrl.dtsi */
+&pinctrl {
+ sdhci0_0_cfg: sdhci0-0-cfg {
+ grp_cmd_data {
+ pinmux = <K1_PADCONF(104, 0)>, /* MMC1_DAT3 */
+ <K1_PADCONF(105, 0)>, /* MMC1_DAT2 */
+ <K1_PADCONF(106, 0)>, /* MMC1_DAT1 */
+ <K1_PADCONF(107, 0)>, /* MMC1_DAT0 */
+ <K1_PADCONF(108, 0)>; /* MMC1_CMD */
+ bias-pull-up = <1>;
+ drive-strength = <19>;
+ power-source = <3300>;
+ };
+ grp_clk {
+ pinmux = <K1_PADCONF(109, 0)>; /* MMC1_CLK */
+ bias-pull-down = <1>;
+ drive-strength = <19>;
+ power-source = <3300>;
+ };
+ };
+
+ sdhci0_1_cfg: sdhci0-1-cfg { /* uhs */
+ grp_cmd_data {
+ pinmux = <K1_PADCONF(104, 0)>, /* MMC1_DAT3 */
+ <K1_PADCONF(105, 0)>, /* MMC1_DAT2 */
+ <K1_PADCONF(106, 0)>, /* MMC1_DAT1 */
+ <K1_PADCONF(107, 0)>, /* MMC1_DAT0 */
+ <K1_PADCONF(108, 0)>; /* MMC1_CMD */
+ bias-pull-up = <1>;
+ drive-strength = <42>;
+ power-source = <1800>;
+ };
+ grp_clk {
+ pinmux = <K1_PADCONF(109, 0)>; /* MMC1_CLK */
+ bias-pull-down = <1>;
+ drive-strength = <42>;
+ power-source = <1800>;
+ };
+ };
+};
+
+&emmc {
+ bootph-pre-ram;
+ resets = <&syscon_apmu RESET_SDH_AXI>, <&syscon_apmu RESET_SDH2>;
+ reset-names = "sdh_axi", "sdh2";
+ vqmmc-supply = <&buck3_1v8>;
+ vmmc-supply = <&aldo1>;
+ max-frequency = <204800000>;
+};
+
+&sdhci0 {
+ vmmc-supply = <&buck4_3v3>;
+};
+
&binman {
u-boot-spl-ddr {
type = "section";
--
2.51.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v8 06/11] dts: k1: add SD card support in u-boot overlay
2026-08-01 16:40 ` [PATCH v8 06/11] dts: k1: add SD card support in u-boot overlay Eric Chung
@ 2026-08-16 4:15 ` Yixun Lan
0 siblings, 0 replies; 13+ messages in thread
From: Yixun Lan @ 2026-08-16 4:15 UTC (permalink / raw)
To: Eric Chung
Cc: u-boot-spacemit, u-boot, Tom Rini, Tim Ouyang, Leo Liang,
Peng Fan, Huan Zhou, Raymond Mao, Jaehoon Chung,
Bhimeswararao Matsa, Tanmay Kathpalia, Kaustabh Chakraborty,
Han Xu, Yanir Levin, Christoph Stoidner, Balsundar Ponnusamy,
Daniel Palmer, Anshul Dalal, Bastien Curutchet, Angelo Dureghello,
Johan Jonker, Sam Protsenko, Guodong Xu, Yao Zi, Rick Chen, Leo
Hi Eric,
On 00:40 Sun 02 Aug , Eric Chung wrote:
> Add the SDH0 controller node and its pinctrl groups to the u-boot
> overlay. The upstream DTS only contains the eMMC node; the SD card
> controller (sdhci@d4280000) and its MMC1 pinctrl configuration are
The kernel side has added SD card support, can you sync first before
adding more into the overlay?
> missing. Place the new node inside the storage-bus via path-based
> merge so it inherits the dma-ranges from the parent bus.
>
> Signed-off-by: Eric Chung <eric.chung@riscstar.com>
>
> ---
--
Yixun Lan (dlan)
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v8 07/11] configs: k1: enable SD and eMMC support
2026-08-01 16:40 [PATCH v8 00/11] spacemit mmc driver Eric Chung
` (5 preceding siblings ...)
2026-08-01 16:40 ` [PATCH v8 06/11] dts: k1: add SD card support in u-boot overlay Eric Chung
@ 2026-08-01 16:40 ` Eric Chung
2026-08-01 16:40 ` [PATCH v8 08/11] MAINTAINER: update Spacemit K1 entry Eric Chung
` (3 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Eric Chung @ 2026-08-01 16:40 UTC (permalink / raw)
To: u-boot-spacemit, u-boot, u-boot
Cc: Tom Rini, Tim Ouyang, Leo Liang, Peng Fan, Huan Zhou, Raymond Mao,
Jaehoon Chung, Bhimeswararao Matsa, Tanmay Kathpalia,
Kaustabh Chakraborty, Han Xu, Yanir Levin, Christoph Stoidner,
Balsundar Ponnusamy, Daniel Palmer, Anshul Dalal,
Bastien Curutchet, Angelo Dureghello, Johan Jonker, Sam Protsenko,
Guodong Xu, Yao Zi, Rick Chen, Leo, Eric Chung
Enable high-speed MMC modes.
Signed-off-by: Eric Chung <eric.chung@riscstar.com>
---
v7:
- Remove mmc driver from MAINTAINERS file.
v5:
- Remove ADMA support since it depends on CMD23 support.
- Enable PINCONF support for related power source setting.
v2:
- Enable ADMA support.
- Enable SYSCON support.
---
configs/spacemit_k1_defconfig | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/configs/spacemit_k1_defconfig b/configs/spacemit_k1_defconfig
index 0604c2feefc1..c0ee3a29f233 100644
--- a/configs/spacemit_k1_defconfig
+++ b/configs/spacemit_k1_defconfig
@@ -23,6 +23,7 @@ CONFIG_DEBUG_UART_BASE=0xd4017000
CONFIG_DEBUG_UART_CLOCK=14700000
CONFIG_TARGET_SPACEMIT_K1=y
CONFIG_ARCH_RV64I=y
+CONFIG_RISCV_ISA_ZICBOM=y
CONFIG_RISCV_SMODE=y
CONFIG_SPL_RISCV_MMODE=y
# CONFIG_SPL_SMP is not set
@@ -48,6 +49,7 @@ CONFIG_SPL_CMD_TLV_EEPROM=y
CONFIG_OF_UPSTREAM=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_CLK=y
CONFIG_CLK_CCF=y
@@ -61,6 +63,7 @@ CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SPL_I2C_EEPROM=y
CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
CONFIG_PINCTRL_SPACEMIT_K1=y
CONFIG_GPIO=y
CONFIG_DM_GPIO=y
@@ -87,9 +90,26 @@ CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_MEM=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x000a0000
CONFIG_CMD_SPI=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SPACEMIT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x4
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
+CONFIG_EFI_PARTITION=y
CONFIG_SPL_SPI=y
CONFIG_SPL_DM_SPI=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_SPI_FLASH_TINY=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
--
2.51.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v8 08/11] MAINTAINER: update Spacemit K1 entry
2026-08-01 16:40 [PATCH v8 00/11] spacemit mmc driver Eric Chung
` (6 preceding siblings ...)
2026-08-01 16:40 ` [PATCH v8 07/11] configs: k1: enable SD and eMMC support Eric Chung
@ 2026-08-01 16:40 ` Eric Chung
2026-08-01 16:40 ` [PATCH v8 09/11] doc: spacemit: flash on K1 SoC based boards Eric Chung
` (2 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Eric Chung @ 2026-08-01 16:40 UTC (permalink / raw)
To: u-boot-spacemit, u-boot, u-boot
Cc: Tom Rini, Tim Ouyang, Leo Liang, Peng Fan, Huan Zhou, Raymond Mao,
Jaehoon Chung, Bhimeswararao Matsa, Tanmay Kathpalia,
Kaustabh Chakraborty, Han Xu, Yanir Levin, Christoph Stoidner,
Balsundar Ponnusamy, Daniel Palmer, Anshul Dalal,
Bastien Curutchet, Angelo Dureghello, Johan Jonker, Sam Protsenko,
Guodong Xu, Yao Zi, Rick Chen, Leo, Eric Chung
Update the maintainer for Spacemit K1 from Guodong to Eric.
Signed-off-by: Eric Chung <eric.chung@riscstar.com>
---
v7:
- Add mmc driver.
v4:
- Update the maintainer.
---
board/spacemit/k1/MAINTAINERS | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/board/spacemit/k1/MAINTAINERS b/board/spacemit/k1/MAINTAINERS
index 32d47ecc8f1e..4b2bc4ecfc10 100644
--- a/board/spacemit/k1/MAINTAINERS
+++ b/board/spacemit/k1/MAINTAINERS
@@ -1,6 +1,6 @@
BananaPi F3
M: Huan Zhou <pericycle.cc@gmail.com>
-M: Guodong Xu <guodong.xu@riscstar.com>
+M: Eric Chung <eric.chung@riscstar.com>
L: u-boot-spacemit@groups.io
S: Maintained
F: arch/riscv/dts/k1-*-u-boot.dtsi
@@ -9,6 +9,7 @@ F: configs/spacemit_k1_defconfig
F: doc/board/spacemit/bananapi-f3.rst
F: drivers/gpio/spacemit_gpio.c
F: drivers/i2c/k1_i2c.c
+F: drivers/mmc/spacemit_sdhci.c
F: drivers/pinctrl/spacemit/
F: drivers/power/pmic/pmic_spacemit_p1.c
F: drivers/power/regulator/spacemit_p1_regulator.c
--
2.51.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v8 09/11] doc: spacemit: flash on K1 SoC based boards
2026-08-01 16:40 [PATCH v8 00/11] spacemit mmc driver Eric Chung
` (7 preceding siblings ...)
2026-08-01 16:40 ` [PATCH v8 08/11] MAINTAINER: update Spacemit K1 entry Eric Chung
@ 2026-08-01 16:40 ` Eric Chung
2026-08-01 16:40 ` [PATCH v8 10/11] config: k1: enable ENV support for eMMC Eric Chung
2026-08-01 16:40 ` [PATCH v8 11/11] spacemit: k1: fix product name detection and DTB matching in SPL Eric Chung
10 siblings, 0 replies; 13+ messages in thread
From: Eric Chung @ 2026-08-01 16:40 UTC (permalink / raw)
To: u-boot-spacemit, u-boot, u-boot
Cc: Tom Rini, Tim Ouyang, Leo Liang, Peng Fan, Huan Zhou, Raymond Mao,
Jaehoon Chung, Bhimeswararao Matsa, Tanmay Kathpalia,
Kaustabh Chakraborty, Han Xu, Yanir Levin, Christoph Stoidner,
Balsundar Ponnusamy, Daniel Palmer, Anshul Dalal,
Bastien Curutchet, Angelo Dureghello, Johan Jonker, Sam Protsenko,
Guodong Xu, Yao Zi, Rick Chen, Leo, Eric Chung
Add document on how to flash images into eMMC of K1 SoC based boards.
Signed-off-by: Eric Chung <eric.chung@riscstar.com>
---
v8:
- Remove SD Card part.
v3:
- Add document on how to flash images into SD card.
---
board/spacemit/k1/MAINTAINERS | 2 +-
doc/board/spacemit/index.rst | 1 +
doc/board/spacemit/k1-mmc.rst | 167 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 169 insertions(+), 1 deletion(-)
diff --git a/board/spacemit/k1/MAINTAINERS b/board/spacemit/k1/MAINTAINERS
index 4b2bc4ecfc10..e12288a206e0 100644
--- a/board/spacemit/k1/MAINTAINERS
+++ b/board/spacemit/k1/MAINTAINERS
@@ -6,7 +6,7 @@ S: Maintained
F: arch/riscv/dts/k1-*-u-boot.dtsi
F: board/spacemit/k1/
F: configs/spacemit_k1_defconfig
-F: doc/board/spacemit/bananapi-f3.rst
+F: doc/board/spacemit/
F: drivers/gpio/spacemit_gpio.c
F: drivers/i2c/k1_i2c.c
F: drivers/mmc/spacemit_sdhci.c
diff --git a/doc/board/spacemit/index.rst b/doc/board/spacemit/index.rst
index a5e35ee12ab6..71854e5735bd 100644
--- a/doc/board/spacemit/index.rst
+++ b/doc/board/spacemit/index.rst
@@ -6,5 +6,6 @@ SpacemiT
:maxdepth: 1
bananapi-f3
+ k1-mmc
k1-spl
diff --git a/doc/board/spacemit/k1-mmc.rst b/doc/board/spacemit/k1-mmc.rst
new file mode 100644
index 000000000000..f30f211342ff
--- /dev/null
+++ b/doc/board/spacemit/k1-mmc.rst
@@ -0,0 +1,167 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+SpacemiT K1 eMMC Guide
+======================
+
+This guide covers the method for booting and flashing U-Boot on SpacemiT K1
+based boards via USB to eMMC.
+
+Tested boards: Banana Pi BPI-F3, MusePi Pro.
+
+
+Chapter 1: eMMC Flash (U-Boot via USB Fastboot)
+===============================================
+
+SpacemiT K1 U-Boot Flash Guide
+==============================
+
+This guide explains how to flash U-Boot on SpacemiT K1 based boards. It covers
+flashing images via USB fastboot.
+
+.. note::
+
+ This procedure flashes images to eMMC over USB fastboot. The fastboot
+ function is not enabled in our SPL yet, so the download stage runs the
+ SpacemiT released SPL; our built FSBL.bin and fit.itb are the images
+ written to eMMC and used on the next normal boot.
+
+Prerequisites
+~~~~~~~~~~~~~
+
+- A SpacemiT K1 board with USB Type-C and UART access
+- USB-to-UART adapter (3.3V TTL)
+- ``minicom`` or equivalent serial terminal, configured at 115200 8N1
+- ``fastboot`` and ``flashserver`` tool on the host
+
+Hardware Setup
+~~~~~~~~~~~~~~
+
+Refer to k1-spl.rst.
+
+Flash images on eMMC
+~~~~~~~~~~~~~~~~~~~~
+
+**1. Obtain the release images**
+
+Get the release package from Spacemit website. It contains SPL image, and so on.
+
+https://archive.spacemit.com/image/k1/version/bianbu/v2.3.3/Bianbu-Minimal-K1-V2.3.3-20260128183217.zip
+
+Unzip images and store them into a directory.
+
+**2. Obtain flashserver tool**
+
+Get ``flashserver`` from Spacemit website.
+
+.. code-block:: bash
+
+ $wget https://cdn-resource.spacemit.com/file/flash/flashserver
+ $chmod +x flashserver
+ $mv flashserver {flash image path}/
+
+**3. Copy built SPL and U-Boot images**
+
+Build U-Boot as mentioned in k1-spl.rst. Create a new directory to save.
+The official u-boot.itb is used to download images. So the built U-Boot should
+not replace the official one.
+
+.. code-block:: bash
+
+ $mkdir {flash image path}/build
+ $cd {flash image path}
+ $ln -sf {path to FSBL.bin} ./build/
+ $ln -sf {path to u-boot.itb} ./build/fit.itb
+
+``{path to FSBL.bin}`` is the signed FSBL produced by ``fsbl.sh`` in
+k1-spl.rst, e.g. ``~/uboot-2022.10/spl_bin/FSBL.bin``.
+``{path to u-boot.itb}`` is the U-Boot build output, e.g.
+``~/u-boot/u-boot.itb``.
+
+**4. Update configuration files**
+
+The ``partition_2M.json`` and ``partition_universal.json`` files come from
+the release package. Patch the ``fsbl`` and ``uboot`` entries to point at
+the images staged under ``build/`` (pick the layout that matches your eMMC):
+
+.. code-block:: diff
+
+ diff -puNr bianbu-25/partition_2M.json clean/partition_2M.json
+ --- bianbu-25/partition_2M.json 2026-03-02 11:55:58.631116807 +0800
+ +++ clean/partition_2M.json 2026-05-20 11:25:21.683801401 +0800
+ @@ -13,7 +13,7 @@
+ "name": "fsbl",
+ "offset": "128K",
+ "size": "256K",
+ - "image": "factory/FSBL.bin"
+ + "image": "build/FSBL.bin"
+ },
+ {
+ "name": "env",
+ @@ -31,7 +31,7 @@
+ "name": "uboot",
+ "offset": "640K",
+ "size": "-",
+ - "image": "u-boot.itb"
+ + "image": "build/fit.itb"
+ }
+ ]
+ }
+ diff -puNr bianbu-25/partition_universal.json clean/partition_universal.json
+ --- bianbu-25/partition_universal.json 2026-03-02 11:55:58.642116862 +0800
+ +++ clean/partition_universal.json 2026-05-20 11:26:23.932581853 +0800
+ @@ -14,7 +14,7 @@
+ "name": "fsbl",
+ "offset": "128K",
+ "size": "256K",
+ - "image": "factory/FSBL.bin"
+ + "image": "build/FSBL.bin"
+ },
+ {
+ "name": "env",
+ @@ -32,7 +32,7 @@
+ "name": "uboot",
+ "offset": "2M",
+ "size": "2M",
+ - "image": "u-boot.itb"
+ + "image": "build/fit.itb"
+ },
+ {
+ "name": "bootfs",
+
+Deploying via USB Fastboot
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+To enter BootROM fastboot mode:
+
+1. Power off the board by unplugging its power supply.
+2. **Press and hold** the FDL button (called "Boot Key" on some boards;
+ see the board layout above for the BPI-F3).
+3. While holding the button, use a USB cable to connect the OTG port to
+ your host. This cable is also used by fastboot to upload the firmware.
+4. Release the button.
+
+On the host, ``fastboot devices`` should list the board::
+
+ dfu-device DFU download
+
+The serial console shows the BootROM's USB download handler trace,
+including a line like::
+
+ usb2d_initialize : enter
+
+This indicates the board is ready to accept an image via USB.
+
+.. tip::
+
+ If you are worried about insufficient USB power, you can first plug
+ in the power, then release the button, and then plug in the USB
+ cable.
+
+On the host:
+
+.. code-block:: console
+
+ $sudo ./flashserver
+
+When ``flashserver`` is running, it lists the detected fastboot devices.
+Enter the corresponding number to select one.
--
2.51.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v8 10/11] config: k1: enable ENV support for eMMC
2026-08-01 16:40 [PATCH v8 00/11] spacemit mmc driver Eric Chung
` (8 preceding siblings ...)
2026-08-01 16:40 ` [PATCH v8 09/11] doc: spacemit: flash on K1 SoC based boards Eric Chung
@ 2026-08-01 16:40 ` Eric Chung
2026-08-01 16:40 ` [PATCH v8 11/11] spacemit: k1: fix product name detection and DTB matching in SPL Eric Chung
10 siblings, 0 replies; 13+ messages in thread
From: Eric Chung @ 2026-08-01 16:40 UTC (permalink / raw)
To: u-boot-spacemit, u-boot, u-boot
Cc: Tom Rini, Tim Ouyang, Leo Liang, Peng Fan, Huan Zhou, Raymond Mao,
Jaehoon Chung, Bhimeswararao Matsa, Tanmay Kathpalia,
Kaustabh Chakraborty, Han Xu, Yanir Levin, Christoph Stoidner,
Balsundar Ponnusamy, Daniel Palmer, Anshul Dalal,
Bastien Curutchet, Angelo Dureghello, Johan Jonker, Sam Protsenko,
Guodong Xu, Yao Zi, Rick Chen, Leo, Eric Chung
Enable environment variable support on the eMMC storage device for
both SPL and U-Boot stages.
Signed-off-by: Eric Chung <eric.chung@riscstar.com>
---
configs/spacemit_k1_defconfig | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/configs/spacemit_k1_defconfig b/configs/spacemit_k1_defconfig
index c0ee3a29f233..7caba18ddcdf 100644
--- a/configs/spacemit_k1_defconfig
+++ b/configs/spacemit_k1_defconfig
@@ -14,7 +14,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x400
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_ADDR=0xc00000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x100000
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x400000
CONFIG_SYS_BOOTM_LEN=0xa000000
CONFIG_SYS_LOAD_ADDR=0x200000
CONFIG_SPL_SIZE_LIMIT=0x31000
@@ -48,6 +48,10 @@ CONFIG_CMD_TLV_EEPROM=y
CONFIG_SPL_CMD_TLV_EEPROM=y
CONFIG_OF_UPSTREAM=y
CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x60000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
@@ -111,5 +115,6 @@ CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_SPI_FLASH_TINY=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
--
2.51.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v8 11/11] spacemit: k1: fix product name detection and DTB matching in SPL
2026-08-01 16:40 [PATCH v8 00/11] spacemit mmc driver Eric Chung
` (9 preceding siblings ...)
2026-08-01 16:40 ` [PATCH v8 10/11] config: k1: enable ENV support for eMMC Eric Chung
@ 2026-08-01 16:40 ` Eric Chung
10 siblings, 0 replies; 13+ messages in thread
From: Eric Chung @ 2026-08-01 16:40 UTC (permalink / raw)
To: u-boot-spacemit, u-boot, u-boot
Cc: Tom Rini, Tim Ouyang, Leo Liang, Peng Fan, Huan Zhou, Raymond Mao,
Jaehoon Chung, Bhimeswararao Matsa, Tanmay Kathpalia,
Kaustabh Chakraborty, Han Xu, Yanir Levin, Christoph Stoidner,
Balsundar Ponnusamy, Daniel Palmer, Anshul Dalal,
Bastien Curutchet, Angelo Dureghello, Johan Jonker, Sam Protsenko,
Guodong Xu, Yao Zi, Rick Chen, Leo, Eric Chung
Use a table to handle DTB matching.
Signed-off-by: Eric Chung <eric.chung@riscstar.com>
---
v7:
- Abandon to load product name from ENV.
v6:
- Rebased onto latest upstream. Cleaned up board_fit_config_name_match()
to maintain consistentcy with v5.
---
board/spacemit/k1/spl.c | 50 +++++++++++++++++++++++++++++++------------------
1 file changed, 32 insertions(+), 18 deletions(-)
diff --git a/board/spacemit/k1/spl.c b/board/spacemit/k1/spl.c
index 613e8c4cf02a..9f200f2fc184 100644
--- a/board/spacemit/k1/spl.c
+++ b/board/spacemit/k1/spl.c
@@ -97,6 +97,15 @@ static void i2c_early_init(void)
}
}
+static const struct {
+ const char *eeprom_name;
+ const char *fit_name;
+} k1_board_map[] = {
+ { "k1-x_MUSE-Pi-Pro", "spacemit/k1-musepi-pro" },
+ { "k1-x_deb1", "spacemit/k1-bananapi-f3" },
+ { "k1-x_milkv-jupiter", "spacemit/k1-milkv-jupiter" },
+};
+
int read_product_name(char *name, int size)
{
u8 eeprom_data[TLV_TOTAL_LEN_MAX], *p;
@@ -130,6 +139,27 @@ int read_product_name(char *name, int size)
return -ENOENT;
}
+static void fixup_product_name(void)
+{
+ char fdt_name[I2C_BUF_SIZE];
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(k1_board_map); i++) {
+ memset(fdt_name, 0, I2C_BUF_SIZE);
+ if (!strncmp(product_name, k1_board_map[i].eeprom_name,
+ strlen(k1_board_map[i].eeprom_name))) {
+ snprintf(fdt_name, I2C_BUF_SIZE, "%s",
+ k1_board_map[i].fit_name);
+ break;
+ }
+ }
+ if (fdt_name[0] == '\0') {
+ /* set default board name */
+ sprintf(fdt_name, CONFIG_DEFAULT_DEVICE_TREE);
+ }
+ memcpy(product_name, fdt_name, I2C_BUF_SIZE);
+}
+
static void clk_early_init(void)
{
struct udevice *dev;
@@ -369,6 +399,7 @@ void board_init_f(ulong dummy)
log_info("Fail to detect board:%d\n", ret);
else
log_info("Get board name:%s\n", product_name);
+ fixup_product_name();
pmic_init();
ddr_early_init();
@@ -432,24 +463,7 @@ void spl_board_init(void)
int board_fit_config_name_match(const char *name)
{
- char fdt_name[I2C_BUF_SIZE];
- int i;
-
- memset(fdt_name, 0, I2C_BUF_SIZE);
- if (!strncmp(product_name, "k1-x_", 5)) {
- snprintf(fdt_name, I2C_BUF_SIZE, "%s-%s", "k1",
- &product_name[5]);
- }
- if (fdt_name[0] == '\0') {
- /* set default board name */
- sprintf(fdt_name, "k1-musepi-pro");
- }
- for (i = 0; i < I2C_BUF_SIZE; i++) {
- if (fdt_name[i] == '\0')
- break;
- fdt_name[i] = tolower(fdt_name[i]);
- }
- if (!strcmp(name, fdt_name))
+ if (!strcmp(name, product_name))
return 0;
return -ENOENT;
}
--
2.51.0
^ permalink raw reply related [flat|nested] 13+ messages in thread