* [PATCH 0/2] Hi there,
@ 2026-08-17 10:27 ` Aiden Isik
0 siblings, 0 replies; 12+ messages in thread
From: Aiden Isik @ 2026-08-17 10:27 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Peter Griffin,
Alim Akhtar
Cc: Krzysztof Kozlowski, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel, Aiden Isik
This patchset adds initial support for the Exynos 5515 SoC, along with
support for the Samsung Galaxy Watch FE (codenamed lucky7), which uses
this SoC.
Support for the following is added:
- Bootloader framebuffer
- Both CPU cores
- Memory
- Generic timer
- Watchdog timer
- CMU_TOP, CMU_FSYS, CMU_PERI clock management units
- ChipID
Only the lowest 490MiB and highest 512MiB of memory are used for now.
The 488MiB between the addresses of 0x9ea00000 and 0xbe680000 is excluded
from the memory node due to a bug where if the kernel even knows about
the existence of this memory, one or both cores will lock up and cause
an RCU stall. There are several regions between this addresses which will
lock up the core, so the issue is difficult to bisect, and attempting to
dump memory information on panic will just lock up the second core.
Currently, these device trees support booting the device to an initramfs.
I am getting checkpatch warnings on this patchset advising to check
MAINTAINERS as new files were added, but I assume they can be ignored
as I am not a maintainer.
This patchset depends on [1], [2], and [3], for drivers and device tree
bindings.
[1] https://lore.kernel.org/all/20260817-for-next-lucky7-chipid-v1-0-eb2908705c0d@member.fsf.org/
[2] https://lore.kernel.org/all/20260817-for-next-lucky7-clock-v1-0-032e4b229c76@member.fsf.org/
[3] https://lore.kernel.org/all/20260817-for-next-lucky7-watchdog-v1-0-a14370e20b92@member.fsf.org/
Kind regards,
- Aiden Isik
Signed-off-by: Aiden Isik <aidenisik+git@member.fsf.org>
---
Aiden Isik (2):
arm64: dts: exynos: Add initial support for Exynos5515 SoC
arm64: dts: exynos: Add initial support for Samsung Galaxy Watch FE
arch/arm64/boot/dts/exynos/exynos5515-lucky7.dts | 106 +++++++++++++
arch/arm64/boot/dts/exynos/exynos5515.dtsi | 186 +++++++++++++++++++++++
2 files changed, 292 insertions(+)
---
base-commit: add58997023d8fbf429745f8a2e25289bbe22885
change-id: 20260815-for-next-lucky7-e5bf3950bdbe
Best regards,
--
Aiden Isik <aidenisik@member.fsf.org>
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH 1/2] arm64: dts: exynos: Add initial support for Exynos5515 SoC
2026-08-17 10:27 ` Aiden Isik
@ 2026-08-17 10:27 ` Aiden Isik
-1 siblings, 0 replies; 12+ messages in thread
From: Aiden Isik via B4 Relay @ 2026-08-17 10:27 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Peter Griffin,
Alim Akhtar
Cc: Krzysztof Kozlowski, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel, Aiden Isik
From: Aiden Isik <aidenisik@member.fsf.org>
The Exynos5515 is an ARMv8 wearable SoC, used in the following devices:
- Samsung Galaxy Watch 4 (SM-R860/SM-R865/SM-R870/SM-R875)
- Samsung Galaxy Watch 4 Classic (SM-R880/SM-R885/SM-R890/SM-R895)
- Samsung Galaxy Watch FE (SM-R861/SM-R866)
- Samsung Galaxy Watch 5 (SM-R900/SM-R905/SM-R910/SM-R915)
- Samsung Galaxy Watch 5 Pro (SM-R920/SM-R925)
- Samsung Galaxy Watch 6 (SM-R930/SM-R935/SM-R940/SM-R945)
- Samsung Galaxy Watch 6 Classic (SM-R950/SM-R955/SM-R960/SM-R965)
Add the following support for this SoC:
- Both Cortex-A55 cores
- ChipID
- Generic timer
- Watchdog timer
- CMU_TOP, CMU_PERI, and CMU_FSYS clock management units
The devices using this SoC suffer from the same issue as many other
Samsung devices, where the stock bootloader does not configure CNTFRQ_EL0.
To mitigate this, the correct frequency is hardcoded in the timer node.
Signed-off-by: Aiden Isik <aidenisik+git@member.fsf.org>
---
arch/arm64/boot/dts/exynos/exynos5515.dtsi | 186 +++++++++++++++++++++++++++++
1 file changed, 186 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5515.dtsi b/arch/arm64/boot/dts/exynos/exynos5515.dtsi
new file mode 100644
index 000000000000..5584c1a3aaf4
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5515.dtsi
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Samsung Exynos 5515 SoC device tree source
+ *
+ * Copyright (c) 2026 Aiden Isik <aidenisik+git@member.fsf.org>
+ */
+
+#include <dt-bindings/clock/samsung,exynos5515-cmu.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "samsung,exynos5515";
+ #address-cells = <2>;
+ interrupt-parent = <&gic>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a55";
+ reg = <0x0>;
+ device_type = "cpu";
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ device_type = "cpu";
+ enable-method = "psci";
+ };
+ };
+
+ oscclk: osc-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "oscclk";
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupt-affinity = <&cpu0>,
+ <&cpu1>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ cpu_off = <0x84000002>;
+ cpu_on = <0xc4000003>;
+ cpu_suspend = <0xc4000001>;
+ method = "smc";
+ };
+
+ soc: soc@0 {
+ compatible = "simple-bus";
+ ranges = <0x0 0x0 0x0 0x20000000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chipid@10000000 {
+ compatible = "samsung,exynos5515-chipid",
+ "samsung,exynos850-chipid";
+ reg = <0x10000000 0x100>;
+ };
+
+ sysreg_peri: syscon@10020000 {
+ compatible = "samsung,exynos5515-peri-sysreg", "syscon";
+ reg = <0x10020000 0x10000>;
+ };
+
+ cmu_peri: clock-controller@10030000 {
+ compatible = "samsung,exynos5515-cmu-peri";
+ reg = <0x10030000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&oscclk>,
+ <&cmu_top CLK_DOUT_CMU_PERI_BUS>,
+ <&cmu_top CLK_DOUT_CMU_PERI_IP>,
+ <&cmu_top CLK_DOUT_CMU_PERI_UART>;
+ clock-names = "oscclk",
+ "bus",
+ "ip",
+ "uart";
+ samsung,sysreg = <&sysreg_peri>;
+ };
+
+ watchdog: watchdog@10050000 {
+ compatible = "samsung,exynos5515-wdt";
+ reg = <0x10050000 0x100>;
+ clocks = <&cmu_peri CLK_GOUT_PERI_WDT0_PCLK>,
+ <&oscclk>;
+ clock-names = "watchdog",
+ "watchdog_src";
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+ samsung,syscon-phandle = <&pmu_system_controller>;
+
+ status = "disabled";
+ };
+
+ cmu_fsys: clock-controller@10400000 {
+ compatible = "samsung,exynos5515-cmu-fsys";
+ reg = <0x10400000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&oscclk>,
+ <&cmu_top CLK_DOUT_CMU_FSYS_BUS>,
+ <&cmu_top CLK_DOUT_CMU_FSYS_MMC_CARD>,
+ <&cmu_top CLK_DOUT_CMU_FSYS_MMC_EMBD>,
+ <&cmu_top CLK_DOUT_CMU_FSYS_USB20DRD>;
+ clock-names = "oscclk",
+ "bus",
+ "mmc_card",
+ "mmc_embd",
+ "usb20drd";
+ samsung,sysreg = <&sysreg_fsys>;
+ };
+
+ sysreg_fsys: syscon@10420000 {
+ compatible = "samsung,exynos5515-fsys-sysreg", "syscon";
+ reg = <0x10420000 0x10000>;
+ };
+
+ pmu_system_controller: system-controller@12860000 {
+ compatible = "samsung,exynos5515-pmu",
+ "samsung,exynos7-pmu",
+ "syscon";
+ reg = <0x12860000 0x10000>;
+ };
+
+ cmu_top: clock-controller@15410000 {
+ compatible = "samsung,exynos5515-cmu-top";
+ reg = <0x15410000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&oscclk>;
+ clock-names = "oscclk";
+ samsung,sysreg = <&sysreg_top>;
+ };
+
+ sysreg_top: syscon@15430000 {
+ compatible = "samsung,exynos5515-top-sysreg", "syscon";
+ reg = <0x15430000 0x10000>;
+ };
+
+ gic: interrupt-controller@15600000 {
+ compatible = "arm,gic-400";
+ reg = <0x15601000 0x1000>,
+ <0x15602000 0x1000>,
+ <0x15604000 0x2000>,
+ <0x15606000 0x2000>;
+ #address-cells = <0>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ /*
+ * Non-updatable, broken stock Samsung bootloader does not
+ * configure CNTFRQ_EL0
+ */
+ clock-frequency = <26000000>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
+
+#include "arm/samsung/exynos-syscon-restart.dtsi"
--
2.54.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 1/2] arm64: dts: exynos: Add initial support for Exynos5515 SoC
@ 2026-08-17 10:27 ` Aiden Isik
0 siblings, 0 replies; 12+ messages in thread
From: Aiden Isik @ 2026-08-17 10:27 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Peter Griffin,
Alim Akhtar
Cc: Krzysztof Kozlowski, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel, Aiden Isik
The Exynos5515 is an ARMv8 wearable SoC, used in the following devices:
- Samsung Galaxy Watch 4 (SM-R860/SM-R865/SM-R870/SM-R875)
- Samsung Galaxy Watch 4 Classic (SM-R880/SM-R885/SM-R890/SM-R895)
- Samsung Galaxy Watch FE (SM-R861/SM-R866)
- Samsung Galaxy Watch 5 (SM-R900/SM-R905/SM-R910/SM-R915)
- Samsung Galaxy Watch 5 Pro (SM-R920/SM-R925)
- Samsung Galaxy Watch 6 (SM-R930/SM-R935/SM-R940/SM-R945)
- Samsung Galaxy Watch 6 Classic (SM-R950/SM-R955/SM-R960/SM-R965)
Add the following support for this SoC:
- Both Cortex-A55 cores
- ChipID
- Generic timer
- Watchdog timer
- CMU_TOP, CMU_PERI, and CMU_FSYS clock management units
The devices using this SoC suffer from the same issue as many other
Samsung devices, where the stock bootloader does not configure CNTFRQ_EL0.
To mitigate this, the correct frequency is hardcoded in the timer node.
Signed-off-by: Aiden Isik <aidenisik+git@member.fsf.org>
---
arch/arm64/boot/dts/exynos/exynos5515.dtsi | 186 +++++++++++++++++++++++++++++
1 file changed, 186 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5515.dtsi b/arch/arm64/boot/dts/exynos/exynos5515.dtsi
new file mode 100644
index 000000000000..5584c1a3aaf4
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5515.dtsi
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Samsung Exynos 5515 SoC device tree source
+ *
+ * Copyright (c) 2026 Aiden Isik <aidenisik+git@member.fsf.org>
+ */
+
+#include <dt-bindings/clock/samsung,exynos5515-cmu.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "samsung,exynos5515";
+ #address-cells = <2>;
+ interrupt-parent = <&gic>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a55";
+ reg = <0x0>;
+ device_type = "cpu";
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ device_type = "cpu";
+ enable-method = "psci";
+ };
+ };
+
+ oscclk: osc-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "oscclk";
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupt-affinity = <&cpu0>,
+ <&cpu1>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ cpu_off = <0x84000002>;
+ cpu_on = <0xc4000003>;
+ cpu_suspend = <0xc4000001>;
+ method = "smc";
+ };
+
+ soc: soc@0 {
+ compatible = "simple-bus";
+ ranges = <0x0 0x0 0x0 0x20000000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chipid@10000000 {
+ compatible = "samsung,exynos5515-chipid",
+ "samsung,exynos850-chipid";
+ reg = <0x10000000 0x100>;
+ };
+
+ sysreg_peri: syscon@10020000 {
+ compatible = "samsung,exynos5515-peri-sysreg", "syscon";
+ reg = <0x10020000 0x10000>;
+ };
+
+ cmu_peri: clock-controller@10030000 {
+ compatible = "samsung,exynos5515-cmu-peri";
+ reg = <0x10030000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&oscclk>,
+ <&cmu_top CLK_DOUT_CMU_PERI_BUS>,
+ <&cmu_top CLK_DOUT_CMU_PERI_IP>,
+ <&cmu_top CLK_DOUT_CMU_PERI_UART>;
+ clock-names = "oscclk",
+ "bus",
+ "ip",
+ "uart";
+ samsung,sysreg = <&sysreg_peri>;
+ };
+
+ watchdog: watchdog@10050000 {
+ compatible = "samsung,exynos5515-wdt";
+ reg = <0x10050000 0x100>;
+ clocks = <&cmu_peri CLK_GOUT_PERI_WDT0_PCLK>,
+ <&oscclk>;
+ clock-names = "watchdog",
+ "watchdog_src";
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+ samsung,syscon-phandle = <&pmu_system_controller>;
+
+ status = "disabled";
+ };
+
+ cmu_fsys: clock-controller@10400000 {
+ compatible = "samsung,exynos5515-cmu-fsys";
+ reg = <0x10400000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&oscclk>,
+ <&cmu_top CLK_DOUT_CMU_FSYS_BUS>,
+ <&cmu_top CLK_DOUT_CMU_FSYS_MMC_CARD>,
+ <&cmu_top CLK_DOUT_CMU_FSYS_MMC_EMBD>,
+ <&cmu_top CLK_DOUT_CMU_FSYS_USB20DRD>;
+ clock-names = "oscclk",
+ "bus",
+ "mmc_card",
+ "mmc_embd",
+ "usb20drd";
+ samsung,sysreg = <&sysreg_fsys>;
+ };
+
+ sysreg_fsys: syscon@10420000 {
+ compatible = "samsung,exynos5515-fsys-sysreg", "syscon";
+ reg = <0x10420000 0x10000>;
+ };
+
+ pmu_system_controller: system-controller@12860000 {
+ compatible = "samsung,exynos5515-pmu",
+ "samsung,exynos7-pmu",
+ "syscon";
+ reg = <0x12860000 0x10000>;
+ };
+
+ cmu_top: clock-controller@15410000 {
+ compatible = "samsung,exynos5515-cmu-top";
+ reg = <0x15410000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&oscclk>;
+ clock-names = "oscclk";
+ samsung,sysreg = <&sysreg_top>;
+ };
+
+ sysreg_top: syscon@15430000 {
+ compatible = "samsung,exynos5515-top-sysreg", "syscon";
+ reg = <0x15430000 0x10000>;
+ };
+
+ gic: interrupt-controller@15600000 {
+ compatible = "arm,gic-400";
+ reg = <0x15601000 0x1000>,
+ <0x15602000 0x1000>,
+ <0x15604000 0x2000>,
+ <0x15606000 0x2000>;
+ #address-cells = <0>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ /*
+ * Non-updatable, broken stock Samsung bootloader does not
+ * configure CNTFRQ_EL0
+ */
+ clock-frequency = <26000000>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
+
+#include "arm/samsung/exynos-syscon-restart.dtsi"
--
2.54.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 1/2] arm64: dts: exynos: Add initial support for Exynos5515 SoC
2026-08-17 10:27 ` Aiden Isik
(?)
@ 2026-08-17 10:38 ` sashiko-bot
2026-08-17 10:57 ` Aiden Isik
-1 siblings, 1 reply; 12+ messages in thread
From: sashiko-bot @ 2026-08-17 10:38 UTC (permalink / raw)
To: Aiden Isik; +Cc: devicetree, robh, conor+dt
Thank you for your contribution! Sashiko AI review found 5 potential issue(s) to consider:
- [Medium] The GIC-400 node lacks the VGIC maintenance interrupt property.
- [Medium] GIC CPU interface (GICC) memory region is incorrectly sized at 0x1000, which breaks VGIC support.
- [Low] Node unit-addresses for `cpu1` and `gic` do not match their `reg` properties.
- [Low] Redundant and deprecated custom function IDs are provided for PSCI 1.0.
- [Low] Missing dt-bindings clock header `samsung,exynos5515-cmu.h`.
--
--- Patch [1]: [PATCH 1/2] arm64: dts: exynos: Add initial support for Exynos5515 SoC ---
commit e8b991884f3a3fd45bff9e8dcdd76dcc3db06db9
Author: Aiden Isik <aidenisik@member.fsf.org>
arm64: dts: exynos: Add initial support for Exynos5515 SoC
The patch adds initial device tree support for the Exynos5515 SoC, used in
Samsung Galaxy Watch models. It adds CPUs, generic timer, watchdog, and
various clock management units.
> diff --git a/arch/arm64/boot/dts/exynos/exynos5515.dtsi b/arch/arm64/boot/dts/exynos/exynos5515.dtsi
> new file mode 100644
> index 0000000000000..5584c1a3aaf4f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos5515.dtsi
> @@ -0,0 +1,186 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Samsung Exynos 5515 SoC device tree source
> + *
> + * Copyright (c) 2026 Aiden Isik <aidenisik+git@member.fsf.org>
> + */
> +
> +#include <dt-bindings/clock/samsung,exynos5515-cmu.h>
[Severity: Low]
Is this header file missing? It appears it was not added in this patch or
earlier in the series, which will cause the device tree compilation to fail.
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
[ ... ]
> + cpu1: cpu@1 {
> + compatible = "arm,cortex-a55";
> + reg = <0x100>;
[Severity: Low]
Does the unit-address for cpu1 match the reg property? The device tree
specification requires the unit-address to match the first address in the
reg property, so should this be cpu@100?
> + device_type = "cpu";
> + enable-method = "psci";
> + };
> + };
[ ... ]
> + psci {
> + compatible = "arm,psci-1.0";
> + cpu_off = <0x84000002>;
> + cpu_on = <0xc4000003>;
> + cpu_suspend = <0xc4000001>;
[Severity: Low]
Are these custom function IDs necessary? Since compatible = "arm,psci-1.0"
is used, the kernel relies on standard architecturally mandated function
IDs, and explicitly defining cpu_off, cpu_on, and cpu_suspend will be ignored.
> + method = "smc";
> + };
[ ... ]
> + gic: interrupt-controller@15600000 {
[Severity: Low]
Does the unit-address for the gic node match its reg property? The first
address in the reg block is 0x15601000, so should the node be named
interrupt-controller@15601000?
[Severity: Medium]
Is the interrupts property for the VGIC maintenance interrupt missing from
the gic device node? Without it, KVM virtualization cannot properly handle
virtual interrupt maintenance.
> + compatible = "arm,gic-400";
> + reg = <0x15601000 0x1000>,
> + <0x15602000 0x1000>,
[Severity: Medium]
Is the GICC memory region incorrectly sized at 0x1000? KVM VGIC
initialization requires access to the GICC_DIR register at offset 0x1000 in
the GICC region for EOI mode 1, so should this size be at least 0x2000?
> + <0x15604000 0x2000>,
> + <0x15606000 0x2000>;
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260817-for-next-lucky7-v1-0-42ffb2b71ba2@member.fsf.org?part=1
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 1/2] arm64: dts: exynos: Add initial support for Exynos5515 SoC
2026-08-17 10:38 ` sashiko-bot
@ 2026-08-17 10:57 ` Aiden Isik
0 siblings, 0 replies; 12+ messages in thread
From: Aiden Isik @ 2026-08-17 10:57 UTC (permalink / raw)
To: sashiko-reviews; +Cc: Aiden Isik, devicetree, robh, conor+dt
> Thank you for your contribution! Sashiko AI review found 5 potential issue(s) to consider:
> - [Medium] The GIC-400 node lacks the VGIC maintenance interrupt property.
> - [Medium] GIC CPU interface (GICC) memory region is incorrectly sized at 0x1000, which breaks VGIC support.
> - [Low] Node unit-addresses for `cpu1` and `gic` do not match their `reg` properties.
> - [Low] Redundant and deprecated custom function IDs are provided for PSCI 1.0.
> - [Low] Missing dt-bindings clock header `samsung,exynos5515-cmu.h`.
> --
>
> --- Patch [1]: [PATCH 1/2] arm64: dts: exynos: Add initial support for Exynos5515 SoC ---
> commit e8b991884f3a3fd45bff9e8dcdd76dcc3db06db9
> Author: Aiden Isik <aidenisik@member.fsf.org>
>
> arm64: dts: exynos: Add initial support for Exynos5515 SoC
>
> The patch adds initial device tree support for the Exynos5515 SoC, used in
> Samsung Galaxy Watch models. It adds CPUs, generic timer, watchdog, and
> various clock management units.
>
> > diff --git a/arch/arm64/boot/dts/exynos/exynos5515.dtsi b/arch/arm64/boot/dts/exynos/exynos5515.dtsi
> > new file mode 100644
> > index 0000000000000..5584c1a3aaf4f
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/exynos/exynos5515.dtsi
> > @@ -0,0 +1,186 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later
> > +/*
> > + * Samsung Exynos 5515 SoC device tree source
> > + *
> > + * Copyright (c) 2026 Aiden Isik <aidenisik+git@member.fsf.org>
> > + */
> > +
> > +#include <dt-bindings/clock/samsung,exynos5515-cmu.h>
>
> [Severity: Low]
> Is this header file missing? It appears it was not added in this patch or
> earlier in the series, which will cause the device tree compilation to fail.
>
This header is added in the series introducing clock driver support.
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/ {
> [ ... ]
> > + cpu1: cpu@1 {
> > + compatible = "arm,cortex-a55";
> > + reg = <0x100>;
>
> [Severity: Low]
> Does the unit-address for cpu1 match the reg property? The device tree
> specification requires the unit-address to match the first address in the
> reg property, so should this be cpu@100?
I took this as a CPU index, but if any maintainers want it to be this way,
then I am happy to change it.
>
> > + device_type = "cpu";
> > + enable-method = "psci";
> > + };
> > + };
> [ ... ]
> > + psci {
> > + compatible = "arm,psci-1.0";
> > + cpu_off = <0x84000002>;
> > + cpu_on = <0xc4000003>;
> > + cpu_suspend = <0xc4000001>;
>
> [Severity: Low]
> Are these custom function IDs necessary? Since compatible = "arm,psci-1.0"
> is used, the kernel relies on standard architecturally mandated function
> IDs, and explicitly defining cpu_off, cpu_on, and cpu_suspend will be ignored.
This is how it is done downstream and in other mainline Exynos SoCs from
memory. Again, if a maintainer wants it changed I am happy to.
>
> > + method = "smc";
> > + };
> [ ... ]
> > + gic: interrupt-controller@15600000 {
>
> [Severity: Low]
> Does the unit-address for the gic node match its reg property? The first
> address in the reg block is 0x15601000, so should the node be named
> interrupt-controller@15601000?
Possibly, I will look into this.
>
> [Severity: Medium]
> Is the interrupts property for the VGIC maintenance interrupt missing from
> the gic device node? Without it, KVM virtualization cannot properly handle
> virtual interrupt maintenance.
>
> > + compatible = "arm,gic-400";
> > + reg = <0x15601000 0x1000>,
> > + <0x15602000 0x1000>,
>
Unsure.
> [Severity: Medium]
> Is the GICC memory region incorrectly sized at 0x1000? KVM VGIC
> initialization requires access to the GICC_DIR register at offset 0x1000 in
> the GICC region for EOI mode 1, so should this size be at least 0x2000?
>
> > + <0x15604000 0x2000>,
> > + <0x15606000 0x2000>;
>
Unsure.
> --
> Sashiko AI review · https://sashiko.dev/#/patchset/20260817-for-next-lucky7-v1-0-42ffb2b71ba2@member.fsf.org?part=1
>
Kind regards,
- Aiden Isik
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 2/2] arm64: dts: exynos: Add initial support for Samsung Galaxy Watch FE
2026-08-17 10:27 ` Aiden Isik
@ 2026-08-17 10:27 ` Aiden Isik
-1 siblings, 0 replies; 12+ messages in thread
From: Aiden Isik via B4 Relay @ 2026-08-17 10:27 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Peter Griffin,
Alim Akhtar
Cc: Krzysztof Kozlowski, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel, Aiden Isik
From: Aiden Isik <aidenisik@member.fsf.org>
The Samsung Galaxy Watch FE (SM-R861/SM-R866), codenamed lucky7, is a
smartwatch developed by Samsung and released in 2024. It has 1.5GiB RAM,
16GiB of eMMC storage, an Exynos5515 (W920) SoC, and a 396x396 display.
Support for the following is added by this device tree:
- Bootloader framebuffer
- Memory
Only the lowest 490MiB and highest 512MiB of memory are used for now.
The 488MiB between the addresses of 0x9ea00000 and 0xbe680000 is excluded
from the memory node due to a bug where if the kernel even knows about
the existence of this memory, one or both cores will lock up and cause
an RCU stall.
Signed-off-by: Aiden Isik <aidenisik+git@member.fsf.org>
---
arch/arm64/boot/dts/exynos/exynos5515-lucky7.dts | 106 +++++++++++++++++++++++
1 file changed, 106 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5515-lucky7.dts b/arch/arm64/boot/dts/exynos/exynos5515-lucky7.dts
new file mode 100644
index 000000000000..f91ea7e44cf8
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5515-lucky7.dts
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Samsung Galaxy Watch FE (lucky7/SM-R861/SM-R866) device tree source
+ *
+ * Copyright (c) 2026 Aiden Isik <aidenisik+git@member.fsf.org>
+ */
+
+/dts-v1/;
+#include "exynos5515.dtsi"
+
+/ {
+ compatible = "samsung,lucky7", "samsung,exynos5515";
+ chassis-type = "watch";
+ model = "Samsung Galaxy Watch FE (SM-R861/SM-R866)";
+
+ chosen {
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ framebuffer@9e0cf000 {
+ compatible = "simple-framebuffer";
+ reg = <0x0 0x9e0cf000 (396 * 396 * 4)>;
+ format = "a8r8g8b8";
+ height = <396>;
+ stride = <(396 * 4)>;
+ width = <396>;
+ };
+ };
+
+ memory@80000000 {
+ /*
+ * Use the lowest 490MiB and highest 512MiB of memory.
+ * The 488MiB between the addresses of 0x9ea00000 and
+ * 0xbe680000 is currently unused due to any memory accesses
+ * in several ranges between those addresses causing the core
+ * performing the accesses to stall.
+ */
+ reg = <0x0 0x80000000 0x1ea00000>,
+ /* Crashing memory at 0x9ea00000-0xbe680000 */
+ /* Memory hole at 0xbe680000-0xc0000000 */
+ <0x0 0xc0000000 0x20000000>;
+ device_type = "memory";
+ };
+
+ reserved-memory {
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ framebuffer@9e0cf000 {
+ reg = <0x0 0x9e0cf000 (396 * 396 * 4)>;
+ no-map;
+ };
+
+ misc-rmem {
+ /*
+ * Some of these regions belong to memory-mapped
+ * devices, and will be assigned to drivers as support
+ * is added.
+ *
+ * Other regions belong to the TrustZone firmware
+ * and should never be touched.
+ */
+ reg = <0x0 0x87000000 0x200000>,
+ <0x0 0x87fff000 0x1000>,
+ <0x0 0x8a000000 0x31000>,
+ <0x0 0x8d800000 0x180000>,
+ <0x0 0x8ffff000 0x33000>,
+ <0x0 0x90100000 0x200000>,
+ <0x0 0x98a00000 0x600000>,
+ <0x0 0x9a000000 0xc00000>,
+ <0x0 0x9b000000 0x400000>,
+ <0x0 0x9bd00000 0x208000>,
+ <0x0 0x9c000000 0x20000>,
+ <0x0 0xa0000000 0x10000>,
+ <0x0 0xa0010000 0x400000>,
+ <0x0 0xa0510000 0x1000>,
+ <0x0 0xa0900000 0x2000>,
+ <0x0 0xa0902000 0x1000>,
+ <0x0 0xa0910000 0x3c000>,
+ <0x0 0xb0000000 0x200000>,
+ <0x0 0xb1000000 0x200000>,
+ <0x0 0xbbfff000 0x1000000>,
+ <0x0 0xbcfff000 0x1000>,
+ <0x0 0xbd430000 0x1250000>,
+ <0x0 0xd0000000 0x5d00000>,
+ <0x0 0xdc444000 0x2bbc000>,
+ <0x0 0xdf005000 0x1000>,
+ <0x0 0xdf008000 0x1000>,
+ <0x0 0xdf009000 0x12000>,
+ <0x0 0xdf01b000 0x21000>,
+ <0x0 0xdf03c000 0x1000>,
+ <0x0 0xdf03d000 0xfc3000>;
+ no-map;
+ };
+ };
+};
+
+&oscclk {
+ clock-frequency = <26000000>;
+};
+
+&watchdog {
+ status = "okay";
+};
--
2.54.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 2/2] arm64: dts: exynos: Add initial support for Samsung Galaxy Watch FE
@ 2026-08-17 10:27 ` Aiden Isik
0 siblings, 0 replies; 12+ messages in thread
From: Aiden Isik @ 2026-08-17 10:27 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Peter Griffin,
Alim Akhtar
Cc: Krzysztof Kozlowski, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel, Aiden Isik
The Samsung Galaxy Watch FE (SM-R861/SM-R866), codenamed lucky7, is a
smartwatch developed by Samsung and released in 2024. It has 1.5GiB RAM,
16GiB of eMMC storage, an Exynos5515 (W920) SoC, and a 396x396 display.
Support for the following is added by this device tree:
- Bootloader framebuffer
- Memory
Only the lowest 490MiB and highest 512MiB of memory are used for now.
The 488MiB between the addresses of 0x9ea00000 and 0xbe680000 is excluded
from the memory node due to a bug where if the kernel even knows about
the existence of this memory, one or both cores will lock up and cause
an RCU stall.
Signed-off-by: Aiden Isik <aidenisik+git@member.fsf.org>
---
arch/arm64/boot/dts/exynos/exynos5515-lucky7.dts | 106 +++++++++++++++++++++++
1 file changed, 106 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5515-lucky7.dts b/arch/arm64/boot/dts/exynos/exynos5515-lucky7.dts
new file mode 100644
index 000000000000..f91ea7e44cf8
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5515-lucky7.dts
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Samsung Galaxy Watch FE (lucky7/SM-R861/SM-R866) device tree source
+ *
+ * Copyright (c) 2026 Aiden Isik <aidenisik+git@member.fsf.org>
+ */
+
+/dts-v1/;
+#include "exynos5515.dtsi"
+
+/ {
+ compatible = "samsung,lucky7", "samsung,exynos5515";
+ chassis-type = "watch";
+ model = "Samsung Galaxy Watch FE (SM-R861/SM-R866)";
+
+ chosen {
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ framebuffer@9e0cf000 {
+ compatible = "simple-framebuffer";
+ reg = <0x0 0x9e0cf000 (396 * 396 * 4)>;
+ format = "a8r8g8b8";
+ height = <396>;
+ stride = <(396 * 4)>;
+ width = <396>;
+ };
+ };
+
+ memory@80000000 {
+ /*
+ * Use the lowest 490MiB and highest 512MiB of memory.
+ * The 488MiB between the addresses of 0x9ea00000 and
+ * 0xbe680000 is currently unused due to any memory accesses
+ * in several ranges between those addresses causing the core
+ * performing the accesses to stall.
+ */
+ reg = <0x0 0x80000000 0x1ea00000>,
+ /* Crashing memory at 0x9ea00000-0xbe680000 */
+ /* Memory hole at 0xbe680000-0xc0000000 */
+ <0x0 0xc0000000 0x20000000>;
+ device_type = "memory";
+ };
+
+ reserved-memory {
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ framebuffer@9e0cf000 {
+ reg = <0x0 0x9e0cf000 (396 * 396 * 4)>;
+ no-map;
+ };
+
+ misc-rmem {
+ /*
+ * Some of these regions belong to memory-mapped
+ * devices, and will be assigned to drivers as support
+ * is added.
+ *
+ * Other regions belong to the TrustZone firmware
+ * and should never be touched.
+ */
+ reg = <0x0 0x87000000 0x200000>,
+ <0x0 0x87fff000 0x1000>,
+ <0x0 0x8a000000 0x31000>,
+ <0x0 0x8d800000 0x180000>,
+ <0x0 0x8ffff000 0x33000>,
+ <0x0 0x90100000 0x200000>,
+ <0x0 0x98a00000 0x600000>,
+ <0x0 0x9a000000 0xc00000>,
+ <0x0 0x9b000000 0x400000>,
+ <0x0 0x9bd00000 0x208000>,
+ <0x0 0x9c000000 0x20000>,
+ <0x0 0xa0000000 0x10000>,
+ <0x0 0xa0010000 0x400000>,
+ <0x0 0xa0510000 0x1000>,
+ <0x0 0xa0900000 0x2000>,
+ <0x0 0xa0902000 0x1000>,
+ <0x0 0xa0910000 0x3c000>,
+ <0x0 0xb0000000 0x200000>,
+ <0x0 0xb1000000 0x200000>,
+ <0x0 0xbbfff000 0x1000000>,
+ <0x0 0xbcfff000 0x1000>,
+ <0x0 0xbd430000 0x1250000>,
+ <0x0 0xd0000000 0x5d00000>,
+ <0x0 0xdc444000 0x2bbc000>,
+ <0x0 0xdf005000 0x1000>,
+ <0x0 0xdf008000 0x1000>,
+ <0x0 0xdf009000 0x12000>,
+ <0x0 0xdf01b000 0x21000>,
+ <0x0 0xdf03c000 0x1000>,
+ <0x0 0xdf03d000 0xfc3000>;
+ no-map;
+ };
+ };
+};
+
+&oscclk {
+ clock-frequency = <26000000>;
+};
+
+&watchdog {
+ status = "okay";
+};
--
2.54.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 2/2] arm64: dts: exynos: Add initial support for Samsung Galaxy Watch FE
2026-08-17 10:27 ` Aiden Isik
(?)
@ 2026-08-17 10:35 ` sashiko-bot
2026-08-17 11:04 ` Aiden Isik
-1 siblings, 1 reply; 12+ messages in thread
From: sashiko-bot @ 2026-08-17 10:35 UTC (permalink / raw)
To: Aiden Isik; +Cc: robh, conor+dt, devicetree
Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [High] Unaligned `no-map` simple-framebuffer region causes memory attribute aliasing.
- [Medium] Invalid usage of `reserved-memory` for memory-mapped devices and regions outside system RAM.
- [Low] Missing unit address in the `misc-rmem` device tree node.
- [Low] Mathematical error in memory calculation in commit message and comments.
--
--- Patch [2]: [PATCH 2/2] arm64: dts: exynos: Add initial support for Samsung Galaxy Watch FE ---
commit 6f30a8a96fda7068a12749f38925083c1838f92d
Author: Aiden Isik <aidenisik@member.fsf.org>
arm64: dts: exynos: Add initial support for Samsung Galaxy Watch FE
This commit adds initial device tree support for the Samsung Galaxy Watch FE,
including bootloader framebuffer and memory definitions.
> Only the lowest 490MiB and highest 512MiB of memory are used for now.
> The 488MiB between the addresses of 0x9ea00000 and 0xbe680000 is excluded
[Severity: Low]
This isn't a bug, but the math in the commit message seems slightly off.
0xbe680000 - 0x9ea00000 is 0x1fc80000, which is 508.5 MiB, not 488 MiB.
> diff --git a/arch/arm64/boot/dts/exynos/exynos5515-lucky7.dts b/arch/arm64/boot/dts/exynos/exynos5515-lucky7.dts
> index 0000000000000..f91ea7e44cf86
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos5515-lucky7.dts
> @@ -0,0 +1,106 @@
[ ... ]
> + memory@80000000 {
> + /*
> + * Use the lowest 490MiB and highest 512MiB of memory.
> + * The 488MiB between the addresses of 0x9ea00000 and
[Severity: Low]
This isn't a bug, but similarly to the commit message, the calculated memory
size here is 508.5 MiB, not 488 MiB.
> + * 0xbe680000 is currently unused due to any memory accesses
> + * in several ranges between those addresses causing the core
> + * performing the accesses to stall.
> + */
> + reg = <0x0 0x80000000 0x1ea00000>,
[ ... ]
> + reserved-memory {
> + ranges;
> + #address-cells = <2>;
> + #size-cells = <1>;
> +
> + framebuffer@9e0cf000 {
> + reg = <0x0 0x9e0cf000 (396 * 396 * 4)>;
> + no-map;
> + };
[Severity: High]
Does this unaligned size combined with no-map cause memory attribute aliasing
on arm64?
The region has an unaligned size of 0x99240 (627264 bytes). The no-map
property drops this exact byte range from the kernel's linear map, leaving the
remainder of the page (0x9e168240-0x9e169000) to be mapped as Normal Cacheable
memory.
When the simple-framebuffer driver calls ioremap_wc(), it maps the entire page
at 0x9e168000 as Write-Combine (Normal Non-Cacheable), creating an attribute
alias.
> +
> + misc-rmem {
> + /*
> + * Some of these regions belong to memory-mapped
> + * devices, and will be assigned to drivers as support
> + * is added.
> + *
> + * Other regions belong to the TrustZone firmware
> + * and should never be touched.
> + */
> + reg = <0x0 0x87000000 0x200000>,
[Severity: Medium]
Is it valid to use reserved-memory for memory-mapped devices and regions
outside system RAM?
The Devicetree specification dictates that reserved-memory regions MUST be
contained within a defined /memory node. The misc-rmem node includes
addresses (e.g., 0xa0000000, 0xb0000000) that fall within the
0x9ea00000-0xc0000000 range explicitly omitted from the /memory node.
Additionally, since these are MMIO regions, shouldn't they be described as
device nodes on a bus rather than reserved RAM?
[Severity: Low]
This isn't a bug, but this node is missing the unit address @87000000
to match the first reg entry, which will generate a unit_address_vs_reg dtc
compiler warning.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260817-for-next-lucky7-v1-0-42ffb2b71ba2@member.fsf.org?part=2
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 2/2] arm64: dts: exynos: Add initial support for Samsung Galaxy Watch FE
2026-08-17 10:35 ` sashiko-bot
@ 2026-08-17 11:04 ` Aiden Isik
0 siblings, 0 replies; 12+ messages in thread
From: Aiden Isik @ 2026-08-17 11:04 UTC (permalink / raw)
To: sashiko-reviews; +Cc: Aiden Isik, robh, conor+dt, devicetree
> Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
> - [High] Unaligned `no-map` simple-framebuffer region causes memory attribute aliasing.
> - [Medium] Invalid usage of `reserved-memory` for memory-mapped devices and regions outside system RAM.
> - [Low] Missing unit address in the `misc-rmem` device tree node.
> - [Low] Mathematical error in memory calculation in commit message and comments.
> --
>
> --- Patch [2]: [PATCH 2/2] arm64: dts: exynos: Add initial support for Samsung Galaxy Watch FE ---
> commit 6f30a8a96fda7068a12749f38925083c1838f92d
> Author: Aiden Isik <aidenisik@member.fsf.org>
>
> arm64: dts: exynos: Add initial support for Samsung Galaxy Watch FE
>
> This commit adds initial device tree support for the Samsung Galaxy Watch FE,
> including bootloader framebuffer and memory definitions.
>
> > Only the lowest 490MiB and highest 512MiB of memory are used for now.
> > The 488MiB between the addresses of 0x9ea00000 and 0xbe680000 is excluded
>
> [Severity: Low]
> This isn't a bug, but the math in the commit message seems slightly off.
>
> 0xbe680000 - 0x9ea00000 is 0x1fc80000, which is 508.5 MiB, not 488 MiB.
Will fix in v2.
>
> > diff --git a/arch/arm64/boot/dts/exynos/exynos5515-lucky7.dts b/arch/arm64/boot/dts/exynos/exynos5515-lucky7.dts
> > index 0000000000000..f91ea7e44cf86
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/exynos/exynos5515-lucky7.dts
> > @@ -0,0 +1,106 @@
> [ ... ]
> > + memory@80000000 {
> > + /*
> > + * Use the lowest 490MiB and highest 512MiB of memory.
> > + * The 488MiB between the addresses of 0x9ea00000 and
>
> [Severity: Low]
> This isn't a bug, but similarly to the commit message, the calculated memory
> size here is 508.5 MiB, not 488 MiB.
Will fix in v2.
>
> > + * 0xbe680000 is currently unused due to any memory accesses
> > + * in several ranges between those addresses causing the core
> > + * performing the accesses to stall.
> > + */
> > + reg = <0x0 0x80000000 0x1ea00000>,
> [ ... ]
> > + reserved-memory {
> > + ranges;
> > + #address-cells = <2>;
> > + #size-cells = <1>;
> > +
> > + framebuffer@9e0cf000 {
> > + reg = <0x0 0x9e0cf000 (396 * 396 * 4)>;
> > + no-map;
> > + };
>
> [Severity: High]
> Does this unaligned size combined with no-map cause memory attribute aliasing
> on arm64?
>
> The region has an unaligned size of 0x99240 (627264 bytes). The no-map
> property drops this exact byte range from the kernel's linear map, leaving the
> remainder of the page (0x9e168240-0x9e169000) to be mapped as Normal Cacheable
> memory.
>
> When the simple-framebuffer driver calls ioremap_wc(), it maps the entire page
> at 0x9e168000 as Write-Combine (Normal Non-Cacheable), creating an attribute
> alias.
Possibly an issue? I haven't seen any other Exynos device trees do anything differently so I'll wait for a maintainer to weigh in.
>
> > +
> > + misc-rmem {
> > + /*
> > + * Some of these regions belong to memory-mapped
> > + * devices, and will be assigned to drivers as support
> > + * is added.
> > + *
> > + * Other regions belong to the TrustZone firmware
> > + * and should never be touched.
> > + */
> > + reg = <0x0 0x87000000 0x200000>,
>
> [Severity: Medium]
> Is it valid to use reserved-memory for memory-mapped devices and regions
> outside system RAM?
>
> The Devicetree specification dictates that reserved-memory regions MUST be
> contained within a defined /memory node. The misc-rmem node includes
> addresses (e.g., 0xa0000000, 0xb0000000) that fall within the
> 0x9ea00000-0xc0000000 range explicitly omitted from the /memory node.
>
> Additionally, since these are MMIO regions, shouldn't they be described as
> device nodes on a bus rather than reserved RAM?
>
These addresses *are* part of RAM. It is just a temporarily disabled region.
> [Severity: Low]
> This isn't a bug, but this node is missing the unit address @87000000
> to match the first reg entry, which will generate a unit_address_vs_reg dtc
> compiler warning.
>
Will wait for a maintainer to weigh in on this one too, but I'll likely fix it in v2.
> --
> Sashiko AI review · https://sashiko.dev/#/patchset/20260817-for-next-lucky7-v1-0-42ffb2b71ba2@member.fsf.org?part=2
>
Kind regards,
- Aiden Isik
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/2] Hi there,
2026-08-17 10:27 ` Aiden Isik
` (2 preceding siblings ...)
(?)
@ 2026-08-17 11:07 ` Krzysztof Kozlowski
2026-08-17 13:46 ` Aiden Isik
-1 siblings, 1 reply; 12+ messages in thread
From: Krzysztof Kozlowski @ 2026-08-17 11:07 UTC (permalink / raw)
To: aidenisik, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Peter Griffin, Alim Akhtar
Cc: devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel,
Aiden Isik
On 17/08/2026 12:27, Aiden Isik via B4 Relay wrote:
> This patchset adds initial support for the Exynos 5515 SoC, along with
You already sent a thread called "Hi there,". One is enough. Please name
cover letters correctly, so it won't get messed in our mailboxes.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 0/2] Hi there,
2026-08-17 11:07 ` [PATCH 0/2] Hi there, Krzysztof Kozlowski
@ 2026-08-17 13:46 ` Aiden Isik
0 siblings, 0 replies; 12+ messages in thread
From: Aiden Isik @ 2026-08-17 13:46 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: aidenisik, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Peter Griffin, Alim Akhtar, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel, Aiden Isik
> > This patchset adds initial support for the Exynos 5515 SoC, along with
> You already sent a thread called "Hi there,". One is enough. Please name
> cover letters correctly, so it won't get messed in our mailboxes.
Sorry about that. First time using b4 and a mailing list for patch
submissions, and I failed to notice the missing subject.
Will fix in v2 as I have issues Sashiko picked up to fix anyways.
> Best regards,
> Krzysztof
Kind regards,
- Aiden Isik
^ permalink raw reply [flat|nested] 12+ messages in thread