[PATCH v3] ARM: dts: renesas: r9a06g032-rzn1d400-eb: enable GPIOs on CN12

[PATCH v3] ARM: dts: renesas: r9a06g032-rzn1d400-eb: enable GPIOs on CN12

[Wolfram Sang]

CN12 offers some GPIOs independently of switch settings. Add the nodes.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---

Changes since v2:
* dropped patch 1 because Geert already queued it
* renamed pin node to 'cn12'
* rely on default pin-bias and drive-strength

 .../arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts
index 303b5926d8d1..eb7295504715 100644
--- a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts
+++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts
@@ -53,6 +53,11 @@ led@1 {
 	};
 };
 
+&gpio2b {
+	pinctrl-0 = <&pins_cn12>;
+	pinctrl-names = "default";
+};
+
 &i2c2 {
 	/* Sensors are different across revisions. All are LM75B compatible */
 	sensor@49 {
@@ -81,6 +86,15 @@ &pci_usb {
 };
 
 &pinctrl {
+	pins_cn12: pins-cn12 {
+		pinmux = <RZN1_PINMUX(164, RZN1_FUNC_GPIO)>,
+			 <RZN1_PINMUX(165, RZN1_FUNC_GPIO)>,
+			 <RZN1_PINMUX(166, RZN1_FUNC_GPIO)>,
+			 <RZN1_PINMUX(167, RZN1_FUNC_GPIO)>,
+			 <RZN1_PINMUX(168, RZN1_FUNC_GPIO)>,
+			 <RZN1_PINMUX(169, RZN1_FUNC_GPIO)>;
+	};
+
 	pins_eth0: pins-eth0 {
 		pinmux = <RZN1_PINMUX(0, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
 			 <RZN1_PINMUX(1, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
-- 
2.47.3

Re: [PATCH v3] ARM: dts: renesas: r9a06g032-rzn1d400-eb: enable GPIOs on CN12

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The `pinctrl-0` and `pinctrl-names` properties are incorrectly placed in the `&gpio2b` child port node instead of the parent `&gpio2` controller node, causing the pinmux configuration to be completely ignored at runtime.
--

--- Patch [1]: [PATCH v3] ARM: dts: renesas: r9a06g032-rzn1d400-eb: enable GPIOs on CN12 ---
commit 36b1187107fd9570845145160bae9fb449b21c31
Author: Wolfram Sang <wsa+renesas@sang-engineering.com>

ARM: dts: renesas: r9a06g032-rzn1d400-eb: enable GPIOs on CN12

This commit enables GPIOs on CN12 for the RZN1D400 evaluation board. It adds
the pinmux configurations for the CN12 pins and assigns them to the gpio2b
node.

> diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts
> index 97a339b30d764..e5bff296ea4a9 100644
> --- a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts
> +++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts
> @@ -53,6 +53,11 @@ led@1 {
>  	};
>  };
>  
> +&gpio2b {
> +	pinctrl-0 = <&pins_cn12>;
> +	pinctrl-names = "default";
> +};

[Severity: Medium]
Will these pinctrl properties be ignored here?

The Linux device core parses devicetree pinctrl properties by calling
pinctrl_bind_pins() strictly during driver probing. Since the gpio-dwapb
driver binds to the parent gpio2 controller node, the child port nodes like
gpio2b are never probed as independent platform devices. 

Because gpio2b bypasses the probe path, the pinctrl core will not process
these properties, leaving the pins unconfigured. Should these pinctrl
properties be placed in the parent &gpio2 node instead?

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260817103255.49565-2-wsa+renesas@sang-engineering.com?part=1