* [RFC PATCH 0/3] RISC-V Sspesa: Linux perf precise sample attribution
@ 2026-08-17 16:02 ` Mayuresh Chitale
0 siblings, 0 replies; 10+ messages in thread
From: Mayuresh Chitale @ 2026-08-17 16:02 UTC (permalink / raw)
To: Albert Ou, Alexandre Ghiti, Andrew Jones, Andrew Morton,
Andy Chiu, Anup Patel, Atish Patra, Charlie Jenkins,
Chunyan Zhang, Clément Léger, Conor Dooley,
Deepak Gupta, Guodong Xu, Guodong Xu, Hui Wang,
Krzysztof Kozlowski, Mark Rutland, Mayuresh Chitale,
Palmer Dabbelt, Paul Walmsley, Pincheng Wang, Rob Herring,
Sergey Matyukevich, Thomas Huth, Will Deacon, Xu Lu
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-perf-users,
linux-riscv
This Linux series adds kernel support for the RISC-V Performance Event
Sampling extensions Sspesa (Precise Event Sample Attribution) and
Ssplcofi (Precise Local Counter Overflow Interrupt).
The first two patches add the DT binding and ISA-extension detection
(Ssplcofi depends on Sspesa). The third patch uses shpmspc to report the
sample PC via PERF_SAMPLE_IP in the SBI PMU overflow handler, and
exports shpmsdata as PERF_SAMPLE_RAW.
Reproducing the full setup:
Sspesa support requires three projects: OpenSBI, Linux and QEMU. The
matching branches are:
OpenSBI: https://github.com/mdchitale/opensbi/tree/riscv_sspesa_rfc_v1
Linux: https://github.com/mdchitale/linux/tree/riscv_sspesa_rfc_v1
QEMU: https://github.com/mdchitale/qemu/tree/riscv_sspesa_rfc_v1
To test Sspesa, build OpenSBI, Linux and QEMU from the branches above,
then boot Linux with:
qemu-system-riscv64 -nographic -machine virt -smp 2 -m 2G \
-cpu rv64,sscofpmf=on,sspesa=on \
-bios /path/to/fw_dynamic.bin -kernel /path/to/Image \
-drive file=/path/to/rootfs.img,id=hd0,format=raw,if=none \
-device virtio-blk-device,drive=hd0 \
-append "root=/dev/vda rw console=ttyS0 earlycon=sbi"
With all three in place, a counter overflow (e.g. 'perf record -e
cycles -c 1000000 -- <workload>') is attributed using the
hardware-provided sample PC (shpmspc) and counter ID (shpmsdata)
instead of falling back to epc.
Mayuresh Chitale (3):
dt-bindings: riscv: Add Sspesa and Ssplcofi extensions
riscv: Add detection for Sspesa and Ssplcofi extensions
perf/riscv: Use Sspesa for precise sample attribution
.../devicetree/bindings/riscv/extensions.yaml | 19 ++++++++++++
arch/riscv/include/asm/csr.h | 7 +++++
arch/riscv/include/asm/hwcap.h | 2 ++
arch/riscv/kernel/cpufeature.c | 12 ++++++++
drivers/perf/riscv_pmu_sbi.c | 29 +++++++++++++++++++
5 files changed, 69 insertions(+)
--
2.43.0
^ permalink raw reply [flat|nested] 10+ messages in thread
* [RFC PATCH 0/3] RISC-V Sspesa: Linux perf precise sample attribution
@ 2026-08-17 16:02 ` Mayuresh Chitale
0 siblings, 0 replies; 10+ messages in thread
From: Mayuresh Chitale @ 2026-08-17 16:02 UTC (permalink / raw)
To: Albert Ou, Alexandre Ghiti, Andrew Jones, Andrew Morton,
Andy Chiu, Anup Patel, Atish Patra, Charlie Jenkins,
Chunyan Zhang, Clément Léger, Conor Dooley,
Deepak Gupta, Guodong Xu, Guodong Xu, Hui Wang,
Krzysztof Kozlowski, Mark Rutland, Mayuresh Chitale,
Palmer Dabbelt, Paul Walmsley, Pincheng Wang, Rob Herring,
Sergey Matyukevich, Thomas Huth, Will Deacon, Xu Lu
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-perf-users,
linux-riscv
This Linux series adds kernel support for the RISC-V Performance Event
Sampling extensions Sspesa (Precise Event Sample Attribution) and
Ssplcofi (Precise Local Counter Overflow Interrupt).
The first two patches add the DT binding and ISA-extension detection
(Ssplcofi depends on Sspesa). The third patch uses shpmspc to report the
sample PC via PERF_SAMPLE_IP in the SBI PMU overflow handler, and
exports shpmsdata as PERF_SAMPLE_RAW.
Reproducing the full setup:
Sspesa support requires three projects: OpenSBI, Linux and QEMU. The
matching branches are:
OpenSBI: https://github.com/mdchitale/opensbi/tree/riscv_sspesa_rfc_v1
Linux: https://github.com/mdchitale/linux/tree/riscv_sspesa_rfc_v1
QEMU: https://github.com/mdchitale/qemu/tree/riscv_sspesa_rfc_v1
To test Sspesa, build OpenSBI, Linux and QEMU from the branches above,
then boot Linux with:
qemu-system-riscv64 -nographic -machine virt -smp 2 -m 2G \
-cpu rv64,sscofpmf=on,sspesa=on \
-bios /path/to/fw_dynamic.bin -kernel /path/to/Image \
-drive file=/path/to/rootfs.img,id=hd0,format=raw,if=none \
-device virtio-blk-device,drive=hd0 \
-append "root=/dev/vda rw console=ttyS0 earlycon=sbi"
With all three in place, a counter overflow (e.g. 'perf record -e
cycles -c 1000000 -- <workload>') is attributed using the
hardware-provided sample PC (shpmspc) and counter ID (shpmsdata)
instead of falling back to epc.
Mayuresh Chitale (3):
dt-bindings: riscv: Add Sspesa and Ssplcofi extensions
riscv: Add detection for Sspesa and Ssplcofi extensions
perf/riscv: Use Sspesa for precise sample attribution
.../devicetree/bindings/riscv/extensions.yaml | 19 ++++++++++++
arch/riscv/include/asm/csr.h | 7 +++++
arch/riscv/include/asm/hwcap.h | 2 ++
arch/riscv/kernel/cpufeature.c | 12 ++++++++
drivers/perf/riscv_pmu_sbi.c | 29 +++++++++++++++++++
5 files changed, 69 insertions(+)
--
2.43.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 10+ messages in thread
* [RFC PATCH 1/3] dt-bindings: riscv: Add Sspesa and Ssplcofi extensions
2026-08-17 16:02 ` Mayuresh Chitale
@ 2026-08-17 16:02 ` Mayuresh Chitale
-1 siblings, 0 replies; 10+ messages in thread
From: Mayuresh Chitale @ 2026-08-17 16:02 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Guodong Xu,
Andrew Morton, Deepak Gupta, Xu Lu, Pincheng Wang
Cc: Mayuresh Chitale, devicetree, linux-riscv, linux-kernel
Document the RISC-V Performance Event Sampling extensions Sspesa
(Precise Event Sample Attribution) and Ssplcofi (Precise Local Counter
Overflow Interrupt) in the ISA extensions binding.
Add a dependency rule requiring Sspesa to be present whenever Ssplcofi
is present.
Signed-off-by: Mayuresh Chitale <mayuresh.chitale@oss.qualcomm.com>
---
.../devicetree/bindings/riscv/extensions.yaml | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 5ffc40d599c0..f316b93754ff 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -232,6 +232,18 @@ properties:
ratified at commit d70011dde6c2 ("Update to ratified state")
of riscv-j-extension.
+ - const: sspesa
+ description: |
+ The standard Sspesa supervisor-level extension for precise event
+ sample attribution, as defined in the RISC-V Performance Event
+ Sampling specification.
+
+ - const: ssplcofi
+ description: |
+ The standard Ssplcofi supervisor-level extension for precise local
+ counter overflow interrupts, as defined in the RISC-V Performance
+ Event Sampling specification. Ssplcofi depends on Sspesa.
+
- const: ssstateen
description: |
The standard Ssstateen extension for supervisor-mode view of the
@@ -934,6 +946,13 @@ properties:
const: smnpm
- contains:
const: ssnpm
+ # Ssplcofi depends on Sspesa
+ - if:
+ contains:
+ const: ssplcofi
+ then:
+ contains:
+ const: sspesa
# Za64rs and Ziccrse depend on Zalrsc or A
- if:
contains:
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [RFC PATCH 1/3] dt-bindings: riscv: Add Sspesa and Ssplcofi extensions
@ 2026-08-17 16:02 ` Mayuresh Chitale
0 siblings, 0 replies; 10+ messages in thread
From: Mayuresh Chitale @ 2026-08-17 16:02 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Guodong Xu,
Andrew Morton, Deepak Gupta, Xu Lu, Pincheng Wang
Cc: Mayuresh Chitale, devicetree, linux-riscv, linux-kernel
Document the RISC-V Performance Event Sampling extensions Sspesa
(Precise Event Sample Attribution) and Ssplcofi (Precise Local Counter
Overflow Interrupt) in the ISA extensions binding.
Add a dependency rule requiring Sspesa to be present whenever Ssplcofi
is present.
Signed-off-by: Mayuresh Chitale <mayuresh.chitale@oss.qualcomm.com>
---
.../devicetree/bindings/riscv/extensions.yaml | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 5ffc40d599c0..f316b93754ff 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -232,6 +232,18 @@ properties:
ratified at commit d70011dde6c2 ("Update to ratified state")
of riscv-j-extension.
+ - const: sspesa
+ description: |
+ The standard Sspesa supervisor-level extension for precise event
+ sample attribution, as defined in the RISC-V Performance Event
+ Sampling specification.
+
+ - const: ssplcofi
+ description: |
+ The standard Ssplcofi supervisor-level extension for precise local
+ counter overflow interrupts, as defined in the RISC-V Performance
+ Event Sampling specification. Ssplcofi depends on Sspesa.
+
- const: ssstateen
description: |
The standard Ssstateen extension for supervisor-mode view of the
@@ -934,6 +946,13 @@ properties:
const: smnpm
- contains:
const: ssnpm
+ # Ssplcofi depends on Sspesa
+ - if:
+ contains:
+ const: ssplcofi
+ then:
+ contains:
+ const: sspesa
# Za64rs and Ziccrse depend on Zalrsc or A
- if:
contains:
--
2.43.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [RFC PATCH 2/3] riscv: Add detection for Sspesa and Ssplcofi extensions
2026-08-17 16:02 ` Mayuresh Chitale
@ 2026-08-17 16:02 ` Mayuresh Chitale
-1 siblings, 0 replies; 10+ messages in thread
From: Mayuresh Chitale @ 2026-08-17 16:02 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Charlie Jenkins, Andy Chiu, Deepak Gupta, Thomas Huth,
Mayuresh Chitale, Sergey Matyukevich, Pincheng Wang, Andrew Jones,
Chunyan Zhang, Xu Lu, Clément Léger, Hui Wang,
Guodong Xu
Cc: linux-riscv, linux-kernel
Add ISA extension detection for the RISC-V Performance Event Sampling
extensions Sspesa (Precise Event Sample Attribution) and Ssplcofi
(Precise Local Counter Overflow Interrupt).
Ssplcofi requires Sspesa, so validate that Sspesa is present before
enabling Ssplcofi.
Signed-off-by: Mayuresh Chitale <mayuresh.chitale@oss.qualcomm.com>
---
arch/riscv/include/asm/csr.h | 7 +++++++
arch/riscv/include/asm/hwcap.h | 2 ++
arch/riscv/kernel/cpufeature.c | 12 ++++++++++++
3 files changed, 21 insertions(+)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 31b8988f4488..a5f38ff35336 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -316,6 +316,13 @@
#define CSR_SCOUNTOVF 0xda0
+/* Temporary addresses for Sspesa (Precise Event Sample Attribution) CSRs. */
+#define CSR_SHPMSPC 0x5d0
+#define CSR_SHPMSDATA 0x5d1
+
+/* shpmsdata fields */
+#define SHPMSDATA_CNTRID GENMASK(4, 0)
+
#define CSR_SSTATUS 0x100
#define CSR_SIE 0x104
#define CSR_STVEC 0x105
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 7ef8e5f55c8d..68f8632bc751 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -112,6 +112,8 @@
#define RISCV_ISA_EXT_ZCLSD 103
#define RISCV_ISA_EXT_ZICFILP 104
#define RISCV_ISA_EXT_ZICFISS 105
+#define RISCV_ISA_EXT_SSPESA 106
+#define RISCV_ISA_EXT_SSPLCOFI 107
#define RISCV_ISA_EXT_XLINUXENVCFG 127
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index f46aa5602d74..ab415704e317 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -287,6 +287,15 @@ static int riscv_ext_zvfbfwma_validate(const struct riscv_isa_ext_data *data,
return -EPROBE_DEFER;
}
+static int riscv_ext_ssplcofi_validate(const struct riscv_isa_ext_data *data,
+ const unsigned long *isa_bitmap)
+{
+ if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_SSPESA))
+ return 0;
+
+ return -EINVAL;
+}
+
static int riscv_ext_svadu_validate(const struct riscv_isa_ext_data *data,
const unsigned long *isa_bitmap)
{
@@ -582,6 +591,9 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
__RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
__RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_exts),
+ __RISCV_ISA_EXT_DATA(sspesa, RISCV_ISA_EXT_SSPESA),
+ __RISCV_ISA_EXT_DATA_VALIDATE(ssplcofi, RISCV_ISA_EXT_SSPLCOFI,
+ riscv_ext_ssplcofi_validate),
__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
__RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE),
__RISCV_ISA_EXT_DATA_VALIDATE(svadu, RISCV_ISA_EXT_SVADU, riscv_ext_svadu_validate),
--
2.43.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [RFC PATCH 2/3] riscv: Add detection for Sspesa and Ssplcofi extensions
@ 2026-08-17 16:02 ` Mayuresh Chitale
0 siblings, 0 replies; 10+ messages in thread
From: Mayuresh Chitale @ 2026-08-17 16:02 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Charlie Jenkins, Andy Chiu, Deepak Gupta, Thomas Huth,
Mayuresh Chitale, Sergey Matyukevich, Pincheng Wang, Andrew Jones,
Chunyan Zhang, Xu Lu, Clément Léger, Hui Wang,
Guodong Xu
Cc: linux-riscv, linux-kernel
Add ISA extension detection for the RISC-V Performance Event Sampling
extensions Sspesa (Precise Event Sample Attribution) and Ssplcofi
(Precise Local Counter Overflow Interrupt).
Ssplcofi requires Sspesa, so validate that Sspesa is present before
enabling Ssplcofi.
Signed-off-by: Mayuresh Chitale <mayuresh.chitale@oss.qualcomm.com>
---
arch/riscv/include/asm/csr.h | 7 +++++++
arch/riscv/include/asm/hwcap.h | 2 ++
arch/riscv/kernel/cpufeature.c | 12 ++++++++++++
3 files changed, 21 insertions(+)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 31b8988f4488..a5f38ff35336 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -316,6 +316,13 @@
#define CSR_SCOUNTOVF 0xda0
+/* Temporary addresses for Sspesa (Precise Event Sample Attribution) CSRs. */
+#define CSR_SHPMSPC 0x5d0
+#define CSR_SHPMSDATA 0x5d1
+
+/* shpmsdata fields */
+#define SHPMSDATA_CNTRID GENMASK(4, 0)
+
#define CSR_SSTATUS 0x100
#define CSR_SIE 0x104
#define CSR_STVEC 0x105
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 7ef8e5f55c8d..68f8632bc751 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -112,6 +112,8 @@
#define RISCV_ISA_EXT_ZCLSD 103
#define RISCV_ISA_EXT_ZICFILP 104
#define RISCV_ISA_EXT_ZICFISS 105
+#define RISCV_ISA_EXT_SSPESA 106
+#define RISCV_ISA_EXT_SSPLCOFI 107
#define RISCV_ISA_EXT_XLINUXENVCFG 127
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index f46aa5602d74..ab415704e317 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -287,6 +287,15 @@ static int riscv_ext_zvfbfwma_validate(const struct riscv_isa_ext_data *data,
return -EPROBE_DEFER;
}
+static int riscv_ext_ssplcofi_validate(const struct riscv_isa_ext_data *data,
+ const unsigned long *isa_bitmap)
+{
+ if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_SSPESA))
+ return 0;
+
+ return -EINVAL;
+}
+
static int riscv_ext_svadu_validate(const struct riscv_isa_ext_data *data,
const unsigned long *isa_bitmap)
{
@@ -582,6 +591,9 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
__RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
__RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_exts),
+ __RISCV_ISA_EXT_DATA(sspesa, RISCV_ISA_EXT_SSPESA),
+ __RISCV_ISA_EXT_DATA_VALIDATE(ssplcofi, RISCV_ISA_EXT_SSPLCOFI,
+ riscv_ext_ssplcofi_validate),
__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
__RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE),
__RISCV_ISA_EXT_DATA_VALIDATE(svadu, RISCV_ISA_EXT_SVADU, riscv_ext_svadu_validate),
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [RFC PATCH 3/3] perf/riscv: Use Sspesa for precise sample attribution
2026-08-17 16:02 ` Mayuresh Chitale
@ 2026-08-17 16:02 ` Mayuresh Chitale
-1 siblings, 0 replies; 10+ messages in thread
From: Mayuresh Chitale @ 2026-08-17 16:02 UTC (permalink / raw)
To: Atish Patra, Anup Patel, Will Deacon, Mark Rutland, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: Mayuresh Chitale, linux-riscv, linux-arm-kernel, linux-perf-users,
linux-kernel
When the Sspesa (Precise Event Sample Attribution) extension is
available and a counter overflows, the hardware records a sample PC in
shpmspc register and the counter ID and additional implementation-defined
data in shpmsdata register.
In the SBI PMU overflow handler, use shpmspc to report sample PC via
PERF_SAMPLE_IP for the counter that caused the overflow. Shpmsdata is
exported as raw data to userspace when events request PERF_SAMPLE_RAW
sample type and it assists in deriving the sample PC from shpmspc if
precise attribution is not supported for the event.
If sspesa is not available or for counters that don't match
shpmsdata.CNTRID, fallback to epc for PERF_SAMPLE_IP.
Signed-off-by: Mayuresh Chitale <mayuresh.chitale@oss.qualcomm.com>
---
drivers/perf/riscv_pmu_sbi.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index dfc886dee5ad..1b0b1cc612de 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -63,6 +63,8 @@ PMU_FORMAT_ATTR(firmware, "config:62-63");
static bool sbi_v2_available;
static bool sbi_v3_available;
+static bool sspesa_available;
+
static DEFINE_STATIC_KEY_FALSE(sbi_pmu_snapshot_available);
#define sbi_pmu_snapshot_available() \
static_branch_unlikely(&sbi_pmu_snapshot_available)
@@ -1051,6 +1053,11 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev)
struct cpu_hw_events *cpu_hw_evt = dev;
u64 start_clock = sched_clock();
struct riscv_pmu_snapshot_data *sdata = cpu_hw_evt->snapshot_addr;
+ unsigned long sample_pc = 0;
+ unsigned long sample_data = 0;
+ int sample_cntrid = -1;
+ u64 raw_sample;
+ struct perf_raw_record raw = { 0 };
if (WARN_ON_ONCE(!cpu_hw_evt))
return IRQ_NONE;
@@ -1088,6 +1095,16 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev)
return IRQ_NONE;
regs = get_irq_regs();
+ /*
+ * Sspesa records the PC and metadata of the overflowing counter in
+ * hardware. The PC is precise only for events that support precise
+ * attribution; otherwise it is best-effort.
+ */
+ if (sspesa_available) {
+ sample_pc = csr_read(CSR_SHPMSPC);
+ sample_data = csr_read(CSR_SHPMSDATA);
+ sample_cntrid = sample_data & SHPMSDATA_CNTRID;
+ }
for_each_set_bit(lidx, cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS) {
struct perf_event *event = cpu_hw_evt->events[lidx];
@@ -1123,6 +1140,15 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev)
riscv_pmu_event_update(event);
hw_evt->state |= PERF_HES_UPTODATE;
perf_sample_data_init(&data, 0, hw_evt->last_period);
+ if (sspesa_available && hidx == sample_cntrid) {
+ data.ip = sample_pc;
+ data.sample_flags |= PERF_SAMPLE_IP;
+
+ raw_sample = sample_data;
+ raw.frag.size = sizeof(raw_sample);
+ raw.frag.data = &raw_sample;
+ perf_sample_save_raw_data(&data, event, &raw);
+ }
if (riscv_pmu_event_set_period(event)) {
/*
* Unlike other ISAs, RISC-V don't have to disable interrupts
@@ -1194,6 +1220,9 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde
struct cpu_hw_events __percpu *hw_events = pmu->hw_events;
struct irq_domain *domain = NULL;
+ if (riscv_isa_extension_available(NULL, SSPESA))
+ sspesa_available = true;
+
if (riscv_isa_extension_available(NULL, SSCOFPMF)) {
riscv_pmu_irq_num = RV_IRQ_PMU;
riscv_pmu_use_irq = true;
--
2.43.0
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^ permalink raw reply related [flat|nested] 10+ messages in thread
* [RFC PATCH 3/3] perf/riscv: Use Sspesa for precise sample attribution
@ 2026-08-17 16:02 ` Mayuresh Chitale
0 siblings, 0 replies; 10+ messages in thread
From: Mayuresh Chitale @ 2026-08-17 16:02 UTC (permalink / raw)
To: Atish Patra, Anup Patel, Will Deacon, Mark Rutland, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: Mayuresh Chitale, linux-riscv, linux-arm-kernel, linux-perf-users,
linux-kernel
When the Sspesa (Precise Event Sample Attribution) extension is
available and a counter overflows, the hardware records a sample PC in
shpmspc register and the counter ID and additional implementation-defined
data in shpmsdata register.
In the SBI PMU overflow handler, use shpmspc to report sample PC via
PERF_SAMPLE_IP for the counter that caused the overflow. Shpmsdata is
exported as raw data to userspace when events request PERF_SAMPLE_RAW
sample type and it assists in deriving the sample PC from shpmspc if
precise attribution is not supported for the event.
If sspesa is not available or for counters that don't match
shpmsdata.CNTRID, fallback to epc for PERF_SAMPLE_IP.
Signed-off-by: Mayuresh Chitale <mayuresh.chitale@oss.qualcomm.com>
---
drivers/perf/riscv_pmu_sbi.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index dfc886dee5ad..1b0b1cc612de 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -63,6 +63,8 @@ PMU_FORMAT_ATTR(firmware, "config:62-63");
static bool sbi_v2_available;
static bool sbi_v3_available;
+static bool sspesa_available;
+
static DEFINE_STATIC_KEY_FALSE(sbi_pmu_snapshot_available);
#define sbi_pmu_snapshot_available() \
static_branch_unlikely(&sbi_pmu_snapshot_available)
@@ -1051,6 +1053,11 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev)
struct cpu_hw_events *cpu_hw_evt = dev;
u64 start_clock = sched_clock();
struct riscv_pmu_snapshot_data *sdata = cpu_hw_evt->snapshot_addr;
+ unsigned long sample_pc = 0;
+ unsigned long sample_data = 0;
+ int sample_cntrid = -1;
+ u64 raw_sample;
+ struct perf_raw_record raw = { 0 };
if (WARN_ON_ONCE(!cpu_hw_evt))
return IRQ_NONE;
@@ -1088,6 +1095,16 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev)
return IRQ_NONE;
regs = get_irq_regs();
+ /*
+ * Sspesa records the PC and metadata of the overflowing counter in
+ * hardware. The PC is precise only for events that support precise
+ * attribution; otherwise it is best-effort.
+ */
+ if (sspesa_available) {
+ sample_pc = csr_read(CSR_SHPMSPC);
+ sample_data = csr_read(CSR_SHPMSDATA);
+ sample_cntrid = sample_data & SHPMSDATA_CNTRID;
+ }
for_each_set_bit(lidx, cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS) {
struct perf_event *event = cpu_hw_evt->events[lidx];
@@ -1123,6 +1140,15 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev)
riscv_pmu_event_update(event);
hw_evt->state |= PERF_HES_UPTODATE;
perf_sample_data_init(&data, 0, hw_evt->last_period);
+ if (sspesa_available && hidx == sample_cntrid) {
+ data.ip = sample_pc;
+ data.sample_flags |= PERF_SAMPLE_IP;
+
+ raw_sample = sample_data;
+ raw.frag.size = sizeof(raw_sample);
+ raw.frag.data = &raw_sample;
+ perf_sample_save_raw_data(&data, event, &raw);
+ }
if (riscv_pmu_event_set_period(event)) {
/*
* Unlike other ISAs, RISC-V don't have to disable interrupts
@@ -1194,6 +1220,9 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde
struct cpu_hw_events __percpu *hw_events = pmu->hw_events;
struct irq_domain *domain = NULL;
+ if (riscv_isa_extension_available(NULL, SSPESA))
+ sspesa_available = true;
+
if (riscv_isa_extension_available(NULL, SSCOFPMF)) {
riscv_pmu_irq_num = RV_IRQ_PMU;
riscv_pmu_use_irq = true;
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [RFC PATCH 1/3] dt-bindings: riscv: Add Sspesa and Ssplcofi extensions
2026-08-17 16:02 ` Mayuresh Chitale
(?)
@ 2026-08-17 16:09 ` sashiko-bot
-1 siblings, 0 replies; 10+ messages in thread
From: sashiko-bot @ 2026-08-17 16:09 UTC (permalink / raw)
To: Mayuresh Chitale; +Cc: conor+dt, robh, devicetree
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The `ssplcofi` extension is missing a dependency on `sscofpmf` in its validation rules.
--
--- Patch [1]: [RFC PATCH 1/3] dt-bindings: riscv: Add Sspesa and Ssplcofi extensions ---
commit d9c857c632fdf5807bbc999144379f6067037960
Author: Mayuresh Chitale <mayuresh.chitale@oss.qualcomm.com>
dt-bindings: riscv: Add Sspesa and Ssplcofi extensions
Document the RISC-V Performance Event Sampling extensions Sspesa and Ssplcofi
in the ISA extensions binding. This adds descriptions for both extensions
and a dependency rule requiring Sspesa when Ssplcofi is present.
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 5ffc40d599c02..f316b93754ff7 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
[ ... ]
> @@ -934,6 +946,13 @@ properties:
> const: smnpm
> - contains:
> const: ssnpm
> + # Ssplcofi depends on Sspesa
> + - if:
> + contains:
> + const: ssplcofi
> + then:
> + contains:
> + const: sspesa
[Severity: Low]
Should this validation block also enforce a dependency on the base sscofpmf
extension?
Without requiring sscofpmf, an invalid device tree configuration declaring
ssplcofi without the base extension could silently pass dtbs_check.
> # Za64rs and Ziccrse depend on Zalrsc or A
> - if:
> contains:
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260817160222.3313295-1-mayuresh.chitale@oss.qualcomm.com?part=1
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [RFC PATCH 3/3] perf/riscv: Use Sspesa for precise sample attribution
2026-08-17 16:02 ` Mayuresh Chitale
(?)
@ 2026-08-17 16:17 ` sashiko-bot
-1 siblings, 0 replies; 10+ messages in thread
From: sashiko-bot @ 2026-08-17 16:17 UTC (permalink / raw)
To: Mayuresh Chitale; +Cc: linux-perf-users
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Logical counter index is incorrectly compared against the physical hardware counter ID when SBI PMU snapshots are used.
- [Medium] Overriding `data.ip` without adjusting the privilege mode in `regs` causes misattribution of precise samples.
--
--- Patch [3]: [RFC PATCH 3/3] perf/riscv: Use Sspesa for precise sample attribution ---
commit b7b8e4e381234c44a7ea95a7ce26fb9dadf28f3a
Author: Mayuresh Chitale <mayuresh.chitale@oss.qualcomm.com>
Date: Mon Aug 17 16:02:19 2026 +0000
perf/riscv: Use Sspesa for precise sample attribution
This commit adds support for the Sspesa extension to provide precise event
sample attribution on RISC-V. It uses the shpmspc and shpmsdata registers
to report accurate instruction pointers and raw sample data on counter
overflow.
> diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> index dfc886dee5ad0..1b0b1cc612def 100644
> --- a/drivers/perf/riscv_pmu_sbi.c
> +++ b/drivers/perf/riscv_pmu_sbi.c
[ ... ]
> @@ -1123,6 +1140,15 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev)
> riscv_pmu_event_update(event);
> hw_evt->state |= PERF_HES_UPTODATE;
> perf_sample_data_init(&data, 0, hw_evt->last_period);
> + if (sspesa_available && hidx == sample_cntrid) {
[Severity: High]
Earlier in pmu_sbi_ovf_handler(), hidx can be assigned the logical index:
if (sbi_pmu_snapshot_available())
hidx = lidx;
Since sample_cntrid represents a physical hardware index read from
CSR_SHPMSDATA, does comparing the logical hidx against the physical
sample_cntrid cause precise samples to be dropped or incorrectly attributed
when SBI PMU snapshots are enabled?
> + data.ip = sample_pc;
> + data.sample_flags |= PERF_SAMPLE_IP;
> +
> + raw_sample = sample_data;
> + raw.frag.size = sizeof(raw_sample);
> + raw.frag.data = &raw_sample;
> + perf_sample_save_raw_data(&data, event, &raw);
> + }
[Severity: Medium]
When overriding data.ip with the precise PC (sample_pc), could we run into
privilege mode mismatches?
If an overflow occurs in user space but the interrupt skids into kernel space,
data.ip gets the precise user-space PC, but regs still reflects the skidded
kernel state.
Since perf_event_overflow() is called shortly after this block and relies on
perf_misc_flags(regs) to determine the privilege level, will this cause
userspace tools to attempt resolving user-space addresses against the kernel
symbol map?
> if (riscv_pmu_event_set_period(event)) {
> /*
> * Unlike other ISAs, RISC-V don't have to disable interrupts
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260817160222.3313295-1-mayuresh.chitale@oss.qualcomm.com?part=3
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2026-08-17 16:17 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-08-17 16:02 [RFC PATCH 0/3] RISC-V Sspesa: Linux perf precise sample attribution Mayuresh Chitale
2026-08-17 16:02 ` Mayuresh Chitale
2026-08-17 16:02 ` [RFC PATCH 1/3] dt-bindings: riscv: Add Sspesa and Ssplcofi extensions Mayuresh Chitale
2026-08-17 16:02 ` Mayuresh Chitale
2026-08-17 16:09 ` sashiko-bot
2026-08-17 16:02 ` [RFC PATCH 2/3] riscv: Add detection for " Mayuresh Chitale
2026-08-17 16:02 ` Mayuresh Chitale
2026-08-17 16:02 ` [RFC PATCH 3/3] perf/riscv: Use Sspesa for precise sample attribution Mayuresh Chitale
2026-08-17 16:02 ` Mayuresh Chitale
2026-08-17 16:17 ` sashiko-bot
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