From: Junjie Cao <junjie.cao@intel.com>
To: Manish Honap <mhonap@nvidia.com>
Cc: alex@shazbot.org, ankita@nvidia.com, jic23@kernel.org,
dave.jiang@intel.com, alejandro.lucero-palau@amd.com,
smadhavan@nvidia.com, pierrick.bouvier@oss.qualcomm.com,
mst@redhat.com, imammedo@redhat.com, anisinha@redhat.com,
pbonzini@redhat.com, eric.auger@redhat.com,
peter.maydell@linaro.org, richard.henderson@linaro.org,
clg@redhat.com, cohuck@redhat.com, kjaju@nvidia.com,
vsethi@nvidia.com, zhiw@nvidia.com, qemu-devel@nongnu.org,
qemu-arm@nongnu.org
Subject: Re: [PATCH 06/10] hw/vfio/pci: Bind a CXL device to its fixed memory window
Date: Tue, 18 Aug 2026 17:52:24 +0800 [thread overview]
Message-ID: <20260818095226.252213-1-junjie.cao@intel.com> (raw)
In-Reply-To: <20260813130623.2499506-7-mhonap@nvidia.com>
Hi Manish,
On Thu, 13 Aug 2026 18:36:19 +0530, Manish Honap wrote:
> +/*
> + * Cold-plug path: the CFMWS windows are placed at machine init done, so the
> + * binding can only be validated from this notifier. The VM has not run yet, so
> + * a configuration error is fatal to startup. A hotplugged device is validated
> + * in realize instead (see vfio_cxl_setup), where the failure fails device_add
> + * without taking down the running VM.
At this point in the series that isn't true yet: the
DEVICE(vdev)->hotplugged branch only arrives in patch 7, while this
patch registers the notifier unconditionally.
qemu_add_machine_init_done_notifier() invokes the notifier immediately
once the machine has reached PHASE_MACHINE_READY (hw/core/machine.c),
so between patches 6 and 7 a device_add with a bad CFMWS config lands
in vfio_cxl_bind_fmws() and exit(1)s the running VM. Move the hotplug
branch from patch 7 into this patch; then every point of the series
matches the comment.
> + for (slot = 0; slot < PCI_SLOT_MAX; slot++) {
> + for (fn = 0; fn < PCI_FUNC_MAX; fn++) {
> + if (ep_bus->devices[PCI_DEVFN(slot, fn)]) {
> + nendpoints++;
> + break;
This counts occupied slots, not functions: the inner loop breaks on
the first function of a slot, so two vfio-cxl functions cold-plugged
at slot 0 each pass with nendpoints == 1, bind the same single-target
window, and map at the same base with equal priority -- the aliasing
this check exists to reject. Count devfns instead.
Many thanks,
Junjie
next prev parent reply other threads:[~2026-08-18 9:52 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-13 13:06 [PATCH 00/10] QEMU: CXL Type-2 device passthrough via vfio-pci mhonap
2026-08-13 13:06 ` [PATCH 01/10] linux-headers: Update vfio.h for CXL Type-2 passthrough mhonap
2026-08-13 13:06 ` [PATCH 02/10] hw/vfio/region: Add vfio_region_setup_with_ops() mhonap
2026-08-13 13:06 ` [PATCH 03/10] hw/vfio/pci: Detect a CXL Type-2 device and read its geometry mhonap
2026-08-13 13:06 ` [PATCH 04/10] hw/vfio/pci: Enforce the passthrough topology for a CXL device mhonap
2026-08-13 13:06 ` [PATCH 05/10] hw/vfio/pci: Back the CXL memory with a RAM-device region mhonap
2026-08-13 13:06 ` [PATCH 06/10] hw/vfio/pci: Bind a CXL device to its fixed memory window mhonap
2026-08-18 9:52 ` Junjie Cao [this message]
2026-08-20 15:55 ` Manish Honap
2026-08-13 13:06 ` [PATCH 07/10] hw/vfio/pci: Map the CXL memory on the guest decoder commit mhonap
2026-08-18 9:52 ` Junjie Cao
2026-08-20 15:56 ` Manish Honap
2026-08-13 13:06 ` [PATCH 08/10] docs/cxl: Document CXL Type-2 device passthrough mhonap
2026-08-13 13:06 ` [PATCH 09/10] hw/arm/smmu-common: Allow pxb-cxl as an SMMUv3 primary bus mhonap
2026-08-13 13:06 ` [PATCH 10/10] hw/pci-host: Emit a _DSM on pxb-cxl to preserve firmware PCI config mhonap
2026-08-18 9:53 ` Junjie Cao
2026-08-20 15:56 ` Manish Honap
2026-08-13 17:42 ` [PATCH 00/10] QEMU: CXL Type-2 device passthrough via vfio-pci Cédric Le Goater
2026-08-14 9:54 ` Manish Honap
2026-08-18 9:51 ` Junjie Cao
2026-08-20 15:55 ` Manish Honap
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