* [PATCH v2 1/3] configs: add no-SPL mode fragment for k3 devices
2026-08-18 11:53 [PATCH v2 0/3] No-SPL Boot Support Gokul Praveen
@ 2026-08-18 11:53 ` Gokul Praveen
2026-08-18 11:53 ` [PATCH v2 2/3] arm: k3-binman: add tinospl.bin for direct U-Boot boot Gokul Praveen
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Gokul Praveen @ 2026-08-18 11:53 UTC (permalink / raw)
To: trini, g-praveen, n-francis, u-boot
This fragment enables a boot mode for K3 platforms where the R5 SPL
directly loads U-Boot proper, bypassing the A Core SPL stage
The R5 config modifies the payload filename to load tinospl.bin
instead of tispl.bin. The A Core config updates the U-Boot load
address to match the A Core SPL load address, allowing R5 SPL to
load U-Boot directly from that location since A Core SPL is not
present in this boot flow.
This reduces boot time by eliminating the A Core SPL stage.
Signed-off-by: Gokul Praveen <g-praveen@ti.com>
Reviewed-by Neha Malcom Francis <n-francis@ti.com>
---
configs/k3_a72_nospl.config | 1 +
configs/k3_r5_nospl.config | 1 +
2 files changed, 2 insertions(+)
create mode 100644 configs/k3_a72_nospl.config
create mode 100644 configs/k3_r5_nospl.config
diff --git a/configs/k3_a72_nospl.config b/configs/k3_a72_nospl.config
new file mode 100644
index 00000000000..7522acab950
--- /dev/null
+++ b/configs/k3_a72_nospl.config
@@ -0,0 +1 @@
+CONFIG_TEXT_BASE=0x80080000
diff --git a/configs/k3_r5_nospl.config b/configs/k3_r5_nospl.config
new file mode 100644
index 00000000000..94931bf8798
--- /dev/null
+++ b/configs/k3_r5_nospl.config
@@ -0,0 +1 @@
+CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="tinospl.bin"
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v2 2/3] arm: k3-binman: add tinospl.bin for direct U-Boot boot
2026-08-18 11:53 [PATCH v2 0/3] No-SPL Boot Support Gokul Praveen
2026-08-18 11:53 ` [PATCH v2 1/3] configs: add no-SPL mode fragment for k3 devices Gokul Praveen
@ 2026-08-18 11:53 ` Gokul Praveen
2026-08-18 11:53 ` [PATCH v2 3/3] doc: ti: document no-SPL boot mode for J784S4 EVM Gokul Praveen
2026-08-18 20:41 ` [PATCH v2 0/3] No-SPL Boot Support Tom Rini
3 siblings, 0 replies; 5+ messages in thread
From: Gokul Praveen @ 2026-08-18 11:53 UTC (permalink / raw)
To: trini, g-praveen, n-francis, u-boot
This patch adds creation of tinospl.bin for J784S4 EVM.
The contents are similar to the existing tispl.bin but the A72 SPL
and its FDT have been removed and replaced with U-Boot proper and its
FDT. This binary is used in a boot mode where R5 SPL directly loads
U-Boot, bypassing the A Core SPL stage.
This reduces boot time by eliminating the A Core SPL stage.
tispl.bin = TFA + TEE + DM + A72 SPL + FDT(A72 SPL)
tinospl.bin = TFA + TEE + DM + U-Boot + FDT(U-Boot)
Signed-off-by: Gokul Praveen <g-praveen@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
---
Makefile | 2 +-
arch/arm/dts/k3-binman.dtsi | 47 +++++++++++++++++++
arch/arm/dts/k3-j784s4-binman.dtsi | 65 ++++++++++++++++++++++++++
arch/arm/dts/k3-j784s4-evm-u-boot.dtsi | 14 ++++++
4 files changed, 127 insertions(+), 1 deletion(-)
diff --git a/Makefile b/Makefile
index c6253670a94..c6723d63f59 100644
--- a/Makefile
+++ b/Makefile
@@ -2556,7 +2556,7 @@ CLEAN_FILES += include/autoconf.mk* include/bmp_logo.h include/bmp_logo_data.h \
idbloader-spi.img lib/efi_loader/helloworld_efi.S *.itb \
Test* capsule*.*.efi-capsule capsule*.map mkimage.imx-boot.spl \
mkimage.imx-boot.u-boot mkimage-out.imx-boot.spl mkimage-out.imx-boot.u-boot \
- imx9image* m33-oei-ddrfw* tifalcon.bin
+ imx9image* m33-oei-ddrfw* tifalcon.bin tinospl.bin
# Directories & files removed with 'make mrproper'
MRPROPER_FILES += include/config include/generated spl tpl vpl \
diff --git a/arch/arm/dts/k3-binman.dtsi b/arch/arm/dts/k3-binman.dtsi
index ad127663d03..aa8479bc0f6 100644
--- a/arch/arm/dts/k3-binman.dtsi
+++ b/arch/arm/dts/k3-binman.dtsi
@@ -543,6 +543,53 @@
};
};
+ ti_nospl_template: template-16 {
+ filename = "tinospl.bin";
+ pad-byte = <0xff>;
+
+ fit {
+ description = "Configuration for no-SPL boot";
+ #address-cells = <1>;
+
+ images {
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ os = "arm-trusted-firmware";
+ load = <CONFIG_K3_ATF_LOAD_ADDR>;
+ entry = <CONFIG_K3_ATF_LOAD_ADDR>;
+ atf-bl31 {
+ filename = "bl31.bin";
+ };
+ };
+ tee {
+ description = "OP-TEE";
+ type = "tee";
+ arch = "arm64";
+ compression = "none";
+ os = "tee";
+ load = <CONFIG_K3_OPTEE_LOAD_ADDR>;
+ entry = <CONFIG_K3_OPTEE_LOAD_ADDR>;
+ tee-os {
+ filename = "tee-raw.bin";
+ optional;
+ };
+ };
+ dm {
+ description = "DM binary";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "DM";
+ load = <0x89000000>;
+ entry = <0x89000000>;
+ };
+ };
+ };
+ };
+
};
#endif
diff --git a/arch/arm/dts/k3-j784s4-binman.dtsi b/arch/arm/dts/k3-j784s4-binman.dtsi
index 34b2cc1e681..0dec4316d6b 100644
--- a/arch/arm/dts/k3-j784s4-binman.dtsi
+++ b/arch/arm/dts/k3-j784s4-binman.dtsi
@@ -317,4 +317,69 @@
};
};
};
+
+&binman{
+ ti_nospl: template-17{
+ insert-template = <&ti_nospl_template>;
+
+ fit {
+ images {
+ dm {
+ ti-dm {
+ };
+ };
+
+ uboot {
+ description = UBOOT_BOARD_DESCRIPTION;
+ type = "firmware";
+ os = "u-boot";
+ arch = "arm";
+ compression = "none";
+ load = <CONFIG_TEXT_BASE>;
+ ti-secure {
+ content = <&u_boot_nodtb_nospl>;
+ keyfile = "custMpk.pem";
+ };
+ u_boot_nodtb_nospl: blob-ext {
+ filename = "u-boot-nodtb.bin";
+ };
+ hash {
+ algo = "crc32";
+ };
+ };
+
+ fdt-0 {
+ description = BOARD_DESCRIPTION;
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+
+ ti-secure {
+ content = <&j784s4_evm_dtb_nospl>;
+ keyfile = "custMpk.pem";
+ };
+
+ j784s4_evm_dtb_nospl: blob-ext {
+ filename = "u-boot.dtb";
+ };
+
+ hash {
+ algo = "crc32";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = BOARD_DESCRIPTION;
+ firmware = "atf";
+ loadables = "tee", "dm", "uboot";
+ fdt = "fdt-0";
+ };
+ };
+ };
+ };
+};
#endif
diff --git a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
index cc0b562d27e..fc6f23736ae 100644
--- a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
+++ b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
@@ -87,6 +87,20 @@
u-boot-unsigned {
insert-template = <&u_boot_unsigned>;
};
+
+ ti-nospl {
+ insert-template = <&ti_nospl>;
+
+ fit {
+ images {
+ dm {
+ ti-dm {
+ filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ };
+ };
+ };
+ };
+ };
};
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v2 3/3] doc: ti: document no-SPL boot mode for J784S4 EVM
2026-08-18 11:53 [PATCH v2 0/3] No-SPL Boot Support Gokul Praveen
2026-08-18 11:53 ` [PATCH v2 1/3] configs: add no-SPL mode fragment for k3 devices Gokul Praveen
2026-08-18 11:53 ` [PATCH v2 2/3] arm: k3-binman: add tinospl.bin for direct U-Boot boot Gokul Praveen
@ 2026-08-18 11:53 ` Gokul Praveen
2026-08-18 20:41 ` [PATCH v2 0/3] No-SPL Boot Support Tom Rini
3 siblings, 0 replies; 5+ messages in thread
From: Gokul Praveen @ 2026-08-18 11:53 UTC (permalink / raw)
To: trini, g-praveen, n-francis, u-boot
This patch adds user documentation for the no-SPL boot mode on J784S4
EVM, where R5 SPL directly loads U-Boot proper, bypassing the A Core
SPL stage.
The documentation covers the boot flow, build steps, and usage
instructions for this boot mode using tinospl.bin.
Signed-off-by: Gokul Praveen <g-praveen@ti.com>
---
doc/board/ti/j784s4_evm.rst | 143 ++++++++++++++++++++++++++++++++++++
1 file changed, 143 insertions(+)
diff --git a/doc/board/ti/j784s4_evm.rst b/doc/board/ti/j784s4_evm.rst
index ec82228ab90..bba0c13985e 100644
--- a/doc/board/ti/j784s4_evm.rst
+++ b/doc/board/ti/j784s4_evm.rst
@@ -637,6 +637,149 @@ to the J784S4 endpoint:
This program copies the boot image to the PCIe endpoint's memory region and
writes the necessary control words to signal image transfer completion.
+No-SPL Boot Mode
+----------------
+
+No-SPL Boot Mode on J784S4 platforms is a boot approach that bypasses
+the A72 SPL while retaining U-Boot in the boot flow. This mode provides faster
+boot times compared to normal boot while maintaining U-Boot's flexibility for
+kernel loading and system configuration.
+
+**Key differences from Normal Boot:**
+
+* Skips A72 SPL execution
+* U-Boot binary included in tinospl.bin alongside TFA, OP-TEE, and DM
+* U-Boot loads at CONFIG_TEXT_BASE=0x80080000 (A72 SPL's earlier load location)
+
+Boot Flow
+^^^^^^^^^
+
+**Normal boot flow:**
+
+.. code-block::
+
+ | tiboot3.bin | tispl.bin | u-boot.img | Image |
+ |-------------+----------------------------+------------+---------|
+ R5 Core | SPL | | | |
+ ---------| \ | | | |
+ A72 Core | ------> TFA -> OP-TEE -> A72 SPL --> U-Boot --> Kernel |
+
+**With no-SPL boot mode:**
+
+.. code-block::
+
+ | tiboot3.bin | tinospl.bin | Image |
+ |-------------+-----------------------------+---------|
+ R5 Core | SPL | | |
+ ---------| \ | | |
+ A72 Core | ------> TFA -> OP-TEE -> DM -> U-Boot --> Kernel |
+
+Build Process
+^^^^^^^^^^^^^
+
+Enabling no-SPL boot mode requires re-building U-Boot as follows:
+
+0. Setup environment variables:
+"""""""""""""""""""""""""""""""
+
+Refer to the build procedure above for setting up the environment variables.
+
+1. U-Boot:
+""""""""""
+
+* **1.1 R5:**
+
+.. prompt:: bash $
+
+ # use the no-SPL config fragment for K3 platforms
+ export UBOOT_NOSPL_CFG_FRAGMENTR="k3_r5_nospl.config"
+ export UBOOT_CFG_CORTEXR="${UBOOT_CFG_CORTEXR} ${UBOOT_NOSPL_CFG_FRAGMENTR}"
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_spl_r5
+ :end-before: .. k3_rst_include_end_build_steps_spl_r5
+
+* **1.2 A72:**
+
+.. prompt:: bash $
+
+ # use the no-SPL config fragment for A72
+ export UBOOT_NOSPL_CFG_FRAGMENTA="k3_a72_nospl.config"
+ export UBOOT_CFG_CORTEXA="${UBOOT_CFG_CORTEXA} ${UBOOT_NOSPL_CFG_FRAGMENTA}"
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_uboot
+ :end-before: .. k3_rst_include_end_build_steps_uboot
+
+.. note::
+
+ The ``tinospl.bin`` file is automatically generated by binman during
+ the A72 U-Boot build process. This binary contains TFA, OP-TEE, DM, and
+ the U-Boot binary with its device tree.
+
+Usage
+^^^^^
+
+No-SPL Boot Mode uses a specialized binary called ``tinospl.bin`` which
+contains all necessary components to boot directly to U-Boot without loading
+the A72 SPL.
+
+**tinospl.bin structure:**
+
+The tinospl.bin is a FIT image containing:
+
+* **ATF (ARM Trusted Firmware)** - loaded at CONFIG_K3_ATF_LOAD_ADDR
+* **OP-TEE** - loaded at CONFIG_K3_OPTEE_LOAD_ADDR
+* **DM (Device Manager)** - loaded at 0x89000000
+* **U-Boot** - loaded at CONFIG_TEXT_BASE (0x80080000)
+* **DTB (Device Tree Blob)** - U-Boot device tree
+
+The R5 SPL requires both ``tiboot3.bin`` and ``tinospl.bin`` to be present
+in the boot partition (first partition) of the MMC device. By default, the SD
+card boot partition is used (``mmcdev=1``). The ``bootpart`` environment variable
+defaults to 1:2, specifying the second partition of the SD card.
+
+To use eMMC instead of SD as the boot media, rebuild the R5 SPL with the
+following diff:
+
+.. code-block:: diff
+
+ diff --git a/board/ti/j784s4/j784s4.env b/board/ti/j784s4/j784s4.env
+ index 82b9f0741bb..73d59ac425c 100644
+ --- a/board/ti/j784s4/j784s4.env
+ +++ b/board/ti/j784s4/j784s4.env
+ @@ -17,8 +17,8 @@ run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
+
+ boot_targets=mmc1 mmc0 usb pxe dhcp
+ boot=mmc
+ -mmcdev=1
+ -bootpart=1:2
+ +mmcdev=0
+ +bootpart=0:2
+ bootdir=/boot
+ rd_spec=-
+
+**List of files required on SD/eMMC for No-SPL Boot Mode:**
+
+.. list-table::
+ :widths: 10 15 10 25
+ :header-rows: 1
+
+ * - File
+ - Copy path on SD/eMMC
+ - Partition
+ - Description
+
+ * - ``tiboot3.bin``
+ - Boot partition (raw)
+ - 1st partition (FAT32)
+ - R5 SPL binary
+
+ * - ``tinospl.bin``
+ - Boot partition (raw)
+ - 1st partition (FAT32)
+ - Combined binary with TFA, OP-TEE, DM, and U-Boot
+
Debugging U-Boot
----------------
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH v2 0/3] No-SPL Boot Support
2026-08-18 11:53 [PATCH v2 0/3] No-SPL Boot Support Gokul Praveen
` (2 preceding siblings ...)
2026-08-18 11:53 ` [PATCH v2 3/3] doc: ti: document no-SPL boot mode for J784S4 EVM Gokul Praveen
@ 2026-08-18 20:41 ` Tom Rini
3 siblings, 0 replies; 5+ messages in thread
From: Tom Rini @ 2026-08-18 20:41 UTC (permalink / raw)
To: Gokul Praveen; +Cc: n-francis, u-boot
[-- Attachment #1: Type: text/plain, Size: 1060 bytes --]
On Tue, Aug 18, 2026 at 05:23:19PM +0530, Gokul Praveen wrote:
> No-SPL Mode is a boot approach that bypasses
> the A72 SPL while retaining U-Boot in the boot flow.
> This mode provides faster boot times compared to normal boot
> while maintaining U-Boot's flexibility for kernel loading
> and system configuration..
>
> v2<==> v1
> ===========
> * Updated the naming convention used from "semi-falcon" to "no-spl".
> * Link to v1: https://lore.kernel.org/all/20260814102153.44487-1-g-praveen@ti.com/
>
> Boot logs link :
> https://gist.github.com/GokulPraveen2001/fef407a482e2dad30272006de557627c
Content-wise, this is fine. Naming wise, in v1 you explained that "No
SPL" (as I partly suggested) isn't right, because it's just the Cortex-A
SPL stage being skipped. So please, work on figuring out a better name
for this flow internally. Or be sure that everyone is really happy with
"no spl" being the name for the flow where you're skipping SPL on the
Cortex-A side, but still having it on the Cortex-R side. Thanks.
--
Tom
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^ permalink raw reply [flat|nested] 5+ messages in thread