From: Brian Cain <brian.cain@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: Laurent Vivier <laurent@vivier.eu>,
Brian Cain <brian.cain@oss.qualcomm.com>,
Helge Deller <deller@gmx.de>,
Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Subject: [PATCH 02/11] tests/tcg/hexagon: check priv instructions raise SIGILL
Date: Tue, 18 Aug 2026 18:31:35 -0700 [thread overview]
Message-ID: <20260819013144.3264096-3-brian.cain@oss.qualcomm.com> (raw)
In-Reply-To: <20260819013144.3264096-1-brian.cain@oss.qualcomm.com>
A_PRIV and A_GUEST instructions executed from user mode raise
HEX_CAUSE_PRIV_USER_NO_SINSN and HEX_CAUSE_PRIV_USER_NO_GINSN, which aborted
qemu-hexagon until the preceding patch.
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
tests/tcg/hexagon/privileged-insn.c | 79 +++++++++++++++++++++++++++++
tests/tcg/hexagon/Makefile.target | 1 +
2 files changed, 80 insertions(+)
create mode 100644 tests/tcg/hexagon/privileged-insn.c
diff --git a/tests/tcg/hexagon/privileged-insn.c b/tests/tcg/hexagon/privileged-insn.c
new file mode 100644
index 00000000000..306d4542ea4
--- /dev/null
+++ b/tests/tcg/hexagon/privileged-insn.c
@@ -0,0 +1,79 @@
+/*
+ * Test that privileged and guest-mode instructions raise SIGILL in user mode.
+ *
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <assert.h>
+#include <signal.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+static void *resume_pc;
+
+static void handle_sigill(int sig, siginfo_t *info, void *puc)
+{
+ ucontext_t *uc = (ucontext_t *)puc;
+
+ if (sig != SIGILL) {
+ _exit(EXIT_FAILURE);
+ }
+
+ uc->uc_mcontext.r0 = SIGILL;
+ uc->uc_mcontext.pc = (unsigned long)resume_pc;
+}
+
+static int test_priv_insn(void)
+{
+ int sig;
+
+ asm volatile(
+ "r0 = #0\n"
+ "r1 = ##1f\n"
+ "memw(%[pc]) = r1\n"
+ "stop(r0)\n"
+ "1:\n"
+ "%[sig] = r0\n"
+ : [sig] "=r"(sig)
+ : [pc] "r"(&resume_pc)
+ : "r0", "r1", "memory");
+
+ return sig;
+}
+
+static int test_guest_insn(void)
+{
+ int sig;
+
+ asm volatile(
+ "r0 = #0\n"
+ "r1 = ##1f\n"
+ "memw(%[pc]) = r1\n"
+ "r0 = g0\n"
+ "1:\n"
+ "%[sig] = r0\n"
+ : [sig] "=r"(sig)
+ : [pc] "r"(&resume_pc)
+ : "r0", "r1", "memory");
+
+ return sig;
+}
+
+int main()
+{
+ struct sigaction act;
+
+ memset(&act, 0, sizeof(act));
+ act.sa_sigaction = handle_sigill;
+ act.sa_flags = SA_SIGINFO;
+ assert(sigaction(SIGILL, &act, NULL) == 0);
+
+ assert(test_priv_insn() == SIGILL);
+ assert(test_guest_insn() == SIGILL);
+
+ puts("PASS");
+ return EXIT_SUCCESS;
+}
diff --git a/tests/tcg/hexagon/Makefile.target b/tests/tcg/hexagon/Makefile.target
index 61adf6356e4..641f6bc10e7 100644
--- a/tests/tcg/hexagon/Makefile.target
+++ b/tests/tcg/hexagon/Makefile.target
@@ -58,6 +58,7 @@ HEX_TESTS += invalid-slots
HEX_TESTS += valid-slots
HEX_TESTS += invalid-encoding
HEX_TESTS += multiple-writes
+HEX_TESTS += privileged-insn
HEX_TESTS += unaligned_pc
HEX_TESTS += unaligned_data
--
2.34.1
next prev parent reply other threads:[~2026-08-19 1:32 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-19 1:31 [PATCH 00/11] Hexagon: exception, interrupt, system reg fixes Brian Cain
2026-08-19 1:31 ` [PATCH 01/11] target/hexagon: align exceptions for user/sysemu Brian Cain
2026-08-20 18:40 ` Pierrick Bouvier
2026-08-20 19:02 ` Brian Cain
2026-08-20 19:32 ` Pierrick Bouvier
2026-08-21 16:37 ` Pierrick Bouvier
2026-08-22 15:46 ` Brian Cain
2026-08-19 1:31 ` Brian Cain [this message]
2026-08-20 18:41 ` [PATCH 02/11] tests/tcg/hexagon: check priv instructions raise SIGILL Pierrick Bouvier
2026-08-19 1:31 ` [PATCH 03/11] hw/intc: clear pending bit on l2vic de-assertion Brian Cain
2026-08-20 18:41 ` Pierrick Bouvier
2026-08-19 1:31 ` [PATCH 04/11] target/hexagon: guard writes to unimplemented guest registers Brian Cain
2026-08-20 18:44 ` Pierrick Bouvier
2026-08-22 15:59 ` Brian Cain
2026-08-19 1:31 ` [PATCH 05/11] target/hexagon: take BQL when reading the system pcycle count Brian Cain
2026-08-20 18:45 ` Pierrick Bouvier
2026-08-19 1:31 ` [PATCH 06/11] target/hexagon: gate GPCYCLE guest register reads on SSR:CE Brian Cain
2026-08-20 18:46 ` Pierrick Bouvier
2026-08-19 1:31 ` [PATCH 07/11] target/hexagon: read UTIMERLO/UTIMERHI from the global timer Brian Cain
2026-08-20 18:48 ` Pierrick Bouvier
2026-08-19 1:31 ` [PATCH 08/11] target/hexagon: raise imprecise exception on multi-TLB match Brian Cain
2026-08-20 18:54 ` Pierrick Bouvier
2026-08-19 1:31 ` [PATCH 09/11] target/hexagon: implement direct-to-guest interrupt delivery Brian Cain
2026-08-20 18:57 ` Pierrick Bouvier
2026-08-20 21:59 ` Brian Cain
2026-08-21 16:22 ` Pierrick Bouvier
2026-08-19 1:31 ` [PATCH 10/11] target/hexagon: fix iassign{r,w} to cover all threads Brian Cain
2026-08-20 18:59 ` Pierrick Bouvier
2026-08-19 1:31 ` [PATCH 11/11] tests/functional/hexagon: update to v0.2.12, +test_{interrupts, sys_regs} Brian Cain via qemu development
2026-08-20 18:59 ` [PATCH 11/11] tests/functional/hexagon: update to v0.2.12, +test_{interrupts,sys_regs} Pierrick Bouvier
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