From: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
To: Brian Cain <brian.cain@oss.qualcomm.com>, qemu-devel@nongnu.org
Cc: Laurent Vivier <laurent@vivier.eu>, Helge Deller <deller@gmx.de>
Subject: Re: [PATCH 02/11] tests/tcg/hexagon: check priv instructions raise SIGILL
Date: Thu, 20 Aug 2026 11:41:13 -0700 [thread overview]
Message-ID: <b4f29291-08dc-4281-bb87-de57dc607e52@oss.qualcomm.com> (raw)
In-Reply-To: <20260819013144.3264096-3-brian.cain@oss.qualcomm.com>
On 8/18/2026 6:31 PM, Brian Cain wrote:
> A_PRIV and A_GUEST instructions executed from user mode raise
> HEX_CAUSE_PRIV_USER_NO_SINSN and HEX_CAUSE_PRIV_USER_NO_GINSN, which aborted
> qemu-hexagon until the preceding patch.
>
> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
> ---
> tests/tcg/hexagon/privileged-insn.c | 79 +++++++++++++++++++++++++++++
> tests/tcg/hexagon/Makefile.target | 1 +
> 2 files changed, 80 insertions(+)
> create mode 100644 tests/tcg/hexagon/privileged-insn.c
>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
next prev parent reply other threads:[~2026-08-20 18:41 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-19 1:31 [PATCH 00/11] Hexagon: exception, interrupt, system reg fixes Brian Cain
2026-08-19 1:31 ` [PATCH 01/11] target/hexagon: align exceptions for user/sysemu Brian Cain
2026-08-20 18:40 ` Pierrick Bouvier
2026-08-20 19:02 ` Brian Cain
2026-08-20 19:32 ` Pierrick Bouvier
2026-08-19 1:31 ` [PATCH 02/11] tests/tcg/hexagon: check priv instructions raise SIGILL Brian Cain
2026-08-20 18:41 ` Pierrick Bouvier [this message]
2026-08-19 1:31 ` [PATCH 03/11] hw/intc: clear pending bit on l2vic de-assertion Brian Cain
2026-08-20 18:41 ` Pierrick Bouvier
2026-08-19 1:31 ` [PATCH 04/11] target/hexagon: guard writes to unimplemented guest registers Brian Cain
2026-08-20 18:44 ` Pierrick Bouvier
2026-08-19 1:31 ` [PATCH 05/11] target/hexagon: take BQL when reading the system pcycle count Brian Cain
2026-08-20 18:45 ` Pierrick Bouvier
2026-08-19 1:31 ` [PATCH 06/11] target/hexagon: gate GPCYCLE guest register reads on SSR:CE Brian Cain
2026-08-20 18:46 ` Pierrick Bouvier
2026-08-19 1:31 ` [PATCH 07/11] target/hexagon: read UTIMERLO/UTIMERHI from the global timer Brian Cain
2026-08-20 18:48 ` Pierrick Bouvier
2026-08-19 1:31 ` [PATCH 08/11] target/hexagon: raise imprecise exception on multi-TLB match Brian Cain
2026-08-20 18:54 ` Pierrick Bouvier
2026-08-19 1:31 ` [PATCH 09/11] target/hexagon: implement direct-to-guest interrupt delivery Brian Cain
2026-08-20 18:57 ` Pierrick Bouvier
2026-08-20 21:59 ` Brian Cain
2026-08-19 1:31 ` [PATCH 10/11] target/hexagon: fix iassign{r,w} to cover all threads Brian Cain
2026-08-20 18:59 ` Pierrick Bouvier
2026-08-19 1:31 ` [PATCH 11/11] tests/functional/hexagon: update to v0.2.12, +test_{interrupts, sys_regs} Brian Cain via qemu development
2026-08-20 18:59 ` [PATCH 11/11] tests/functional/hexagon: update to v0.2.12, +test_{interrupts,sys_regs} Pierrick Bouvier
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