* [PATCH 2/4] ddr: imx: Move error message for failed training to calling side
2026-08-19 6:57 [PATCH 1/4] ddr: imx: Reload the training firmware for every PHY configuration Frieder Schrempf
@ 2026-08-19 6:57 ` Frieder Schrempf
2026-08-19 6:58 ` [PATCH 3/4] ddr: imx: Allow to call ddr init without logging failure Frieder Schrempf
2026-08-19 6:58 ` [PATCH 4/4] imx: kontron-sl-mx8mm: Stop printing error message on first DDR init Frieder Schrempf
2 siblings, 0 replies; 5+ messages in thread
From: Frieder Schrempf @ 2026-08-19 6:57 UTC (permalink / raw)
To: Stefano Babic, Fabio Estevam, Tom Rini, u-boot
Cc: uboot-imx, Frieder Schrempf
From: Frieder Schrempf <frieder.schrempf@kontron.de>
Move the error message from wait_ddrphy_training_complete() to the
calling site in ddr_cfg_phy(). This is more robust to future changes
in wait_ddrphy_training_complete() and allows us to make the message
optional.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
---
drivers/ddr/imx/phy/ddrphy_train.c | 4 +++-
drivers/ddr/imx/phy/ddrphy_utils.c | 1 -
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/ddr/imx/phy/ddrphy_train.c b/drivers/ddr/imx/phy/ddrphy_train.c
index 63a6ca800a3..68468610fd6 100644
--- a/drivers/ddr/imx/phy/ddrphy_train.c
+++ b/drivers/ddr/imx/phy/ddrphy_train.c
@@ -72,8 +72,10 @@ int ddr_cfg_phy(struct dram_timing_info *dram_timing)
/* Wait for the training firmware to complete */
ret = wait_ddrphy_training_complete();
- if (ret)
+ if (ret) {
+ printf("Training FAILED\n");
return ret;
+ }
/* Halt the microcontroller. */
dwc_ddrphy_apb_wr(0xd0099, 0x1);
diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c b/drivers/ddr/imx/phy/ddrphy_utils.c
index 8e350de8315..8779db01607 100644
--- a/drivers/ddr/imx/phy/ddrphy_utils.c
+++ b/drivers/ddr/imx/phy/ddrphy_utils.c
@@ -97,7 +97,6 @@ int wait_ddrphy_training_complete(void)
debug("Training PASS\n");
return 0;
} else if (mail == 0xff) {
- printf("Training FAILED\n");
return -1;
}
}
--
2.55.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 3/4] ddr: imx: Allow to call ddr init without logging failure
2026-08-19 6:57 [PATCH 1/4] ddr: imx: Reload the training firmware for every PHY configuration Frieder Schrempf
2026-08-19 6:57 ` [PATCH 2/4] ddr: imx: Move error message for failed training to calling side Frieder Schrempf
@ 2026-08-19 6:58 ` Frieder Schrempf
2026-08-19 10:03 ` Marek Vasut
2026-08-19 6:58 ` [PATCH 4/4] imx: kontron-sl-mx8mm: Stop printing error message on first DDR init Frieder Schrempf
2 siblings, 1 reply; 5+ messages in thread
From: Frieder Schrempf @ 2026-08-19 6:58 UTC (permalink / raw)
To: Stefano Babic, Fabio Estevam, Ilias Apalodimas, Tom Rini, u-boot
Cc: uboot-imx, Frieder Schrempf, Marek Vasut, Simona Toaca
From: Frieder Schrempf <frieder.schrempf@kontron.de>
In some cases we need to call ddr_init() multiple times to try
different configurations. In this case failures are expected and
error messages cause confusion. Introduce ddr_init_silent_fail()
for those cases.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
---
arch/arm/include/asm/arch-imx8m/ddr.h | 4 +++-
arch/arm/include/asm/arch-imx9/ddr.h | 4 +++-
drivers/ddr/imx/imx8m/ddr_init.c | 14 ++++++++++++--
drivers/ddr/imx/imx9/ddr_init.c | 14 ++++++++++++--
drivers/ddr/imx/phy/ddrphy_train.c | 5 +++--
5 files changed, 33 insertions(+), 8 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h
index 5092ccae188..442c45237f9 100644
--- a/arch/arm/include/asm/arch-imx8m/ddr.h
+++ b/arch/arm/include/asm/arch-imx8m/ddr.h
@@ -9,6 +9,7 @@
#include <asm/io.h>
#include <asm/types.h>
#include <asm/arch/imx-regs.h>
+#include <linux/types.h>
#define DDRC_DDR_SS_GPR0 0x3d000000
#define DDRC_IPS_BASE_ADDR_0 0x3f400000
@@ -705,8 +706,9 @@ struct dram_timing_info {
extern struct dram_timing_info dram_timing;
void ddr_load_train_firmware(enum fw_type type);
+int ddr_init_silent_fail(struct dram_timing_info *timing_info);
int ddr_init(struct dram_timing_info *timing_info);
-int ddr_cfg_phy(struct dram_timing_info *timing_info);
+int ddr_cfg_phy(struct dram_timing_info *timing_info, bool log_fail);
void load_lpddr4_phy_pie(void);
void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num);
void *dram_config_save(struct dram_timing_info *info, unsigned long base);
diff --git a/arch/arm/include/asm/arch-imx9/ddr.h b/arch/arm/include/asm/arch-imx9/ddr.h
index b0f90b53f64..c85f4cc7810 100644
--- a/arch/arm/include/asm/arch-imx9/ddr.h
+++ b/arch/arm/include/asm/arch-imx9/ddr.h
@@ -8,6 +8,7 @@
#include <asm/io.h>
#include <asm/types.h>
+#include <linux/types.h>
#define DDR_CTL_BASE 0x4E300000
#define DDR_PHY_BASE 0x4E100000
@@ -147,8 +148,9 @@ struct ddrphy_qb_state {
};
void ddr_load_train_firmware(enum fw_type type);
+int ddr_init_silent_fail(struct dram_timing_info *timing_info);
int ddr_init(struct dram_timing_info *timing_info);
-int ddr_cfg_phy(struct dram_timing_info *timing_info);
+int ddr_cfg_phy(struct dram_timing_info *timing_info, bool log_fail);
void load_lpddr4_phy_pie(void);
void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num);
void *dram_config_save(struct dram_timing_info *info, unsigned long base);
diff --git a/drivers/ddr/imx/imx8m/ddr_init.c b/drivers/ddr/imx/imx8m/ddr_init.c
index e9209ce8b61..537c36acc8d 100644
--- a/drivers/ddr/imx/imx8m/ddr_init.c
+++ b/drivers/ddr/imx/imx8m/ddr_init.c
@@ -310,7 +310,7 @@ void update_umctl2_rank_space_setting(unsigned int pstat_num)
}
}
-int ddr_init(struct dram_timing_info *dram_timing)
+static int __ddr_init(struct dram_timing_info *dram_timing, bool log_fail)
{
unsigned int tmp, initial_drate, target_freq;
int ret;
@@ -390,7 +390,7 @@ int ddr_init(struct dram_timing_info *dram_timing)
*/
debug("DDRINFO:ddrphy config start\n");
- ret = ddr_cfg_phy(dram_timing);
+ ret = ddr_cfg_phy(dram_timing, log_fail);
if (ret)
return ret;
@@ -470,6 +470,16 @@ int ddr_init(struct dram_timing_info *dram_timing)
return 0;
}
+int ddr_init(struct dram_timing_info *dram_timing)
+{
+ return __ddr_init(dram_timing, true);
+}
+
+int ddr_init_silent_fail(struct dram_timing_info *dram_timing)
+{
+ return __ddr_init(dram_timing, false);
+}
+
ulong ddrphy_addr_remap(uint32_t paddr_apb_from_ctlr)
{
return 4 * paddr_apb_from_ctlr;
diff --git a/drivers/ddr/imx/imx9/ddr_init.c b/drivers/ddr/imx/imx9/ddr_init.c
index 5b0ad773875..f2600c65703 100644
--- a/drivers/ddr/imx/imx9/ddr_init.c
+++ b/drivers/ddr/imx/imx9/ddr_init.c
@@ -335,7 +335,7 @@ void save_trained_mr12_14(struct dram_cfg_param *cfg, u32 cfg_num, u32 mr12, u32
}
}
-int ddr_init(struct dram_timing_info *dram_timing)
+static int __ddr_init(struct dram_timing_info *dram_timing, bool log_fail)
{
unsigned int initial_drate;
struct dram_timing_info *saved_timing;
@@ -361,7 +361,7 @@ int ddr_init(struct dram_timing_info *dram_timing)
*/
debug("DDRINFO:ddrphy config start\n");
- ret = ddr_cfg_phy(dram_timing);
+ ret = ddr_cfg_phy(dram_timing, log_fail);
if (ret)
return ret;
@@ -412,6 +412,16 @@ int ddr_init(struct dram_timing_info *dram_timing)
return 0;
}
+int ddr_init(struct dram_timing_info *dram_timing)
+{
+ return __ddr_init(dram_timing, true);
+}
+
+int ddr_init_silent_fail(struct dram_timing_info *dram_timing)
+{
+ return __ddr_init(dram_timing, false);
+}
+
ulong ddrphy_addr_remap(u32 paddr_apb_from_ctlr)
{
u32 paddr_apb_qual;
diff --git a/drivers/ddr/imx/phy/ddrphy_train.c b/drivers/ddr/imx/phy/ddrphy_train.c
index 68468610fd6..770a568d8f2 100644
--- a/drivers/ddr/imx/phy/ddrphy_train.c
+++ b/drivers/ddr/imx/phy/ddrphy_train.c
@@ -8,7 +8,7 @@
#include <asm/arch/ddr.h>
#include <asm/arch/sys_proto.h>
-int ddr_cfg_phy(struct dram_timing_info *dram_timing)
+int ddr_cfg_phy(struct dram_timing_info *dram_timing, bool log_fail)
{
struct dram_cfg_param *dram_cfg;
struct dram_fsp_msg *fsp_msg;
@@ -73,7 +73,8 @@ int ddr_cfg_phy(struct dram_timing_info *dram_timing)
/* Wait for the training firmware to complete */
ret = wait_ddrphy_training_complete();
if (ret) {
- printf("Training FAILED\n");
+ if (log_fail || _DEBUG)
+ printf("Training FAILED\n");
return ret;
}
--
2.55.0
^ permalink raw reply related [flat|nested] 5+ messages in thread