Re: [PATCH v3 1/4] arm64: dts: qcom: monaco: Add compatible to the PCIe Root Port

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] This problem wasn't introduced by this patch, but the patch provides an incomplete fix. It adds `compatible = "pciclass,0604";` to `pcieport0` to enable PCI-to-PCI bridge matching, but fails to apply the same required fix to the identical `pcieport1` node in the same file.
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--- Patch [1]: [PATCH v3 1/4] arm64: dts: qcom: monaco: Add compatible to the PCIe Root Port ---
commit aa27523e9b0a54b6db3c28da2c6526d7f13eeef7
Author: Wei Deng <wei.deng@oss.qualcomm.com>

arm64: dts: qcom: monaco: Add compatible to the PCIe Root Port

This patch adds the "pciclass,0604" compatible string to the pcieport0 node
in monaco.dtsi. This enables the PCI subsystem to properly associate the DT
node with the PCI-to-PCI bridge device, allowing downstream DT nodes to be
matched.

> diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
> index e4c8466f941bd..44526f4d85870 100644
> --- a/arch/arm64/boot/dts/qcom/monaco.dtsi
> +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
> @@ -2413,6 +2413,7 @@ opp-32000000 {
>  			};
>  
>  			pcieport0: pcie@0 {
> +				compatible = "pciclass,0604";
>  				device_type = "pci";
>  				reg = <0x0 0x0 0x0 0x0 0x0>;
>  				bus-range = <0x01 0xff>;

[Severity: High]
This isn't a bug introduced by this patch, but does this provide an incomplete
fix?

Looking further down in arch/arm64/boot/dts/qcom/monaco.dtsi, there is a
second PCIe Root Port that is missing this compatible string:

			pcieport1: pcie@0 {
				device_type = "pci";
				reg = <0x0 0x0 0x0 0x0 0x0>;
				bus-range = <0x01 0xff>;
				...

Without the "pciclass,0604" property here, the PCI subsystem cannot associate
the DT node for pcieport1 with the physical PCI-to-PCI bridge device. This
prevents downstream endpoints from being assigned their respective of_node,
breaking the binding of PCI power control drivers (e.g., pci-pwrctrl-pwrseq)
and leaving the devices unusable.

Should this compatible string be added to pcieport1 as well?

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Sashiko AI review · https://sashiko.dev/#/patchset/20260819-b4-monaco-evk-m2-v1-v3-0-988145ef65cd@oss.qualcomm.com?part=1