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From: "Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: qemu-s390x@nongnu.org, "Paolo Bonzini" <pbonzini@redhat.com>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	qemu-ppc@nongnu.org, qemu-riscv@nongnu.org,
	"Richard Henderson" <richard.henderson@linaro.org>,
	qemu-arm@nongnu.org,
	"Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"Weiwei Li" <liwei1518@gmail.com>,
	"Daniel Henrique Barboza" <daniel.barboza@oss.qualcomm.com>,
	"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
	"Chao Liu" <chao.liu@processmission.com>
Subject: [RFC PATCH 10/13] target/riscv: Constify CPURISCVState for various cpu_*() getters
Date: Thu, 20 Aug 2026 12:47:26 +0200	[thread overview]
Message-ID: <20260820104730.25462-11-philmd@oss.qualcomm.com> (raw)
In-Reply-To: <20260820104730.25462-1-philmd@oss.qualcomm.com>

Add the const qualifier to CPURISCVState when the
argument is accessed without modification.

Note we have to use the recently introduced
env_archcpu_const() helper in riscv_cpu_cfg().

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
 target/riscv/cpu.h | 12 ++++++------
 target/riscv/cpu.c |  8 ++++----
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 2333dcecd8a..9fd9ba54147 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -637,10 +637,10 @@ int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero);
 uint8_t riscv_cpu_default_priority(int irq);
 uint64_t riscv_cpu_all_pending(const CPURISCVState *env);
-int riscv_cpu_mirq_pending(CPURISCVState *env);
-int riscv_cpu_sirq_pending(CPURISCVState *env);
-int riscv_cpu_vsirq_pending(CPURISCVState *env);
-int riscv_cpu_pending_to_irq(CPURISCVState *env,
+int riscv_cpu_mirq_pending(const CPURISCVState *env);
+int riscv_cpu_sirq_pending(const CPURISCVState *env);
+int riscv_cpu_vsirq_pending(const CPURISCVState *env);
+int riscv_cpu_pending_to_irq(const CPURISCVState *env,
                              int extirq, unsigned int extirq_def_prio,
                              uint64_t pending, const uint8_t *iprio);
 
@@ -753,9 +753,9 @@ static inline RISCVMXL riscv_cpu_mxl(const CPURISCVState *env)
 #endif
 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env)))
 
-static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env)
+static inline const RISCVCPUConfig *riscv_cpu_cfg(const CPURISCVState *env)
 {
-    return &env_archcpu(env)->cfg;
+    return &env_archcpu_const(env)->cfg;
 }
 
 #if !defined(CONFIG_USER_ONLY)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a344daf62f8..ab2868dc1e2 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -864,7 +864,7 @@ uint8_t riscv_cpu_default_priority(int irq)
     return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO;
 };
 
-int riscv_cpu_pending_to_irq(CPURISCVState *env,
+int riscv_cpu_pending_to_irq(const CPURISCVState *env,
                              int extirq, unsigned int extirq_def_prio,
                              uint64_t pending, const uint8_t *iprio)
 {
@@ -917,7 +917,7 @@ uint64_t riscv_cpu_all_pending(const CPURISCVState *env)
     return (env->mip | vsgein | vstip) & env->mie;
 }
 
-int riscv_cpu_mirq_pending(CPURISCVState *env)
+int riscv_cpu_mirq_pending(const CPURISCVState *env)
 {
     uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg &
                     ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
@@ -926,7 +926,7 @@ int riscv_cpu_mirq_pending(CPURISCVState *env)
                                     irqs, env->miprio);
 }
 
-int riscv_cpu_sirq_pending(CPURISCVState *env)
+int riscv_cpu_sirq_pending(const CPURISCVState *env)
 {
     uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & ~env->hideleg;
     uint64_t irqs_f = env->mvip & env->mvien & ~env->mideleg & env->sie;
@@ -935,7 +935,7 @@ int riscv_cpu_sirq_pending(CPURISCVState *env)
                                     irqs | irqs_f, env->siprio);
 }
 
-int riscv_cpu_vsirq_pending(CPURISCVState *env)
+int riscv_cpu_vsirq_pending(const CPURISCVState *env)
 {
     uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & env->hideleg;
     uint64_t irqs_f_vs = env->hvip & env->hvien & ~env->hideleg & env->vsie;
-- 
2.53.0



  parent reply	other threads:[~2026-08-20 10:49 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-20 10:47 [PATCH 00/13] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
2026-08-20 10:47 ` [PATCH 01/13] target/avr: Constify CPUAVRState for some cpu_*() getters Philippe Mathieu-Daudé
2026-08-20 12:36   ` marcandre.lureau
2026-08-20 10:47 ` [PATCH 02/13] target/i386: Constify CPU*State for cpu_*_interrupt() getters Philippe Mathieu-Daudé
2026-08-20 12:36   ` marcandre.lureau
2026-08-20 10:47 ` [PATCH 03/13] target/loongarch: Constify CPULoongArchState for various cpu_*() getters Philippe Mathieu-Daudé
2026-08-20 12:36   ` marcandre.lureau
2026-08-20 10:47 ` [PATCH 04/13] target/mips: Constify CPUMIPSState " Philippe Mathieu-Daudé
2026-08-20 12:36   ` marcandre.lureau
2026-08-20 10:47 ` [PATCH 05/13] target/s390x: Constify S390CPU for cpu_has_*() getters Philippe Mathieu-Daudé
2026-08-20 11:06   ` Ilya Leoshkevich
2026-08-20 12:36   ` marcandre.lureau
2026-08-20 19:22   ` Eric Farman
2026-08-20 10:47 ` [PATCH 06/13] target/riscv: Constify @iprio argument in riscv_cpu_pending_to_irq() Philippe Mathieu-Daudé
2026-08-20 13:22   ` marcandre.lureau
2026-08-20 10:47 ` [PATCH 07/13] target/riscv: Constify CPURISCVState for various cpu_*() getters Philippe Mathieu-Daudé
2026-08-20 13:22   ` marcandre.lureau
2026-08-20 10:47 ` [PATCH 08/13] target/sparc: Constify CPUSPARCState " Philippe Mathieu-Daudé
2026-08-20 13:22   ` marcandre.lureau
2026-08-20 10:47 ` [RFC PATCH 09/13] cpus: Add const-qualified CPU environment accessors Philippe Mathieu-Daudé
2026-08-20 13:22   ` marcandre.lureau
2026-08-20 15:21   ` Richard Henderson
2026-08-20 16:24     ` Philippe Mathieu-Daudé
2026-08-20 16:50       ` Philippe Mathieu-Daudé
2026-08-20 17:09         ` Marc-André Lureau
2026-08-20 10:47 ` Philippe Mathieu-Daudé [this message]
2026-08-20 13:22   ` [RFC PATCH 10/13] target/riscv: Constify CPURISCVState for various cpu_*() getters marcandre.lureau
2026-08-20 10:47 ` [RFC PATCH 11/13] target/hexagon: Constify CPUHexagonState in hexagon_thread_is_enabled() Philippe Mathieu-Daudé
2026-08-20 13:22   ` marcandre.lureau
2026-08-20 15:28   ` Brian Cain
2026-08-20 10:47 ` [RFC PATCH 12/13] target/mips: Constify CPUMIPSState in mips_vpe_active() Philippe Mathieu-Daudé
2026-08-20 13:22   ` marcandre.lureau
2026-08-20 10:47 ` [RFC PATCH 13/13] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
2026-08-20 11:05   ` Philippe Mathieu-Daudé
2026-08-20 13:22   ` marcandre.lureau
2026-08-20 13:55     ` Philippe Mathieu-Daudé

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