[PATCH] PCI/ASPM: Clear L1SS capability when L1 latency is unacceptable

[PATCH] PCI/ASPM: Clear L1SS capability when L1 latency is unacceptable

[Aniket]

From: Aniket Maurya <aniketmaurya@google.com>

pcie_aspm_cap_init() initializes link->aspm_capable from
link->aspm_support, which includes PCIE_LINK_STATE_L1SS (L1.1, L1.2, etc.)
if supported by both ends of the link.

pcie_aspm_check_latency() then evaluates whether the exit latency of the
link exceeds the acceptable L1 latency advertised by downstream endpoints.
If the latency is unacceptable, it clears PCIE_LINK_STATE_L1 from
link->aspm_capable. However, it does not clear PCIE_LINK_STATE_L1SS.

L1 PM Substates are substates of L1 and require
L1 to be supported and enabled. If L1 is not capable due to unacceptable
exit latency, L1 PM Substates cannot be supported either.

Leaving PCIE_LINK_STATE_L1SS set in link->aspm_capable when L1 is not
capable causes:
1) aspm_ctrl_attrs_are_visible() to expose L1SS sysfs control files
   (e.g., l1_1_aspm, l1_2_aspm) even though the link cannot use L1/L1SS.
2) pcie_config_aspm_link() to unnecessarily invoke pcie_config_aspm_l1ss()
   during ASPM configuration.

Clear PCIE_LINK_STATE_L1SS along with PCIE_LINK_STATE_L1 from
link->aspm_capable when L1 exit latency is unacceptable.

Signed-off-by: Aniket <aniketmaurya@google.com>
---
 drivers/pci/pcie/aspm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index 172783e7f519..38eb7b1e2377 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -666,7 +666,8 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
 		latency = max_t(u32, latency_up_l1, latency_dw_l1);
 		if ((link->aspm_capable & PCIE_LINK_STATE_L1) &&
 		    (latency + l1_switch_latency > acceptable_l1))
-			link->aspm_capable &= ~PCIE_LINK_STATE_L1;
+			link->aspm_capable &= ~(PCIE_LINK_STATE_L1 |
+						PCIE_LINK_STATE_L1SS);
 		l1_switch_latency += NSEC_PER_USEC;
 
 		link = link->parent;
-- 
2.55.0.766.g2966f0265a-goog

Re: [PATCH] PCI/ASPM: Clear L1SS capability when L1 latency is unacceptable

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Hardware State Desynchronization: Clearing PCIE_LINK_STATE_L1SS from `link->aspm_capable` prevents the kernel from properly disabling L1 PM Substates in hardware configuration registers.
--

--- Patch [1]: [PATCH] PCI/ASPM: Clear L1SS capability when L1 latency is unacceptable ---
commit b94fabc7c75525f540a542b9992482d82ee2ac83
Author: Aniket Maurya <aniketmaurya@google.com>

PCI/ASPM: Clear L1SS capability when L1 latency is unacceptable

This commit clears PCIE_LINK_STATE_L1SS from link->aspm_capable when L1
exit latency is unacceptable. This prevents L1SS sysfs control files from
being exposed and avoids invoking pcie_config_aspm_l1ss() unnecessarily.

> diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
> index 172783e7f519a..38eb7b1e23774 100644
> --- a/drivers/pci/pcie/aspm.c
> +++ b/drivers/pci/pcie/aspm.c
> @@ -666,7 +666,8 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
>  		latency = max_t(u32, latency_up_l1, latency_dw_l1);
>  		if ((link->aspm_capable & PCIE_LINK_STATE_L1) &&
>  		    (latency + l1_switch_latency > acceptable_l1))
> -			link->aspm_capable &= ~PCIE_LINK_STATE_L1;
> +			link->aspm_capable &= ~(PCIE_LINK_STATE_L1 |
> +						PCIE_LINK_STATE_L1SS);

[Severity: High]
Does clearing PCIE_LINK_STATE_L1SS here prevent the kernel from disabling
L1 PM Substates in the hardware configuration registers if the BIOS left
them enabled?

When pcie_config_aspm_link() runs later to apply the state, it checks this
exact capability before performing the cleanup:

pcie_config_aspm_link() {
    ...
    if (link->aspm_capable & PCIE_LINK_STATE_L1SS)
        pcie_config_aspm_l1ss(link, state);
    ...
}

Because the capability was stripped earlier in pcie_aspm_check_latency(),
this condition evaluates to false. Will this bypass the hardware cleanup
routine, leaving stale BIOS configurations active and causing L1 to be
disabled while L1SS remains enabled in hardware?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260821103214.2049218-1-aniketmaurya@google.com?part=1

Re: [PATCH] PCI/ASPM: Clear L1SS capability when L1 latency is unacceptable

[Aniket .]

> Because the capability was stripped earlier in pcie_aspm_check_latency(),
> this condition evaluates to false. Will this bypass the hardware cleanup
> routine, leaving stale BIOS configurations active and causing L1 to be
> disabled while L1SS remains enabled in hardware?

Yeah this might lead to inconsistent states between the L1SS hardware
register and the software variable. Fixing this in v2.