[PATCH 0/3] Modify the SW tail logic in OA

All of lore.kernel.org
 help / color / mirror / Atom feed

* [PATCH 0/3] Modify the SW tail logic in OA
@ 2026-08-21 20:07 Umesh Nerlige Ramappa
  2026-08-21 20:07 ` [PATCH 1/3] drm/xe/xe_oa: Clear status only if relevant bits are set Umesh Nerlige Ramappa
                   ` (5 more replies)
  0 siblings, 6 replies; 19+ messages in thread
From: Umesh Nerlige Ramappa @ 2026-08-21 20:07 UTC (permalink / raw)
  To: intel-xe, Ashutosh Dixit

OA unit updates the HW TAIL register to indicate that a new report is
available, although it does not guarantee that the report is visible in
memory. Also the currently running workload contributes to some latency
in seeing this report in memory. In the past we would set some fields in
the OA report and check if the fields are populated to non-zero values
by the HW, but this is no longer sufficient since some parts of the
report may land out of order under heavy workloads. Drop this WA and add
a new logic that just waits for a fixed number of HW TAIL report
increments before returning data to the user. User will always see the
reports lagging by this fixed number, however we do not have realtime
use cases for OAG since OAG reports are mainly post processed.

v2: Rebase
v3: Add Sashiko's review comments
v4: Rebase, checkpatch fixes
v5: Add Ashutosh's review comments

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Umesh Nerlige Ramappa (3):
  drm/xe/xe_oa: Clear status only if relevant bits are set
  drm/xe/xe_oa: Avoid checking and setting fields in the OA report
  drm/xe/xe_oa: Add a lag to the reports that is exported to user

 drivers/gpu/drm/xe/xe_oa.c | 99 ++++++--------------------------------
 1 file changed, 16 insertions(+), 83 deletions(-)

-- 
2.51.0

^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH 1/3] drm/xe/xe_oa: Clear status only if relevant bits are set
  2026-08-21 20:07 [PATCH 0/3] Modify the SW tail logic in OA Umesh Nerlige Ramappa
@ 2026-08-21 20:07 ` Umesh Nerlige Ramappa
  2026-08-21 20:07 ` [PATCH 2/3] drm/xe/xe_oa: Avoid checking and setting fields in the OA report Umesh Nerlige Ramappa
                   ` (4 subsequent siblings)
  5 siblings, 0 replies; 19+ messages in thread
From: Umesh Nerlige Ramappa @ 2026-08-21 20:07 UTC (permalink / raw)
  To: intel-xe, Ashutosh Dixit

OA monitors only a few bits in the status field. The current
read-modify-write will write to the MMIO even if none of the relevant
bits are set. Clear the status only if relevant bits are set.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
v2: Move comment (Ashutosh)
---
 drivers/gpu/drm/xe/xe_oa.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
index b460fcdfca15..024940478c06 100644
--- a/drivers/gpu/drm/xe/xe_oa.c
+++ b/drivers/gpu/drm/xe/xe_oa.c
@@ -542,15 +542,17 @@ static int xe_oa_wait_unlocked(struct xe_oa_stream *stream)
 static int __xe_oa_read(struct xe_oa_stream *stream, char __user *buf,
 			size_t count, size_t *offset)
 {
-	/* Only clear our bits to avoid side-effects */
-	stream->oa_status = xe_mmio_rmw32(&stream->gt->mmio, __oa_regs(stream)->oa_status,
-					  OASTATUS_RELEVANT_BITS, 0);
+	stream->oa_status = xe_mmio_read32(&stream->gt->mmio, __oa_regs(stream)->oa_status);
 	/*
 	 * Signal to userspace that there is non-zero OA status to read via
 	 * @DRM_XE_OBSERVATION_IOCTL_STATUS observation stream fd ioctl
 	 */
-	if (stream->oa_status & OASTATUS_RELEVANT_BITS)
+	if (stream->oa_status & OASTATUS_RELEVANT_BITS) {
+		/* Only clear our bits to avoid side-effects */
+		xe_mmio_write32(&stream->gt->mmio, __oa_regs(stream)->oa_status,
+				stream->oa_status & ~OASTATUS_RELEVANT_BITS);
 		return -EIO;
+	}
 
 	return xe_oa_append_reports(stream, buf, count, offset);
 }
-- 
2.51.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH 2/3] drm/xe/xe_oa: Avoid checking and setting fields in the OA report
  2026-08-21 20:07 [PATCH 0/3] Modify the SW tail logic in OA Umesh Nerlige Ramappa
  2026-08-21 20:07 ` [PATCH 1/3] drm/xe/xe_oa: Clear status only if relevant bits are set Umesh Nerlige Ramappa
@ 2026-08-21 20:07 ` Umesh Nerlige Ramappa
  2026-08-21 20:24   ` sashiko-bot
  2026-08-21 20:07 ` [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user Umesh Nerlige Ramappa
                   ` (3 subsequent siblings)
  5 siblings, 1 reply; 19+ messages in thread
From: Umesh Nerlige Ramappa @ 2026-08-21 20:07 UTC (permalink / raw)
  To: intel-xe, Ashutosh Dixit

OA unit updates the HW TAIL register to indicate that a new report is
available, although it does not guarantee that the report is visible in
memory. Also the currently running workload contributes to some latency
in seeing this report in memory. In the past we would set some fields in
the OA report and check if the fields are populated to non-zero values
by the HW, but this is no longer sufficient since some parts of the
report may land out of order under heavy workloads. Drop this WA and add
a new logic in subsequent patches to return updated reports to the user.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 drivers/gpu/drm/xe/xe_oa.c | 79 +-------------------------------------
 1 file changed, 2 insertions(+), 77 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
index 024940478c06..d7647f37ab02 100644
--- a/drivers/gpu/drm/xe/xe_oa.c
+++ b/drivers/gpu/drm/xe/xe_oa.c
@@ -216,42 +216,6 @@ static u32 xe_oa_hw_tail_read(struct xe_oa_stream *stream)
 #define oa_report_header_64bit(__s) \
 	((__s)->oa_buffer.format->header == HDR_64_BIT)
 
-static u64 oa_report_id(struct xe_oa_stream *stream, u32 report_offset)
-{
-	struct iosys_map *map = &stream->oa_buffer.bo->vmap;
-
-	return oa_report_header_64bit(stream) ?
-		xe_map_rd(stream->oa->xe, map, report_offset, u64) :
-		xe_map_rd(stream->oa->xe, map, report_offset, u32);
-}
-
-static void oa_report_id_clear(struct xe_oa_stream *stream, u32 report_offset)
-{
-	struct iosys_map *map = &stream->oa_buffer.bo->vmap;
-
-	oa_report_header_64bit(stream) ?
-		xe_map_wr(stream->oa->xe, map, report_offset, u64, 0) :
-		xe_map_wr(stream->oa->xe, map, report_offset, u32, 0);
-}
-
-static u64 oa_timestamp(struct xe_oa_stream *stream, u32 report_offset)
-{
-	struct iosys_map *map = &stream->oa_buffer.bo->vmap;
-
-	return oa_report_header_64bit(stream) ?
-		xe_map_rd(stream->oa->xe, map, report_offset + 8, u64) :
-		xe_map_rd(stream->oa->xe, map, report_offset + 4, u32);
-}
-
-static void oa_timestamp_clear(struct xe_oa_stream *stream, u32 report_offset)
-{
-	struct iosys_map *map = &stream->oa_buffer.bo->vmap;
-
-	oa_report_header_64bit(stream) ?
-		xe_map_wr(stream->oa->xe, map, report_offset + 8, u64, 0) :
-		xe_map_wr(stream->oa->xe, map, report_offset + 4, u32, 0);
-}
-
 static bool mert_wa_14026633728(struct xe_oa_stream *s)
 {
 	return s->oa_unit->type == DRM_XE_OA_UNIT_TYPE_MERT && XE_DEVICE_WA(s->oa->xe, 14026633728);
@@ -260,7 +224,7 @@ static bool mert_wa_14026633728(struct xe_oa_stream *s)
 static bool xe_oa_buffer_check_unlocked(struct xe_oa_stream *stream)
 {
 	u32 gtt_offset = xe_bo_ggtt_addr(stream->oa_buffer.bo);
-	u32 tail, hw_tail, partial_report_size, available;
+	u32 hw_tail, partial_report_size, available;
 	int report_size = stream->oa_buffer.format->size;
 	unsigned long flags;
 
@@ -280,29 +244,7 @@ static bool xe_oa_buffer_check_unlocked(struct xe_oa_stream *stream)
 	/* Subtract partial amount off the tail */
 	hw_tail = xe_oa_circ_diff(stream, hw_tail, partial_report_size);
 
-	tail = hw_tail;
-
-	/*
-	 * Walk the stream backward until we find a report with report id and timestamp
-	 * not 0. We can't tell whether a report has fully landed in memory before the
-	 * report id and timestamp of the following report have landed.
-	 *
-	 * This is assuming that the writes of the OA unit land in memory in the order
-	 * they were written.  If not : (╯°□°）╯︵ ┻━┻
-	 */
-	while (xe_oa_circ_diff(stream, tail, stream->oa_buffer.tail) >= report_size) {
-		if (oa_report_id(stream, tail) || oa_timestamp(stream, tail))
-			break;
-
-		tail = xe_oa_circ_diff(stream, tail, report_size);
-	}
-
-	if (xe_oa_circ_diff(stream, hw_tail, tail) > report_size)
-		drm_dbg(&stream->oa->xe->drm,
-			"unlanded report(s) head=0x%x tail=0x%x hw_tail=0x%x\n",
-			stream->oa_buffer.head, tail, hw_tail);
-
-	stream->oa_buffer.tail = tail;
+	stream->oa_buffer.tail = hw_tail;
 
 	available = xe_oa_circ_diff(stream, stream->oa_buffer.tail, stream->oa_buffer.head);
 	stream->pollin = available >= stream->wait_num_reports * report_size;
@@ -387,23 +329,6 @@ static int xe_oa_append_reports(struct xe_oa_stream *stream, char __user *buf,
 		ret = xe_oa_append_report(stream, buf, count, offset, head);
 		if (ret)
 			break;
-
-		if (!(stream->oa_buffer.circ_size % report_size)) {
-			/* Clear out report id and timestamp to detect unlanded reports */
-			oa_report_id_clear(stream, head);
-			oa_timestamp_clear(stream, head);
-		} else {
-			struct iosys_map *map = &stream->oa_buffer.bo->vmap;
-			u32 part = stream->oa_buffer.circ_size - head;
-
-			/* Zero out the entire report */
-			if (report_size <= part) {
-				xe_map_memset(stream->oa->xe, map, head, 0, report_size);
-			} else {
-				xe_map_memset(stream->oa->xe, map, head, 0, part);
-				xe_map_memset(stream->oa->xe, map, 0, 0, report_size - part);
-			}
-		}
 	}
 
 	if (start_offset != *offset) {
-- 
2.51.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* Re: [PATCH 2/3] drm/xe/xe_oa: Avoid checking and setting fields in the OA report
  2026-08-21 20:07 ` [PATCH 2/3] drm/xe/xe_oa: Avoid checking and setting fields in the OA report Umesh Nerlige Ramappa
@ 2026-08-21 20:24   ` sashiko-bot
  0 siblings, 0 replies; 19+ messages in thread
From: sashiko-bot @ 2026-08-21 20:24 UTC (permalink / raw)
  To: Umesh Nerlige Ramappa; +Cc: intel-xe

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The macro `oa_report_header_64bit` becomes unused and is left as dead code.
--

--- Patch [2]: [PATCH 2/3] drm/xe/xe_oa: Avoid checking and setting fields in the OA report ---
commit 834ec77b5bb816bced6887fd353db954dc30486c
Author: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

drm/xe/xe_oa: Avoid checking and setting fields in the OA report

This commit removes the workaround that checked and cleared specific fields
in the OA report buffer, as reports can now land out of order. Future patches
will introduce new logic to handle updated reports.

> diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
> index 2e4a89ebf737a..020b27c642268 100644
> --- a/drivers/gpu/drm/xe/xe_oa.c
> +++ b/drivers/gpu/drm/xe/xe_oa.c
> @@ -216,42 +216,6 @@ static u32 xe_oa_hw_tail_read(struct xe_oa_stream *stream)
>  #define oa_report_header_64bit(__s) \
>  	((__s)->oa_buffer.format->header == HDR_64_BIT)

[Severity: Low]
This isn't a bug, but since oa_report_id(), oa_report_id_clear(),
oa_timestamp(), and oa_timestamp_clear() were removed by this patch, does
this leave the oa_report_header_64bit() macro unused?

> -static u64 oa_report_id(struct xe_oa_stream *stream, u32 report_offset)
> -{
> -	struct iosys_map *map = &stream->oa_buffer.bo->vmap;
> -
> -	return oa_report_header_64bit(stream) ?
> -		xe_map_rd(stream->oa->xe, map, report_offset, u64) :
> -		xe_map_rd(stream->oa->xe, map, report_offset, u32);
> -}

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260821200728.1048699-5-umesh.nerlige.ramappa@intel.com?part=2

^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user
  2026-08-21 20:07 [PATCH 0/3] Modify the SW tail logic in OA Umesh Nerlige Ramappa
  2026-08-21 20:07 ` [PATCH 1/3] drm/xe/xe_oa: Clear status only if relevant bits are set Umesh Nerlige Ramappa
  2026-08-21 20:07 ` [PATCH 2/3] drm/xe/xe_oa: Avoid checking and setting fields in the OA report Umesh Nerlige Ramappa
@ 2026-08-21 20:07 ` Umesh Nerlige Ramappa
  2026-08-21 20:21   ` sashiko-bot
  2026-08-21 20:14 ` ✓ CI.KUnit: success for Modify the SW tail logic in OA Patchwork
                   ` (2 subsequent siblings)
  5 siblings, 1 reply; 19+ messages in thread
From: Umesh Nerlige Ramappa @ 2026-08-21 20:07 UTC (permalink / raw)
  To: intel-xe, Ashutosh Dixit

When running heavy workloads, reading the OA reports too soon does not
guarantee that the report has landed in memory. To make sure correct
reports are copied to user buffer, only return reports that lag the
current HW_TAIL register by 32 reports. This is an empirical number
based on a heavy render workload and several test iterations.

The reports that user reads will always lag the HW tail by 32 reports,
however since OA is used for post processing analysis, this should not
affect any current use cases. When the stream is closed or disabled, we
let the user read the remaining reports up until HW tail.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
v2: Fix the LAG logic by using sliding window (Sashiko)
v3: Fix checkpatch warning
v4: Update sw tail on stream disable (Ashutosh)
---
 drivers/gpu/drm/xe/xe_oa.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
index d7647f37ab02..2a88f7d9e67c 100644
--- a/drivers/gpu/drm/xe/xe_oa.c
+++ b/drivers/gpu/drm/xe/xe_oa.c
@@ -224,7 +224,7 @@ static bool mert_wa_14026633728(struct xe_oa_stream *s)
 static bool xe_oa_buffer_check_unlocked(struct xe_oa_stream *stream)
 {
 	u32 gtt_offset = xe_bo_ggtt_addr(stream->oa_buffer.bo);
-	u32 hw_tail, partial_report_size, available;
+	u32 hw_tail, partial_report_size, available, lag;
 	int report_size = stream->oa_buffer.format->size;
 	unsigned long flags;
 
@@ -234,17 +234,23 @@ static bool xe_oa_buffer_check_unlocked(struct xe_oa_stream *stream)
 	hw_tail -= gtt_offset;
 
 	/*
-	 * The tail pointer increases in 64 byte (cacheline size), not in report_size
+	 * The hw_tail pointer increases in 64 byte (cacheline size), not in report_size
 	 * increments. Also report size may not be a power of 2. Compute potential
 	 * partially landed report in OA buffer.
 	 */
 	partial_report_size = xe_oa_circ_diff(stream, hw_tail, stream->oa_buffer.tail);
 	partial_report_size %= report_size;
 
-	/* Subtract partial amount off the tail */
+	/* Subtract partial amount off the hw_tail */
 	hw_tail = xe_oa_circ_diff(stream, hw_tail, partial_report_size);
 
-	stream->oa_buffer.tail = hw_tail;
+#define LAG_REPORTS 32
+	lag = xe_oa_circ_diff(stream, hw_tail, stream->oa_buffer.tail);
+	if (!stream->enabled)
+		stream->oa_buffer.tail = hw_tail;
+	else if (lag > LAG_REPORTS * report_size)
+		stream->oa_buffer.tail = xe_oa_circ_diff(stream, hw_tail,
+							 LAG_REPORTS * report_size);
 
 	available = xe_oa_circ_diff(stream, stream->oa_buffer.tail, stream->oa_buffer.head);
 	stream->pollin = available >= stream->wait_num_reports * report_size;
-- 
2.51.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* Re: [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user
  2026-08-21 20:07 ` [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user Umesh Nerlige Ramappa
@ 2026-08-21 20:21   ` sashiko-bot
  0 siblings, 0 replies; 19+ messages in thread
From: sashiko-bot @ 2026-08-21 20:21 UTC (permalink / raw)
  To: Umesh Nerlige Ramappa; +Cc: intel-xe

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Readers can block indefinitely on disabled streams because `stream->enabled` is set to false too late, failing to flush the final OA reports.
- [Medium] Data race on `stream->enabled` between `xe_oa_buffer_check_unlocked` and `xe_oa_disable_locked`/`xe_oa_enable_locked`.
--

--- Patch [3]: [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user ---
commit 4ec3e1c770bffdf39a86c1db169059b4bc510058
Author: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

drm/xe/xe_oa: Add a lag to the reports that is exported to user

This commit delays the visibility of OA reports to user space by holding
back the tail by 32 reports to ensure they have landed in memory. It also
attempts to flush all remaining reports when the stream is disabled.

> diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
> --- a/drivers/gpu/drm/xe/xe_oa.c
> +++ b/drivers/gpu/drm/xe/xe_oa.c

[ ... ]

> @@ -234,17 +234,23 @@ static bool xe_oa_buffer_check_unlocked(struct xe_oa_stream *stream)
>  	/* Subtract partial amount off the hw_tail */
>  	hw_tail = xe_oa_circ_diff(stream, hw_tail, partial_report_size);
>  
> -	stream->oa_buffer.tail = hw_tail;
> +#define LAG_REPORTS 32
> +	lag = xe_oa_circ_diff(stream, hw_tail, stream->oa_buffer.tail);
> +	if (!stream->enabled)

[Severity: Medium]
Is it safe to read stream->enabled here? It appears to be read while holding
the stream->oa_buffer.ptr_lock spinlock, but modified in
xe_oa_disable_locked() and xe_oa_enable_locked() while holding the
stream->stream_lock mutex. Could this cause data races?

[Severity: High]
Will readers waiting on a disabled stream block indefinitely?

When a thread calls DRM_XE_OBSERVATION_IOCTL_DISABLE, xe_oa_disable_locked()
is executed:

xe_oa_disable_locked() {
    xe_oa_stream_disable(stream);
    ...
    stream->enabled = false;
}

xe_oa_stream_disable() cancels the poll timer and calls
xe_oa_buffer_check_unlocked() to flush the final reports. However, since
stream->enabled is still true when xe_oa_buffer_check_unlocked() is called,
this bypass check will evaluate to false.

If the tail is held back by the lag, pollin evaluates to false, and
wake_up() is never called, could this cause userspace threads blocking in
read() or poll() to hang indefinitely with stranded reports?

> +		stream->oa_buffer.tail = hw_tail;
> +	else if (lag > LAG_REPORTS * report_size)
> +		stream->oa_buffer.tail = xe_oa_circ_diff(stream, hw_tail,
> +							 LAG_REPORTS * report_size);
>  
>  	available = xe_oa_circ_diff(stream, stream->oa_buffer.tail, stream->oa_buffer.head);

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260821200728.1048699-5-umesh.nerlige.ramappa@intel.com?part=3

^ permalink raw reply	[flat|nested] 19+ messages in thread

* ✓ CI.KUnit: success for Modify the SW tail logic in OA
  2026-08-21 20:07 [PATCH 0/3] Modify the SW tail logic in OA Umesh Nerlige Ramappa
                   ` (2 preceding siblings ...)
  2026-08-21 20:07 ` [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user Umesh Nerlige Ramappa
@ 2026-08-21 20:14 ` Patchwork
  2026-08-21 21:03 ` ✓ Xe.CI.BAT: " Patchwork
  2026-08-21 22:35 ` ✓ Xe.CI.FULL: " Patchwork
  5 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2026-08-21 20:14 UTC (permalink / raw)
  To: Umesh Nerlige Ramappa; +Cc: intel-xe

== Series Details ==

Series: Modify the SW tail logic in OA
URL   : https://patchwork.freedesktop.org/series/172609/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[20:13:10] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:13:15] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:13:47] Starting KUnit Kernel (1/1)...
[20:13:47] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:13:47] ================== guc_buf (11 subtests) ===================
[20:13:47] [PASSED] test_smallest
[20:13:47] [PASSED] test_largest
[20:13:47] [PASSED] test_granular
[20:13:47] [PASSED] test_unique
[20:13:47] [PASSED] test_overlap
[20:13:47] [PASSED] test_reusable
[20:13:47] [PASSED] test_too_big
[20:13:47] [PASSED] test_flush
[20:13:47] [PASSED] test_lookup
[20:13:47] [PASSED] test_data
[20:13:47] [PASSED] test_class
[20:13:47] ===================== [PASSED] guc_buf =====================
[20:13:47] =================== guc_dbm (7 subtests) ===================
[20:13:47] [PASSED] test_empty
[20:13:47] [PASSED] test_default
[20:13:47] ======================== test_size  ========================
[20:13:47] [PASSED] 4
[20:13:47] [PASSED] 8
[20:13:47] [PASSED] 32
[20:13:47] [PASSED] 256
[20:13:47] ==================== [PASSED] test_size ====================
[20:13:47] ======================= test_reuse  ========================
[20:13:47] [PASSED] 4
[20:13:47] [PASSED] 8
[20:13:47] [PASSED] 32
[20:13:47] [PASSED] 256
[20:13:47] =================== [PASSED] test_reuse ====================
[20:13:47] =================== test_range_overlap  ====================
[20:13:47] [PASSED] 4
[20:13:47] [PASSED] 8
[20:13:47] [PASSED] 32
[20:13:47] [PASSED] 256
[20:13:47] =============== [PASSED] test_range_overlap ================
[20:13:47] =================== test_range_compact  ====================
[20:13:47] [PASSED] 4
[20:13:47] [PASSED] 8
[20:13:47] [PASSED] 32
[20:13:47] [PASSED] 256
[20:13:47] =============== [PASSED] test_range_compact ================
[20:13:47] ==================== test_range_spare  =====================
[20:13:47] [PASSED] 4
[20:13:47] [PASSED] 8
[20:13:47] [PASSED] 32
[20:13:47] [PASSED] 256
[20:13:47] ================ [PASSED] test_range_spare =================
[20:13:47] ===================== [PASSED] guc_dbm =====================
[20:13:47] =================== guc_idm (6 subtests) ===================
[20:13:47] [PASSED] bad_init
[20:13:47] [PASSED] no_init
[20:13:47] [PASSED] init_fini
[20:13:47] [PASSED] check_used
[20:13:47] [PASSED] check_quota
[20:13:47] [PASSED] check_all
[20:13:47] ===================== [PASSED] guc_idm =====================
[20:13:47] =============== guc_klv_helpers (9 subtests) ===============
[20:13:47] [PASSED] test_count
[20:13:47] [PASSED] test_encode_u32
[20:13:47] [PASSED] test_encode_u64
[20:13:47] [PASSED] test_encode_string
[20:13:47] [PASSED] test_encode_object_raw
[20:13:47] [PASSED] test_encode_object_klv
[20:13:47] [PASSED] test_encode_object_nested
[20:13:47] [PASSED] test_encode_object_basic
[20:13:47] [PASSED] test_print
[20:13:47] ================= [PASSED] guc_klv_helpers =================
[20:13:47] =================== xe_log (4 subtests) ====================
[20:13:47] [PASSED] demo_cper
[20:13:47] [PASSED] demo_dmesg
[20:13:47] ======================= test_dmesg  ========================
[20:13:47] [PASSED] test_fatal
[20:13:47] [PASSED] test_fatal_tile
[20:13:47] [PASSED] test_fatal_gt
[20:13:47] [PASSED] test_fatal_comp
[20:13:47] [PASSED] test_fatal_comp_tile
[20:13:47] [PASSED] test_fatal_comp_gt
[20:13:47] [PASSED] test_fatal_all
[20:13:47] [PASSED] test_recoverable
[20:13:47] [PASSED] test_recoverable_tile
[20:13:47] [PASSED] test_recoverable_gt
[20:13:47] [PASSED] test_recoverable_comp
[20:13:47] [PASSED] test_recoverable_comp_tile
[20:13:47] [PASSED] test_recoverable_comp_gt
[20:13:47] [PASSED] test_recoverable_all
[20:13:47] [PASSED] test_info
[20:13:47] [PASSED] test_info_tile
[20:13:47] [PASSED] test_info_gt
[20:13:47] [PASSED] test_info_err
[20:13:47] [PASSED] test_info_comp
[20:13:47] [PASSED] test_info_comp_tile
[20:13:47] [PASSED] test_info_comp_gt
[20:13:47] [PASSED] test_info_all
[20:13:47] [PASSED] test_hw_fatal
[20:13:47] [PASSED] test_hw_recoverable
[20:13:47] [PASSED] test_hw_corrected
[20:13:47] [PASSED] test_hw_informational
[20:13:47] =================== [PASSED] test_dmesg ====================
[20:13:47] ====================== test_invalid  =======================
[20:13:47] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[20:13:47] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[20:13:47] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[20:13:47] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[20:13:47] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[20:13:47] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[20:13:47] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[20:13:47] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[20:13:47] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[20:13:47] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[20:13:47] ================== [SKIPPED] test_invalid ==================
[20:13:47] ===================== [PASSED] xe_log ======================
[20:13:47] ================== no_relay (3 subtests) ===================
[20:13:47] [PASSED] xe_drops_guc2pf_if_not_ready
[20:13:47] [PASSED] xe_drops_guc2vf_if_not_ready
[20:13:47] [PASSED] xe_rejects_send_if_not_ready
[20:13:47] ==================== [PASSED] no_relay =====================
[20:13:47] ================== pf_relay (14 subtests) ==================
[20:13:47] [PASSED] pf_rejects_guc2pf_too_short
[20:13:47] [PASSED] pf_rejects_guc2pf_too_long
[20:13:47] [PASSED] pf_rejects_guc2pf_no_payload
[20:13:47] [PASSED] pf_fails_no_payload
[20:13:47] [PASSED] pf_fails_bad_origin
[20:13:47] [PASSED] pf_fails_bad_type
[20:13:47] [PASSED] pf_txn_reports_error
[20:13:47] [PASSED] pf_txn_sends_pf2guc
[20:13:47] [PASSED] pf_sends_pf2guc
[20:13:47] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[20:13:47] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[20:13:47] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[20:13:47] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[20:13:47] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[20:13:47] ==================== [PASSED] pf_relay =====================
[20:13:47] ================== vf_relay (3 subtests) ===================
[20:13:47] [PASSED] vf_rejects_guc2vf_too_short
[20:13:47] [PASSED] vf_rejects_guc2vf_too_long
[20:13:47] [PASSED] vf_rejects_guc2vf_no_payload
[20:13:47] ==================== [PASSED] vf_relay =====================
[20:13:47] ================ pf_gt_config (9 subtests) =================
[20:13:47] [PASSED] fair_contexts_1vf
[20:13:47] [PASSED] fair_doorbells_1vf
[20:13:47] [PASSED] fair_ggtt_1vf
[20:13:47] ====================== fair_vram_1vf  ======================
[20:13:47] [PASSED] 3.50 GiB
[20:13:47] [PASSED] 11.5 GiB
[20:13:47] [PASSED] 15.5 GiB
[20:13:47] [PASSED] 31.5 GiB
[20:13:47] [PASSED] 63.5 GiB
[20:13:47] [PASSED] 1.91 GiB
[20:13:47] ================== [PASSED] fair_vram_1vf ==================
[20:13:47] ================ fair_vram_1vf_admin_only  =================
[20:13:47] [PASSED] 3.50 GiB
[20:13:47] [PASSED] 11.5 GiB
[20:13:47] [PASSED] 15.5 GiB
[20:13:47] [PASSED] 31.5 GiB
[20:13:47] [PASSED] 63.5 GiB
[20:13:47] [PASSED] 1.91 GiB
[20:13:47] ============ [PASSED] fair_vram_1vf_admin_only =============
[20:13:47] ====================== fair_contexts  ======================
[20:13:47] [PASSED] 1 VF
[20:13:47] [PASSED] 2 VFs
[20:13:47] [PASSED] 3 VFs
[20:13:47] [PASSED] 4 VFs
[20:13:47] [PASSED] 5 VFs
[20:13:47] [PASSED] 6 VFs
[20:13:47] [PASSED] 7 VFs
[20:13:47] [PASSED] 8 VFs
[20:13:47] [PASSED] 9 VFs
[20:13:47] [PASSED] 10 VFs
[20:13:47] [PASSED] 11 VFs
[20:13:47] [PASSED] 12 VFs
[20:13:47] [PASSED] 13 VFs
[20:13:47] [PASSED] 14 VFs
[20:13:47] [PASSED] 15 VFs
[20:13:47] [PASSED] 16 VFs
[20:13:47] [PASSED] 17 VFs
[20:13:47] [PASSED] 18 VFs
[20:13:47] [PASSED] 19 VFs
[20:13:47] [PASSED] 20 VFs
[20:13:47] [PASSED] 21 VFs
[20:13:47] [PASSED] 22 VFs
[20:13:47] [PASSED] 23 VFs
[20:13:47] [PASSED] 24 VFs
[20:13:47] [PASSED] 25 VFs
[20:13:47] [PASSED] 26 VFs
[20:13:47] [PASSED] 27 VFs
[20:13:47] [PASSED] 28 VFs
[20:13:47] [PASSED] 29 VFs
[20:13:47] [PASSED] 30 VFs
[20:13:47] [PASSED] 31 VFs
[20:13:47] [PASSED] 32 VFs
[20:13:47] [PASSED] 33 VFs
[20:13:47] [PASSED] 34 VFs
[20:13:47] [PASSED] 35 VFs
[20:13:47] [PASSED] 36 VFs
[20:13:47] [PASSED] 37 VFs
[20:13:47] [PASSED] 38 VFs
[20:13:47] [PASSED] 39 VFs
[20:13:47] [PASSED] 40 VFs
[20:13:47] [PASSED] 41 VFs
[20:13:47] [PASSED] 42 VFs
[20:13:47] [PASSED] 43 VFs
[20:13:47] [PASSED] 44 VFs
[20:13:47] [PASSED] 45 VFs
[20:13:47] [PASSED] 46 VFs
[20:13:47] [PASSED] 47 VFs
[20:13:47] [PASSED] 48 VFs
[20:13:47] [PASSED] 49 VFs
[20:13:47] [PASSED] 50 VFs
[20:13:47] [PASSED] 51 VFs
[20:13:47] [PASSED] 52 VFs
[20:13:47] [PASSED] 53 VFs
[20:13:47] [PASSED] 54 VFs
[20:13:47] [PASSED] 55 VFs
[20:13:47] [PASSED] 56 VFs
[20:13:47] [PASSED] 57 VFs
[20:13:47] [PASSED] 58 VFs
[20:13:47] [PASSED] 59 VFs
[20:13:47] [PASSED] 60 VFs
[20:13:47] [PASSED] 61 VFs
[20:13:47] [PASSED] 62 VFs
[20:13:47] [PASSED] 63 VFs
[20:13:47] ================== [PASSED] fair_contexts ==================
[20:13:47] ===================== fair_doorbells  ======================
[20:13:47] [PASSED] 1 VF
[20:13:47] [PASSED] 2 VFs
[20:13:47] [PASSED] 3 VFs
[20:13:47] [PASSED] 4 VFs
[20:13:47] [PASSED] 5 VFs
[20:13:47] [PASSED] 6 VFs
[20:13:47] [PASSED] 7 VFs
[20:13:47] [PASSED] 8 VFs
[20:13:47] [PASSED] 9 VFs
[20:13:47] [PASSED] 10 VFs
[20:13:47] [PASSED] 11 VFs
[20:13:47] [PASSED] 12 VFs
[20:13:47] [PASSED] 13 VFs
[20:13:47] [PASSED] 14 VFs
[20:13:47] [PASSED] 15 VFs
[20:13:47] [PASSED] 16 VFs
[20:13:47] [PASSED] 17 VFs
[20:13:47] [PASSED] 18 VFs
[20:13:47] [PASSED] 19 VFs
[20:13:47] [PASSED] 20 VFs
[20:13:47] [PASSED] 21 VFs
[20:13:47] [PASSED] 22 VFs
[20:13:47] [PASSED] 23 VFs
[20:13:47] [PASSED] 24 VFs
[20:13:47] [PASSED] 25 VFs
[20:13:47] [PASSED] 26 VFs
[20:13:47] [PASSED] 27 VFs
[20:13:47] [PASSED] 28 VFs
[20:13:47] [PASSED] 29 VFs
[20:13:47] [PASSED] 30 VFs
[20:13:47] [PASSED] 31 VFs
[20:13:47] [PASSED] 32 VFs
[20:13:47] [PASSED] 33 VFs
[20:13:47] [PASSED] 34 VFs
[20:13:47] [PASSED] 35 VFs
[20:13:47] [PASSED] 36 VFs
[20:13:47] [PASSED] 37 VFs
[20:13:47] [PASSED] 38 VFs
[20:13:47] [PASSED] 39 VFs
[20:13:47] [PASSED] 40 VFs
[20:13:47] [PASSED] 41 VFs
[20:13:47] [PASSED] 42 VFs
[20:13:47] [PASSED] 43 VFs
[20:13:47] [PASSED] 44 VFs
[20:13:47] [PASSED] 45 VFs
[20:13:47] [PASSED] 46 VFs
[20:13:47] [PASSED] 47 VFs
[20:13:47] [PASSED] 48 VFs
[20:13:47] [PASSED] 49 VFs
[20:13:47] [PASSED] 50 VFs
[20:13:47] [PASSED] 51 VFs
[20:13:47] [PASSED] 52 VFs
[20:13:47] [PASSED] 53 VFs
[20:13:47] [PASSED] 54 VFs
[20:13:47] [PASSED] 55 VFs
[20:13:47] [PASSED] 56 VFs
[20:13:47] [PASSED] 57 VFs
[20:13:47] [PASSED] 58 VFs
[20:13:47] [PASSED] 59 VFs
[20:13:47] [PASSED] 60 VFs
[20:13:47] [PASSED] 61 VFs
[20:13:47] [PASSED] 62 VFs
[20:13:47] [PASSED] 63 VFs
[20:13:47] ================= [PASSED] fair_doorbells ==================
[20:13:47] ======================== fair_ggtt  ========================
[20:13:47] [PASSED] 1 VF
[20:13:47] [PASSED] 2 VFs
[20:13:47] [PASSED] 3 VFs
[20:13:47] [PASSED] 4 VFs
[20:13:47] [PASSED] 5 VFs
[20:13:47] [PASSED] 6 VFs
[20:13:47] [PASSED] 7 VFs
[20:13:47] [PASSED] 8 VFs
[20:13:47] [PASSED] 9 VFs
[20:13:47] [PASSED] 10 VFs
[20:13:47] [PASSED] 11 VFs
[20:13:47] [PASSED] 12 VFs
[20:13:47] [PASSED] 13 VFs
[20:13:47] [PASSED] 14 VFs
[20:13:47] [PASSED] 15 VFs
[20:13:47] [PASSED] 16 VFs
[20:13:47] [PASSED] 17 VFs
[20:13:47] [PASSED] 18 VFs
[20:13:47] [PASSED] 19 VFs
[20:13:47] [PASSED] 20 VFs
[20:13:47] [PASSED] 21 VFs
[20:13:47] [PASSED] 22 VFs
[20:13:47] [PASSED] 23 VFs
[20:13:47] [PASSED] 24 VFs
[20:13:47] [PASSED] 25 VFs
[20:13:47] [PASSED] 26 VFs
[20:13:47] [PASSED] 27 VFs
[20:13:47] [PASSED] 28 VFs
[20:13:47] [PASSED] 29 VFs
[20:13:47] [PASSED] 30 VFs
[20:13:47] [PASSED] 31 VFs
[20:13:47] [PASSED] 32 VFs
[20:13:47] [PASSED] 33 VFs
[20:13:47] [PASSED] 34 VFs
[20:13:47] [PASSED] 35 VFs
[20:13:47] [PASSED] 36 VFs
[20:13:47] [PASSED] 37 VFs
[20:13:47] [PASSED] 38 VFs
[20:13:47] [PASSED] 39 VFs
[20:13:47] [PASSED] 40 VFs
[20:13:47] [PASSED] 41 VFs
[20:13:47] [PASSED] 42 VFs
[20:13:47] [PASSED] 43 VFs
[20:13:47] [PASSED] 44 VFs
[20:13:47] [PASSED] 45 VFs
[20:13:47] [PASSED] 46 VFs
[20:13:47] [PASSED] 47 VFs
[20:13:47] [PASSED] 48 VFs
[20:13:47] [PASSED] 49 VFs
[20:13:47] [PASSED] 50 VFs
[20:13:47] [PASSED] 51 VFs
[20:13:47] [PASSED] 52 VFs
[20:13:47] [PASSED] 53 VFs
[20:13:47] [PASSED] 54 VFs
[20:13:47] [PASSED] 55 VFs
[20:13:47] [PASSED] 56 VFs
[20:13:47] [PASSED] 57 VFs
[20:13:47] [PASSED] 58 VFs
[20:13:47] [PASSED] 59 VFs
[20:13:47] [PASSED] 60 VFs
[20:13:47] [PASSED] 61 VFs
[20:13:47] [PASSED] 62 VFs
[20:13:47] [PASSED] 63 VFs
[20:13:47] ==================== [PASSED] fair_ggtt ====================
[20:13:47] ======================== fair_vram  ========================
[20:13:47] [PASSED] 1 VF
[20:13:47] [PASSED] 2 VFs
[20:13:47] [PASSED] 3 VFs
[20:13:47] [PASSED] 4 VFs
[20:13:47] [PASSED] 5 VFs
[20:13:47] [PASSED] 6 VFs
[20:13:47] [PASSED] 7 VFs
[20:13:47] [PASSED] 8 VFs
[20:13:47] [PASSED] 9 VFs
[20:13:47] [PASSED] 10 VFs
[20:13:47] [PASSED] 11 VFs
[20:13:47] [PASSED] 12 VFs
[20:13:47] [PASSED] 13 VFs
[20:13:47] [PASSED] 14 VFs
[20:13:47] [PASSED] 15 VFs
[20:13:47] [PASSED] 16 VFs
[20:13:47] [PASSED] 17 VFs
[20:13:47] [PASSED] 18 VFs
[20:13:47] [PASSED] 19 VFs
[20:13:47] [PASSED] 20 VFs
[20:13:47] [PASSED] 21 VFs
[20:13:47] [PASSED] 22 VFs
[20:13:47] [PASSED] 23 VFs
[20:13:47] [PASSED] 24 VFs
[20:13:47] [PASSED] 25 VFs
[20:13:47] [PASSED] 26 VFs
[20:13:47] [PASSED] 27 VFs
[20:13:47] [PASSED] 28 VFs
[20:13:47] [PASSED] 29 VFs
[20:13:47] [PASSED] 30 VFs
[20:13:47] [PASSED] 31 VFs
[20:13:47] [PASSED] 32 VFs
[20:13:47] [PASSED] 33 VFs
[20:13:47] [PASSED] 34 VFs
[20:13:47] [PASSED] 35 VFs
[20:13:47] [PASSED] 36 VFs
[20:13:47] [PASSED] 37 VFs
[20:13:47] [PASSED] 38 VFs
[20:13:47] [PASSED] 39 VFs
[20:13:47] [PASSED] 40 VFs
[20:13:47] [PASSED] 41 VFs
[20:13:47] [PASSED] 42 VFs
[20:13:47] [PASSED] 43 VFs
[20:13:47] [PASSED] 44 VFs
[20:13:47] [PASSED] 45 VFs
[20:13:47] [PASSED] 46 VFs
[20:13:47] [PASSED] 47 VFs
[20:13:47] [PASSED] 48 VFs
[20:13:47] [PASSED] 49 VFs
[20:13:47] [PASSED] 50 VFs
[20:13:47] [PASSED] 51 VFs
[20:13:47] [PASSED] 52 VFs
[20:13:47] [PASSED] 53 VFs
[20:13:47] [PASSED] 54 VFs
[20:13:47] [PASSED] 55 VFs
[20:13:47] [PASSED] 56 VFs
[20:13:47] [PASSED] 57 VFs
[20:13:47] [PASSED] 58 VFs
[20:13:47] [PASSED] 59 VFs
[20:13:47] [PASSED] 60 VFs
[20:13:47] [PASSED] 61 VFs
[20:13:47] [PASSED] 62 VFs
[20:13:47] [PASSED] 63 VFs
[20:13:47] ==================== [PASSED] fair_vram ====================
[20:13:47] ================== [PASSED] pf_gt_config ===================
[20:13:47] ===================== lmtt (1 subtest) =====================
[20:13:47] ======================== test_ops  =========================
[20:13:47] [PASSED] 2-level
[20:13:47] [PASSED] multi-level
[20:13:47] ==================== [PASSED] test_ops =====================
[20:13:47] ====================== [PASSED] lmtt =======================
[20:13:47] ================= sriov_packet (1 subtest) =================
[20:13:47] [PASSED] test_descriptor_init
[20:13:47] ================== [PASSED] sriov_packet ===================
[20:13:47] ================= pf_service (11 subtests) =================
[20:13:47] [PASSED] pf_negotiate_any
[20:13:47] [PASSED] pf_negotiate_base_match
[20:13:47] [PASSED] pf_negotiate_base_newer
[20:13:47] [PASSED] pf_negotiate_base_next
[20:13:47] [SKIPPED] pf_negotiate_base_older (no older minor)
[20:13:47] [PASSED] pf_negotiate_base_prev
[20:13:47] [PASSED] pf_negotiate_latest_match
[20:13:47] [PASSED] pf_negotiate_latest_newer
[20:13:47] [PASSED] pf_negotiate_latest_next
[20:13:47] [SKIPPED] pf_negotiate_latest_older (no older minor)
[20:13:47] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[20:13:47] =================== [PASSED] pf_service ====================
[20:13:47] ================= xe_guc_g2g (2 subtests) ==================
[20:13:47] ============== xe_live_guc_g2g_kunit_default  ==============
[20:13:47] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[20:13:47] ============== xe_live_guc_g2g_kunit_allmem  ===============
[20:13:47] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[20:13:47] =================== [SKIPPED] xe_guc_g2g ===================
[20:13:47] =================== xe_mocs (2 subtests) ===================
[20:13:47] ================ xe_live_mocs_kernel_kunit  ================
[20:13:47] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[20:13:47] ================ xe_live_mocs_reset_kunit  =================
[20:13:47] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[20:13:47] ==================== [SKIPPED] xe_mocs =====================
[20:13:47] ================= xe_migrate (2 subtests) ==================
[20:13:47] ================= xe_migrate_sanity_kunit  =================
[20:13:47] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[20:13:47] ================== xe_validate_ccs_kunit  ==================
[20:13:47] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[20:13:47] =================== [SKIPPED] xe_migrate ===================
[20:13:47] ================== xe_dma_buf (1 subtest) ==================
[20:13:47] ==================== xe_dma_buf_kunit  =====================
[20:13:47] ================ [SKIPPED] xe_dma_buf_kunit ================
[20:13:47] =================== [SKIPPED] xe_dma_buf ===================
[20:13:47] ================= xe_bo_shrink (1 subtest) =================
[20:13:47] =================== xe_bo_shrink_kunit  ====================
[20:13:47] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[20:13:47] ================== [SKIPPED] xe_bo_shrink ==================
[20:13:47] ==================== xe_bo (2 subtests) ====================
[20:13:47] ================== xe_ccs_migrate_kunit  ===================
[20:13:47] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[20:13:47] ==================== xe_bo_evict_kunit  ====================
[20:13:47] =============== [SKIPPED] xe_bo_evict_kunit ================
[20:13:47] ===================== [SKIPPED] xe_bo ======================
[20:13:47] =================== xe_any (9 subtests) ====================
[20:13:47] [PASSED] test_to_xe
[20:13:47] [PASSED] test_to_dev
[20:13:47] [PASSED] test_to_pdev
[20:13:47] [PASSED] test_to_drm
[20:13:47] [PASSED] test_if_pdev
[20:13:47] [PASSED] test_if_xe
[20:13:47] [PASSED] test_if_tile
[20:13:47] [PASSED] test_if_gt
[20:13:47] [PASSED] test_to_id
[20:13:47] ===================== [PASSED] xe_any ======================
[20:13:47] ==================== args (13 subtests) ====================
[20:13:47] [PASSED] count_args_test
[20:13:47] [PASSED] call_args_example
[20:13:47] [PASSED] call_args_test
[20:13:47] [PASSED] drop_first_arg_example
[20:13:47] [PASSED] drop_first_arg_test
[20:13:47] [PASSED] first_arg_example
[20:13:47] [PASSED] first_arg_test
[20:13:47] [PASSED] last_arg_example
[20:13:47] [PASSED] last_arg_test
[20:13:47] [PASSED] pick_arg_example
[20:13:47] [PASSED] if_args_example
[20:13:47] [PASSED] if_args_test
[20:13:47] [PASSED] sep_comma_example
[20:13:47] ====================== [PASSED] args =======================
[20:13:47] =================== xe_pci (3 subtests) ====================
[20:13:47] ==================== check_graphics_ip  ====================
[20:13:47] [PASSED] 12.00 Xe_LP
[20:13:47] [PASSED] 12.10 Xe_LP+
[20:13:47] [PASSED] 12.55 Xe_HPG
[20:13:47] [PASSED] 12.60 Xe_HPC
[20:13:47] [PASSED] 12.70 Xe_LPG
[20:13:47] [PASSED] 12.71 Xe_LPG
[20:13:47] [PASSED] 12.74 Xe_LPG+
[20:13:47] [PASSED] 20.01 Xe2_HPG
[20:13:47] [PASSED] 20.02 Xe2_HPG
[20:13:47] [PASSED] 20.04 Xe2_LPG
[20:13:47] [PASSED] 30.00 Xe3_LPG
[20:13:47] [PASSED] 30.01 Xe3_LPG
[20:13:47] [PASSED] 30.03 Xe3_LPG
[20:13:47] [PASSED] 30.04 Xe3_LPG
[20:13:47] [PASSED] 30.05 Xe3_LPG
[20:13:47] [PASSED] 35.10 Xe3p_LPG
[20:13:47] [PASSED] 35.11 Xe3p_XPC
[20:13:47] ================ [PASSED] check_graphics_ip ================
[20:13:47] ===================== check_media_ip  ======================
[20:13:47] [PASSED] 12.00 Xe_M
[20:13:47] [PASSED] 12.55 Xe_HPM
[20:13:47] [PASSED] 13.00 Xe_LPM+
[20:13:47] [PASSED] 13.01 Xe2_HPM
[20:13:47] [PASSED] 20.00 Xe2_LPM
[20:13:47] [PASSED] 30.00 Xe3_LPM
[20:13:47] [PASSED] 30.02 Xe3_LPM
[20:13:47] [PASSED] 35.00 Xe3p_LPM
[20:13:47] [PASSED] 35.03 Xe3p_HPM
[20:13:47] ================= [PASSED] check_media_ip ==================
[20:13:47] =================== check_platform_desc  ===================
[20:13:47] [PASSED] 0x9A60 (TIGERLAKE)
[20:13:47] [PASSED] 0x9A68 (TIGERLAKE)
[20:13:47] [PASSED] 0x9A70 (TIGERLAKE)
[20:13:47] [PASSED] 0x9A40 (TIGERLAKE)
[20:13:47] [PASSED] 0x9A49 (TIGERLAKE)
[20:13:47] [PASSED] 0x9A59 (TIGERLAKE)
[20:13:47] [PASSED] 0x9A78 (TIGERLAKE)
[20:13:47] [PASSED] 0x9AC0 (TIGERLAKE)
[20:13:47] [PASSED] 0x9AC9 (TIGERLAKE)
[20:13:47] [PASSED] 0x9AD9 (TIGERLAKE)
[20:13:47] [PASSED] 0x9AF8 (TIGERLAKE)
[20:13:47] [PASSED] 0x4C80 (ROCKETLAKE)
[20:13:47] [PASSED] 0x4C8A (ROCKETLAKE)
[20:13:47] [PASSED] 0x4C8B (ROCKETLAKE)
[20:13:47] [PASSED] 0x4C8C (ROCKETLAKE)
[20:13:47] [PASSED] 0x4C90 (ROCKETLAKE)
[20:13:47] [PASSED] 0x4C9A (ROCKETLAKE)
[20:13:47] [PASSED] 0x4680 (ALDERLAKE_S)
[20:13:47] [PASSED] 0x4682 (ALDERLAKE_S)
[20:13:47] [PASSED] 0x4688 (ALDERLAKE_S)
[20:13:47] [PASSED] 0x468A (ALDERLAKE_S)
[20:13:47] [PASSED] 0x468B (ALDERLAKE_S)
[20:13:47] [PASSED] 0x4690 (ALDERLAKE_S)
[20:13:47] [PASSED] 0x4692 (ALDERLAKE_S)
[20:13:47] [PASSED] 0x4693 (ALDERLAKE_S)
[20:13:47] [PASSED] 0x46A0 (ALDERLAKE_P)
[20:13:47] [PASSED] 0x46A1 (ALDERLAKE_P)
[20:13:47] [PASSED] 0x46A2 (ALDERLAKE_P)
[20:13:47] [PASSED] 0x46A3 (ALDERLAKE_P)
[20:13:47] [PASSED] 0x46A6 (ALDERLAKE_P)
[20:13:47] [PASSED] 0x46A8 (ALDERLAKE_P)
[20:13:47] [PASSED] 0x46AA (ALDERLAKE_P)
[20:13:47] [PASSED] 0x462A (ALDERLAKE_P)
[20:13:47] [PASSED] 0x4626 (ALDERLAKE_P)
[20:13:47] [PASSED] 0x4628 (ALDERLAKE_P)
[20:13:47] [PASSED] 0x46B0 (ALDERLAKE_P)
[20:13:47] [PASSED] 0x46B1 (ALDERLAKE_P)
[20:13:47] [PASSED] 0x46B2 (ALDERLAKE_P)
[20:13:47] [PASSED] 0x46B3 (ALDERLAKE_P)
[20:13:47] [PASSED] 0x46C0 (ALDERLAKE_P)
[20:13:47] [PASSED] 0x46C1 (ALDERLAKE_P)
[20:13:47] [PASSED] 0x46C2 (ALDERLAKE_P)
[20:13:47] [PASSED] 0x46C3 (ALDERLAKE_P)
[20:13:47] [PASSED] 0x46D0 (ALDERLAKE_N)
[20:13:47] [PASSED] 0x46D1 (ALDERLAKE_N)
[20:13:47] [PASSED] 0x46D2 (ALDERLAKE_N)
[20:13:47] [PASSED] 0x46D3 (ALDERLAKE_N)
[20:13:47] [PASSED] 0x46D4 (ALDERLAKE_N)
[20:13:47] [PASSED] 0xA721 (ALDERLAKE_P)
[20:13:47] [PASSED] 0xA7A1 (ALDERLAKE_P)
[20:13:47] [PASSED] 0xA7A9 (ALDERLAKE_P)
[20:13:47] [PASSED] 0xA7AC (ALDERLAKE_P)
[20:13:47] [PASSED] 0xA7AD (ALDERLAKE_P)
[20:13:47] [PASSED] 0xA720 (ALDERLAKE_P)
[20:13:47] [PASSED] 0xA7A0 (ALDERLAKE_P)
[20:13:47] [PASSED] 0xA7A8 (ALDERLAKE_P)
[20:13:47] [PASSED] 0xA7AA (ALDERLAKE_P)
[20:13:47] [PASSED] 0xA7AB (ALDERLAKE_P)
[20:13:47] [PASSED] 0xA780 (ALDERLAKE_S)
[20:13:47] [PASSED] 0xA781 (ALDERLAKE_S)
[20:13:47] [PASSED] 0xA782 (ALDERLAKE_S)
[20:13:47] [PASSED] 0xA783 (ALDERLAKE_S)
[20:13:47] [PASSED] 0xA788 (ALDERLAKE_S)
[20:13:47] [PASSED] 0xA789 (ALDERLAKE_S)
[20:13:47] [PASSED] 0xA78A (ALDERLAKE_S)
[20:13:47] [PASSED] 0xA78B (ALDERLAKE_S)
[20:13:47] [PASSED] 0x4905 (DG1)
[20:13:47] [PASSED] 0x4906 (DG1)
[20:13:47] [PASSED] 0x4907 (DG1)
[20:13:47] [PASSED] 0x4908 (DG1)
[20:13:47] [PASSED] 0x4909 (DG1)
[20:13:47] [PASSED] 0x56C0 (DG2)
[20:13:47] [PASSED] 0x56C2 (DG2)
[20:13:47] [PASSED] 0x56C1 (DG2)
[20:13:47] [PASSED] 0x7D51 (METEORLAKE)
[20:13:47] [PASSED] 0x7DD1 (METEORLAKE)
[20:13:47] [PASSED] 0x7D41 (METEORLAKE)
[20:13:47] [PASSED] 0x7D67 (METEORLAKE)
[20:13:47] [PASSED] 0xB640 (METEORLAKE)
[20:13:47] [PASSED] 0x56A0 (DG2)
[20:13:47] [PASSED] 0x56A1 (DG2)
[20:13:47] [PASSED] 0x56A2 (DG2)
[20:13:47] [PASSED] 0x56BE (DG2)
[20:13:47] [PASSED] 0x56BF (DG2)
[20:13:47] [PASSED] 0x5690 (DG2)
[20:13:47] [PASSED] 0x5691 (DG2)
[20:13:47] [PASSED] 0x5692 (DG2)
[20:13:47] [PASSED] 0x56A5 (DG2)
[20:13:47] [PASSED] 0x56A6 (DG2)
[20:13:47] [PASSED] 0x56B0 (DG2)
[20:13:47] [PASSED] 0x56B1 (DG2)
[20:13:47] [PASSED] 0x56BA (DG2)
[20:13:47] [PASSED] 0x56BB (DG2)
[20:13:47] [PASSED] 0x56BC (DG2)
[20:13:47] [PASSED] 0x56BD (DG2)
[20:13:47] [PASSED] 0x5693 (DG2)
[20:13:47] [PASSED] 0x5694 (DG2)
[20:13:47] [PASSED] 0x5695 (DG2)
[20:13:47] [PASSED] 0x56A3 (DG2)
[20:13:47] [PASSED] 0x56A4 (DG2)
[20:13:47] [PASSED] 0x56B2 (DG2)
[20:13:47] [PASSED] 0x56B3 (DG2)
[20:13:47] [PASSED] 0x5696 (DG2)
[20:13:47] [PASSED] 0x5697 (DG2)
[20:13:47] [PASSED] 0xB69 (PVC)
[20:13:47] [PASSED] 0xB6E (PVC)
[20:13:47] [PASSED] 0xBD4 (PVC)
[20:13:47] [PASSED] 0xBD5 (PVC)
[20:13:47] [PASSED] 0xBD6 (PVC)
[20:13:47] [PASSED] 0xBD7 (PVC)
[20:13:47] [PASSED] 0xBD8 (PVC)
[20:13:47] [PASSED] 0xBD9 (PVC)
[20:13:47] [PASSED] 0xBDA (PVC)
[20:13:47] [PASSED] 0xBDB (PVC)
[20:13:47] [PASSED] 0xBE0 (PVC)
[20:13:47] [PASSED] 0xBE1 (PVC)
[20:13:47] [PASSED] 0xBE5 (PVC)
[20:13:47] [PASSED] 0x7D40 (METEORLAKE)
[20:13:47] [PASSED] 0x7D45 (METEORLAKE)
[20:13:47] [PASSED] 0x7D55 (METEORLAKE)
[20:13:47] [PASSED] 0x7D60 (METEORLAKE)
[20:13:47] [PASSED] 0x7DD5 (METEORLAKE)
[20:13:47] [PASSED] 0x6420 (LUNARLAKE)
[20:13:47] [PASSED] 0x64A0 (LUNARLAKE)
[20:13:47] [PASSED] 0x64B0 (LUNARLAKE)
[20:13:47] [PASSED] 0xE202 (BATTLEMAGE)
[20:13:47] [PASSED] 0xE209 (BATTLEMAGE)
[20:13:47] [PASSED] 0xE20B (BATTLEMAGE)
[20:13:47] [PASSED] 0xE20C (BATTLEMAGE)
[20:13:47] [PASSED] 0xE20D (BATTLEMAGE)
[20:13:47] [PASSED] 0xE210 (BATTLEMAGE)
[20:13:47] [PASSED] 0xE211 (BATTLEMAGE)
[20:13:47] [PASSED] 0xE212 (BATTLEMAGE)
[20:13:47] [PASSED] 0xE216 (BATTLEMAGE)
[20:13:47] [PASSED] 0xE220 (BATTLEMAGE)
[20:13:47] [PASSED] 0xE221 (BATTLEMAGE)
[20:13:47] [PASSED] 0xE222 (BATTLEMAGE)
[20:13:47] [PASSED] 0xE223 (BATTLEMAGE)
[20:13:47] [PASSED] 0xB080 (PANTHERLAKE)
[20:13:47] [PASSED] 0xB081 (PANTHERLAKE)
[20:13:47] [PASSED] 0xB082 (PANTHERLAKE)
[20:13:47] [PASSED] 0xB083 (PANTHERLAKE)
[20:13:47] [PASSED] 0xB084 (PANTHERLAKE)
[20:13:47] [PASSED] 0xB085 (PANTHERLAKE)
[20:13:47] [PASSED] 0xB086 (PANTHERLAKE)
[20:13:47] [PASSED] 0xB087 (PANTHERLAKE)
[20:13:47] [PASSED] 0xB08F (PANTHERLAKE)
[20:13:47] [PASSED] 0xB090 (PANTHERLAKE)
[20:13:47] [PASSED] 0xB0A0 (PANTHERLAKE)
[20:13:47] [PASSED] 0xB0B0 (PANTHERLAKE)
[20:13:47] [PASSED] 0xFD80 (PANTHERLAKE)
[20:13:47] [PASSED] 0xFD81 (PANTHERLAKE)
[20:13:47] [PASSED] 0xD740 (NOVALAKE_S)
[20:13:47] [PASSED] 0xD741 (NOVALAKE_S)
[20:13:47] [PASSED] 0xD742 (NOVALAKE_S)
[20:13:47] [PASSED] 0xD743 (NOVALAKE_S)
[20:13:47] [PASSED] 0xD745 (NOVALAKE_S)
[20:13:47] [PASSED] 0xD74A (NOVALAKE_S)
[20:13:47] [PASSED] 0xD74B (NOVALAKE_S)
[20:13:47] [PASSED] 0x674C (CRESCENTISLAND)
[20:13:47] [PASSED] 0x674D (CRESCENTISLAND)
[20:13:47] [PASSED] 0x674E (CRESCENTISLAND)
[20:13:47] [PASSED] 0x674F (CRESCENTISLAND)
[20:13:47] [PASSED] 0x6750 (CRESCENTISLAND)
[20:13:47] [PASSED] 0xD750 (NOVALAKE_P)
[20:13:47] [PASSED] 0xD751 (NOVALAKE_P)
[20:13:47] [PASSED] 0xD752 (NOVALAKE_P)
[20:13:47] [PASSED] 0xD753 (NOVALAKE_P)
[20:13:47] [PASSED] 0xD754 (NOVALAKE_P)
[20:13:47] [PASSED] 0xD755 (NOVALAKE_P)
[20:13:47] [PASSED] 0xD756 (NOVALAKE_P)
[20:13:47] [PASSED] 0xD757 (NOVALAKE_P)
[20:13:47] [PASSED] 0xD75F (NOVALAKE_P)
[20:13:47] =============== [PASSED] check_platform_desc ===============
[20:13:47] ===================== [PASSED] xe_pci ======================
[20:13:47] ============= xe_rtp_tables_test (5 subtests) ==============
[20:13:47] ================== xe_rtp_table_gt_test  ===================
[20:13:47] [PASSED] gt_was/14011060649
[20:13:47] [PASSED] gt_was/14011059788
[20:13:47] [PASSED] gt_was/14015795083
[20:13:47] [PASSED] gt_was/16021867713
[20:13:47] [PASSED] gt_was/14019449301
[20:13:47] [PASSED] gt_was/16028005424
[20:13:47] [PASSED] gt_was/14026578760
[20:13:47] [PASSED] gt_was/1409420604
[20:13:47] [PASSED] gt_was/1408615072
[20:13:47] [PASSED] gt_was/22010523718
[20:13:47] [PASSED] gt_was/14011006942
[20:13:47] [PASSED] gt_was/14014830051
[20:13:47] [PASSED] gt_was/18018781329
[20:13:47] [PASSED] gt_was/1509235366
[20:13:47] [PASSED] gt_was/18018781329
[20:13:47] [PASSED] gt_was/16016694945
[20:13:47] [PASSED] gt_was/14018575942
[20:13:47] [PASSED] gt_was/22016670082
[20:13:47] [PASSED] gt_was/22016670082
[20:13:47] [PASSED] gt_was/14017421178
[20:13:47] [PASSED] gt_was/16025250150
[20:13:47] [PASSED] gt_was/14021871409
[20:13:47] [PASSED] gt_was/16021865536
[20:13:47] [PASSED] gt_was/14021486841
[20:13:47] [PASSED] gt_was/14025160223
[20:13:47] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[20:13:47] [PASSED] gt_was/14025635424
[20:13:47] [PASSED] gt_was/16028005424
[20:13:47] ============== [PASSED] xe_rtp_table_gt_test ===============
[20:13:47] ================== xe_rtp_table_gt_test  ===================
[20:13:47] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[20:13:47] [PASSED] gt_tunings/Tuning: 32B Access Enable
[20:13:47] [PASSED] gt_tunings/Tuning: L3 cache
[20:13:47] [PASSED] gt_tunings/Tuning: L3 cache - media
[20:13:47] [PASSED] gt_tunings/Tuning: Compression Overfetch
[20:13:47] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[20:13:47] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[20:13:47] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[20:13:47] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[20:13:47] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[20:13:47] [PASSED] gt_tunings/Tuning: Stateless compression control
[20:13:47] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[20:13:47] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[20:13:47] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[20:13:47] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[20:13:47] ============== [PASSED] xe_rtp_table_gt_test ===============
[20:13:47] ================== xe_rtp_table_oob_test  ==================
[20:13:47] [PASSED] oob_was/1607983814
[20:13:47] [PASSED] oob_was/16010904313
[20:13:47] [PASSED] oob_was/18022495364
[20:13:47] [PASSED] oob_was/22012773006
[20:13:47] [PASSED] oob_was/14014475959
[20:13:47] [PASSED] oob_was/22011391025
[20:13:47] [PASSED] oob_was/22012727170
[20:13:47] [PASSED] oob_was/22012727685
[20:13:47] [PASSED] oob_was/22016596838
[20:13:47] [PASSED] oob_was/18020744125
[20:13:47] [PASSED] oob_was/1409600907
[20:13:47] [PASSED] oob_was/22014953428
[20:13:47] [PASSED] oob_was/16017236439
[20:13:47] [PASSED] oob_was/14019821291
[20:13:47] [PASSED] oob_was/14015076503
[20:13:47] [PASSED] oob_was/14018913170
[20:13:47] [PASSED] oob_was/14018094691
[20:13:47] [PASSED] oob_was/18024947630
[20:13:47] [PASSED] oob_was/16022287689
[20:13:47] [PASSED] oob_was/13011645652
[20:13:47] [PASSED] oob_was/14022293748
[20:13:47] [PASSED] oob_was/22019794406
[20:13:47] [PASSED] oob_was/22019338487
[20:13:47] [PASSED] oob_was/16023588340
[20:13:47] [PASSED] oob_was/14019789679
[20:13:47] [PASSED] oob_was/14022866841
[20:13:47] [PASSED] oob_was/16021333562
[20:13:47] [PASSED] oob_was/14016712196
[20:13:47] [PASSED] oob_was/14015568240
[20:13:47] [PASSED] oob_was/18013179988
[20:13:47] [PASSED] oob_was/1508761755
[20:13:47] [PASSED] oob_was/16023105232
[20:13:47] [PASSED] oob_was/16026508708
[20:13:47] [PASSED] oob_was/14020001231
[20:13:47] [PASSED] oob_was/16023683509
[20:13:47] [PASSED] oob_was/14025515070
[20:13:47] [PASSED] oob_was/15015404425_disable
[20:13:47] [PASSED] oob_was/16026007364
[20:13:47] [PASSED] oob_was/14020316580
[20:13:47] [PASSED] oob_was/14025883347
[20:13:47] [PASSED] oob_was/16029380221
[20:13:47] [PASSED] oob_was/22022079272
[20:13:47] [PASSED] oob_was/16029897822
[20:13:47] [PASSED] oob_was/14027054324
[20:13:47] ============== [PASSED] xe_rtp_table_oob_test ==============
[20:13:47] ================ xe_rtp_table_dev_oob_test  ================
[20:13:47] [PASSED] device_oob_was/22010954014
[20:13:47] [PASSED] device_oob_was/15015404425
[20:13:47] [PASSED] device_oob_was/22019338487_display
[20:13:47] [PASSED] device_oob_was/14022085890
[20:13:47] [PASSED] device_oob_was/14026539277
[20:13:47] [PASSED] device_oob_was/14026633728
[20:13:47] [PASSED] device_oob_was/14026746987
[20:13:47] [PASSED] device_oob_was/14026779378
[20:13:47] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[20:13:47] ========== xe_rtp_table_missing_upper_bound_test  ==========
[20:13:47] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[20:13:47] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[20:13:47] [PASSED] register_whitelist/1806527549
[20:13:47] [PASSED] register_whitelist/allow_read_ctx_timestamp
[20:13:47] [PASSED] register_whitelist/allow_read_queue_timestamp
[20:13:47] [PASSED] register_whitelist/16014440446
[20:13:47] [PASSED] register_whitelist/16017236439
[20:13:47] [PASSED] register_whitelist/16020183090
[20:13:47] [PASSED] register_whitelist/14024997852
[20:13:47] [PASSED] register_whitelist/14024997852
[20:13:47] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[20:13:47] =============== [PASSED] xe_rtp_tables_test ================
[20:13:47] =================== xe_rtp (3 subtests) ====================
[20:13:47] =================== xe_rtp_rules_tests  ====================
[20:13:47] [PASSED] no
[20:13:47] [PASSED] yes
[20:13:47] [PASSED] no-and-no
[20:13:47] [PASSED] no-and-yes
[20:13:47] [PASSED] yes-and-no
[20:13:47] [PASSED] yes-and-yes
[20:13:47] [PASSED] no-or-no
[20:13:47] [PASSED] no-or-yes
[20:13:47] [PASSED] yes-or-no
[20:13:47] [PASSED] yes-or-yes
[20:13:47] [PASSED] no-yes-or-yes-no
[20:13:47] [PASSED] no-yes-or-yes-yes
[20:13:47] [PASSED] yes-yes-or-no-yes
[20:13:47] [PASSED] yes-yes-or-yes-yes
[20:13:47] [PASSED] no-no-or-yes-or-no
[20:13:47] [PASSED] or
[20:13:47] [PASSED] or-yes
[20:13:47] [PASSED] or-no
[20:13:47] [PASSED] yes-or
[20:13:47] [PASSED] no-or
[20:13:47] [PASSED] no-or-or-yes
[20:13:47] [PASSED] yes-or-or-no
[20:13:47] [PASSED] no-or-or-no
[20:13:47] [PASSED] missing-context-engine-class
[20:13:47] [PASSED] missing-context-engine-class-or-yes
[20:13:47] [PASSED] missing-context-engine-class-or-or-yes
[20:13:47] =============== [PASSED] xe_rtp_rules_tests ================
[20:13:47] =============== xe_rtp_process_to_sr_tests  ================
[20:13:47] [PASSED] coalesce-same-reg
[20:13:47] [PASSED] coalesce-same-reg-literal-and-func
[20:13:47] [PASSED] no-match-no-add
[20:13:47] [PASSED] two-regs-two-entries
[20:13:47] [PASSED] clr-one-set-other
[20:13:47] [PASSED] set-field
[20:13:47] [PASSED] conflict-duplicate
[20:13:47] [PASSED] conflict-not-disjoint
[20:13:47] [PASSED] conflict-not-disjoint-literal-and-func
[20:13:47] [PASSED] conflict-reg-type
[20:13:47] [PASSED] bad-mcr-reg-forced-to-regular
[20:13:47] [PASSED] bad-regular-reg-forced-to-mcr
[20:13:47] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[20:13:47] ================== xe_rtp_process_tests  ===================
[20:13:47] [PASSED] active1
[20:13:47] [PASSED] active2
[20:13:47] [PASSED] active-inactive
[20:13:47] [PASSED] inactive-active
[20:13:47] [PASSED] inactive-active-inactive
[20:13:47] [PASSED] inactive-inactive-inactive
[20:13:47] ============== [PASSED] xe_rtp_process_tests ===============
[20:13:47] ===================== [PASSED] xe_rtp ======================
[20:13:47] ==================== xe_wa (1 subtest) =====================
[20:13:47] ======================== xe_wa_gt  =========================
[20:13:47] [PASSED] TIGERLAKE B0
[20:13:47] [PASSED] DG1 A0
[20:13:47] [PASSED] DG1 B0
[20:13:47] [PASSED] ALDERLAKE_S A0
[20:13:47] [PASSED] ALDERLAKE_S B0
[20:13:47] [PASSED] ALDERLAKE_S C0
[20:13:47] [PASSED] ALDERLAKE_S D0
[20:13:47] [PASSED] ALDERLAKE_P A0
[20:13:47] [PASSED] ALDERLAKE_P B0
[20:13:47] [PASSED] ALDERLAKE_P C0
[20:13:47] [PASSED] ALDERLAKE_S RPLS D0
[20:13:47] [PASSED] ALDERLAKE_P RPLU E0
[20:13:47] [PASSED] DG2 G10 C0
[20:13:47] [PASSED] DG2 G11 B1
[20:13:47] [PASSED] DG2 G12 A1
[20:13:47] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[20:13:47] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[20:13:47] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[20:13:47] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[20:13:47] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[20:13:47] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[20:13:47] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[20:13:47] ==================== [PASSED] xe_wa_gt =====================
[20:13:47] ====================== [PASSED] xe_wa ======================
[20:13:47] ============================================================
[20:13:47] Testing complete. Ran 789 tests: passed: 761, skipped: 28
[20:13:47] Elapsed time: 37.013s total, 4.330s configuring, 31.967s building, 0.681s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[20:13:48] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:13:49] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:14:14] Starting KUnit Kernel (1/1)...
[20:14:14] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:14:14] ============ drm_test_pick_cmdline (2 subtests) ============
[20:14:14] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[20:14:14] =============== drm_test_pick_cmdline_named  ===============
[20:14:14] [PASSED] NTSC
[20:14:14] [PASSED] NTSC-J
[20:14:14] [PASSED] PAL
[20:14:14] [PASSED] PAL-M
[20:14:14] =========== [PASSED] drm_test_pick_cmdline_named ===========
[20:14:14] ============== [PASSED] drm_test_pick_cmdline ==============
[20:14:14] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[20:14:14] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[20:14:14] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[20:14:14] =========== drm_validate_clone_mode (2 subtests) ===========
[20:14:14] ============== drm_test_check_in_clone_mode  ===============
[20:14:14] [PASSED] in_clone_mode
[20:14:14] [PASSED] not_in_clone_mode
[20:14:14] ========== [PASSED] drm_test_check_in_clone_mode ===========
[20:14:14] =============== drm_test_check_valid_clones  ===============
[20:14:14] [PASSED] not_in_clone_mode
[20:14:14] [PASSED] valid_clone
[20:14:14] [PASSED] invalid_clone
[20:14:14] =========== [PASSED] drm_test_check_valid_clones ===========
[20:14:14] ============= [PASSED] drm_validate_clone_mode =============
[20:14:14] ============= drm_validate_modeset (1 subtest) =============
[20:14:14] [PASSED] drm_test_check_connector_changed_modeset
[20:14:14] ============== [PASSED] drm_validate_modeset ===============
[20:14:14] ====== drm_test_bridge_get_current_state (1 subtest) =======
[20:14:14] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[20:14:14] ======== [PASSED] drm_test_bridge_get_current_state ========
[20:14:14] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[20:14:14] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[20:14:14] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[20:14:14] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[20:14:14] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[20:14:14] ============== drm_bridge_alloc (2 subtests) ===============
[20:14:14] [PASSED] drm_test_drm_bridge_alloc_basic
[20:14:14] [PASSED] drm_test_drm_bridge_alloc_get_put
[20:14:14] ================ [PASSED] drm_bridge_alloc =================
[20:14:14] ============= drm_bridge_bus_fmt (5 subtests) ==============
[20:14:14] [PASSED] drm_test_bridge_rgb_yuv_rgb
[20:14:14] [PASSED] drm_test_bridge_must_convert_to_yuv444
[20:14:14] [PASSED] drm_test_bridge_hdmi_auto_rgb
[20:14:14] [PASSED] drm_test_bridge_auto_first
[20:14:14] [PASSED] drm_test_bridge_rgb_yuv_no_path
[20:14:14] =============== [PASSED] drm_bridge_bus_fmt ================
[20:14:14] ============= drm_cmdline_parser (40 subtests) =============
[20:14:14] [PASSED] drm_test_cmdline_force_d_only
[20:14:14] [PASSED] drm_test_cmdline_force_D_only_dvi
[20:14:14] [PASSED] drm_test_cmdline_force_D_only_hdmi
[20:14:14] [PASSED] drm_test_cmdline_force_D_only_not_digital
[20:14:14] [PASSED] drm_test_cmdline_force_e_only
[20:14:14] [PASSED] drm_test_cmdline_res
[20:14:14] [PASSED] drm_test_cmdline_res_vesa
[20:14:14] [PASSED] drm_test_cmdline_res_vesa_rblank
[20:14:14] [PASSED] drm_test_cmdline_res_rblank
[20:14:14] [PASSED] drm_test_cmdline_res_bpp
[20:14:14] [PASSED] drm_test_cmdline_res_refresh
[20:14:14] [PASSED] drm_test_cmdline_res_bpp_refresh
[20:14:14] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[20:14:14] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[20:14:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[20:14:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[20:14:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[20:14:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[20:14:14] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[20:14:14] [PASSED] drm_test_cmdline_res_margins_force_on
[20:14:14] [PASSED] drm_test_cmdline_res_vesa_margins
[20:14:14] [PASSED] drm_test_cmdline_name
[20:14:14] [PASSED] drm_test_cmdline_name_bpp
[20:14:14] [PASSED] drm_test_cmdline_name_option
[20:14:14] [PASSED] drm_test_cmdline_name_bpp_option
[20:14:14] [PASSED] drm_test_cmdline_rotate_0
[20:14:14] [PASSED] drm_test_cmdline_rotate_90
[20:14:14] [PASSED] drm_test_cmdline_rotate_180
[20:14:14] [PASSED] drm_test_cmdline_rotate_270
[20:14:14] [PASSED] drm_test_cmdline_hmirror
[20:14:14] [PASSED] drm_test_cmdline_vmirror
[20:14:14] [PASSED] drm_test_cmdline_margin_options
[20:14:14] [PASSED] drm_test_cmdline_multiple_options
[20:14:14] [PASSED] drm_test_cmdline_bpp_extra_and_option
[20:14:14] [PASSED] drm_test_cmdline_extra_and_option
[20:14:14] [PASSED] drm_test_cmdline_freestanding_options
[20:14:14] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[20:14:14] [PASSED] drm_test_cmdline_panel_orientation
[20:14:14] ================ drm_test_cmdline_invalid  =================
[20:14:14] [PASSED] margin_only
[20:14:14] [PASSED] interlace_only
[20:14:14] [PASSED] res_missing_x
[20:14:14] [PASSED] res_missing_y
[20:14:14] [PASSED] res_bad_y
[20:14:14] [PASSED] res_missing_y_bpp
[20:14:14] [PASSED] res_bad_bpp
[20:14:14] [PASSED] res_bad_refresh
[20:14:14] [PASSED] res_bpp_refresh_force_on_off
[20:14:14] [PASSED] res_invalid_mode
[20:14:14] [PASSED] res_bpp_wrong_place_mode
[20:14:14] [PASSED] name_bpp_refresh
[20:14:14] [PASSED] name_refresh
[20:14:14] [PASSED] name_refresh_wrong_mode
[20:14:14] [PASSED] name_refresh_invalid_mode
[20:14:14] [PASSED] rotate_multiple
[20:14:14] [PASSED] rotate_invalid_val
[20:14:14] [PASSED] rotate_truncated
[20:14:14] [PASSED] invalid_option
[20:14:14] [PASSED] invalid_tv_option
[20:14:14] [PASSED] truncated_tv_option
[20:14:14] ============ [PASSED] drm_test_cmdline_invalid =============
[20:14:14] =============== drm_test_cmdline_tv_options  ===============
[20:14:14] [PASSED] NTSC
[20:14:14] [PASSED] NTSC_443
[20:14:14] [PASSED] NTSC_J
[20:14:14] [PASSED] PAL
[20:14:14] [PASSED] PAL_M
[20:14:14] [PASSED] PAL_N
[20:14:14] [PASSED] SECAM
[20:14:14] [PASSED] MONO_525
[20:14:14] [PASSED] MONO_625
[20:14:14] =========== [PASSED] drm_test_cmdline_tv_options ===========
[20:14:14] =============== [PASSED] drm_cmdline_parser ================
[20:14:14] ========== drmm_connector_hdmi_init (20 subtests) ==========
[20:14:14] [PASSED] drm_test_connector_hdmi_init_valid
[20:14:14] [PASSED] drm_test_connector_hdmi_init_bpc_8
[20:14:14] [PASSED] drm_test_connector_hdmi_init_bpc_10
[20:14:14] [PASSED] drm_test_connector_hdmi_init_bpc_12
[20:14:14] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[20:14:14] [PASSED] drm_test_connector_hdmi_init_bpc_null
[20:14:14] [PASSED] drm_test_connector_hdmi_init_formats_empty
[20:14:14] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[20:14:14] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[20:14:14] [PASSED] supported_formats=0x9 yuv420_allowed=1
[20:14:14] [PASSED] supported_formats=0x9 yuv420_allowed=0
[20:14:14] [PASSED] supported_formats=0x5 yuv420_allowed=1
[20:14:14] [PASSED] supported_formats=0x5 yuv420_allowed=0
[20:14:14] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[20:14:14] [PASSED] drm_test_connector_hdmi_init_null_ddc
[20:14:14] [PASSED] drm_test_connector_hdmi_init_null_product
[20:14:14] [PASSED] drm_test_connector_hdmi_init_null_vendor
[20:14:14] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[20:14:14] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[20:14:14] [PASSED] drm_test_connector_hdmi_init_product_valid
[20:14:14] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[20:14:14] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[20:14:14] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[20:14:14] ========= drm_test_connector_hdmi_init_type_valid  =========
[20:14:14] [PASSED] HDMI-A
[20:14:14] [PASSED] HDMI-B
[20:14:14] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[20:14:14] ======== drm_test_connector_hdmi_init_type_invalid  ========
[20:14:14] [PASSED] Unknown
[20:14:14] [PASSED] VGA
[20:14:14] [PASSED] DVI-I
[20:14:14] [PASSED] DVI-D
[20:14:14] [PASSED] DVI-A
[20:14:14] [PASSED] Composite
[20:14:14] [PASSED] SVIDEO
[20:14:14] [PASSED] LVDS
[20:14:14] [PASSED] Component
[20:14:14] [PASSED] DIN
[20:14:14] [PASSED] DP
[20:14:14] [PASSED] TV
[20:14:14] [PASSED] eDP
[20:14:14] [PASSED] Virtual
[20:14:14] [PASSED] DSI
[20:14:14] [PASSED] DPI
[20:14:14] [PASSED] Writeback
[20:14:14] [PASSED] SPI
[20:14:14] [PASSED] USB
[20:14:14] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[20:14:14] ============ [PASSED] drmm_connector_hdmi_init =============
[20:14:14] ============= drmm_connector_init (3 subtests) =============
[20:14:14] [PASSED] drm_test_drmm_connector_init
[20:14:14] [PASSED] drm_test_drmm_connector_init_null_ddc
[20:14:14] ========= drm_test_drmm_connector_init_type_valid  =========
[20:14:14] [PASSED] Unknown
[20:14:14] [PASSED] VGA
[20:14:14] [PASSED] DVI-I
[20:14:14] [PASSED] DVI-D
[20:14:14] [PASSED] DVI-A
[20:14:14] [PASSED] Composite
[20:14:14] [PASSED] SVIDEO
[20:14:14] [PASSED] LVDS
[20:14:14] [PASSED] Component
[20:14:14] [PASSED] DIN
[20:14:14] [PASSED] DP
[20:14:14] [PASSED] HDMI-A
[20:14:14] [PASSED] HDMI-B
[20:14:14] [PASSED] TV
[20:14:14] [PASSED] eDP
[20:14:14] [PASSED] Virtual
[20:14:14] [PASSED] DSI
[20:14:14] [PASSED] DPI
[20:14:14] [PASSED] Writeback
[20:14:14] [PASSED] SPI
[20:14:14] [PASSED] USB
[20:14:14] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[20:14:14] =============== [PASSED] drmm_connector_init ===============
[20:14:14] ========= drm_connector_dynamic_init (6 subtests) ==========
[20:14:14] [PASSED] drm_test_drm_connector_dynamic_init
[20:14:14] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[20:14:14] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[20:14:14] [PASSED] drm_test_drm_connector_dynamic_init_properties
[20:14:14] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[20:14:14] [PASSED] Unknown
[20:14:14] [PASSED] VGA
[20:14:14] [PASSED] DVI-I
[20:14:14] [PASSED] DVI-D
[20:14:14] [PASSED] DVI-A
[20:14:14] [PASSED] Composite
[20:14:14] [PASSED] SVIDEO
[20:14:14] [PASSED] LVDS
[20:14:14] [PASSED] Component
[20:14:14] [PASSED] DIN
[20:14:14] [PASSED] DP
[20:14:14] [PASSED] HDMI-A
[20:14:14] [PASSED] HDMI-B
[20:14:14] [PASSED] TV
[20:14:14] [PASSED] eDP
[20:14:14] [PASSED] Virtual
[20:14:14] [PASSED] DSI
[20:14:14] [PASSED] DPI
[20:14:14] [PASSED] Writeback
[20:14:14] [PASSED] SPI
[20:14:14] [PASSED] USB
[20:14:14] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[20:14:14] ======== drm_test_drm_connector_dynamic_init_name  =========
[20:14:14] [PASSED] Unknown
[20:14:14] [PASSED] VGA
[20:14:14] [PASSED] DVI-I
[20:14:14] [PASSED] DVI-D
[20:14:14] [PASSED] DVI-A
[20:14:14] [PASSED] Composite
[20:14:14] [PASSED] SVIDEO
[20:14:14] [PASSED] LVDS
[20:14:14] [PASSED] Component
[20:14:14] [PASSED] DIN
[20:14:14] [PASSED] DP
[20:14:14] [PASSED] HDMI-A
[20:14:14] [PASSED] HDMI-B
[20:14:14] [PASSED] TV
[20:14:14] [PASSED] eDP
[20:14:14] [PASSED] Virtual
[20:14:14] [PASSED] DSI
[20:14:14] [PASSED] DPI
[20:14:14] [PASSED] Writeback
[20:14:14] [PASSED] SPI
[20:14:14] [PASSED] USB
[20:14:14] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[20:14:14] =========== [PASSED] drm_connector_dynamic_init ============
[20:14:14] ==== drm_connector_dynamic_register_early (4 subtests) =====
[20:14:14] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[20:14:14] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[20:14:14] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[20:14:14] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[20:14:14] ====== [PASSED] drm_connector_dynamic_register_early =======
[20:14:14] ======= drm_connector_dynamic_register (7 subtests) ========
[20:14:14] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[20:14:14] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[20:14:14] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[20:14:14] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[20:14:14] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[20:14:14] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[20:14:14] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[20:14:14] ========= [PASSED] drm_connector_dynamic_register ==========
[20:14:14] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[20:14:14] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[20:14:14] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[20:14:14] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[20:14:14] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[20:14:14] ========== drm_test_get_tv_mode_from_name_valid  ===========
[20:14:14] [PASSED] NTSC
[20:14:14] [PASSED] NTSC-443
[20:14:14] [PASSED] NTSC-J
[20:14:14] [PASSED] PAL
[20:14:14] [PASSED] PAL-M
[20:14:14] [PASSED] PAL-N
[20:14:14] [PASSED] SECAM
[20:14:14] [PASSED] Mono
[20:14:14] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[20:14:14] [PASSED] drm_test_get_tv_mode_from_name_truncated
[20:14:14] ============ [PASSED] drm_get_tv_mode_from_name ============
[20:14:14] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[20:14:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[20:14:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[20:14:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[20:14:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[20:14:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[20:14:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[20:14:14] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[20:14:14] [PASSED] VIC 96
[20:14:14] [PASSED] VIC 97
[20:14:14] [PASSED] VIC 101
[20:14:14] [PASSED] VIC 102
[20:14:14] [PASSED] VIC 106
[20:14:14] [PASSED] VIC 107
[20:14:14] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[20:14:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[20:14:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[20:14:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[20:14:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[20:14:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[20:14:14] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[20:14:14] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[20:14:14] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[20:14:14] [PASSED] Automatic
[20:14:14] [PASSED] Full
[20:14:14] [PASSED] Limited 16:235
[20:14:14] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[20:14:14] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[20:14:14] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[20:14:14] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[20:14:14] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[20:14:14] [PASSED] RGB
[20:14:14] [PASSED] YUV 4:2:0
[20:14:14] [PASSED] YUV 4:2:2
[20:14:14] [PASSED] YUV 4:4:4
[20:14:14] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[20:14:14] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[20:14:14] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[20:14:14] ============= drm_damage_helper (21 subtests) ==============
[20:14:14] [PASSED] drm_test_damage_iter_no_damage
[20:14:14] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[20:14:14] [PASSED] drm_test_damage_iter_no_damage_src_moved
[20:14:14] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[20:14:14] [PASSED] drm_test_damage_iter_no_damage_not_visible
[20:14:14] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[20:14:14] [PASSED] drm_test_damage_iter_no_damage_no_fb
[20:14:14] [PASSED] drm_test_damage_iter_simple_damage
[20:14:14] [PASSED] drm_test_damage_iter_single_damage
[20:14:14] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[20:14:14] [PASSED] drm_test_damage_iter_single_damage_outside_src
[20:14:14] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[20:14:14] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[20:14:14] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[20:14:14] [PASSED] drm_test_damage_iter_single_damage_src_moved
[20:14:14] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[20:14:14] [PASSED] drm_test_damage_iter_damage
[20:14:14] [PASSED] drm_test_damage_iter_damage_one_intersect
[20:14:14] [PASSED] drm_test_damage_iter_damage_one_outside
[20:14:14] [PASSED] drm_test_damage_iter_damage_src_moved
[20:14:14] [PASSED] drm_test_damage_iter_damage_not_visible
[20:14:14] ================ [PASSED] drm_damage_helper ================
[20:14:14] ============== drm_dp_mst_helper (3 subtests) ==============
[20:14:14] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[20:14:14] [PASSED] Clock 154000 BPP 30 DSC disabled
[20:14:14] [PASSED] Clock 234000 BPP 30 DSC disabled
[20:14:14] [PASSED] Clock 297000 BPP 24 DSC disabled
[20:14:14] [PASSED] Clock 332880 BPP 24 DSC enabled
[20:14:14] [PASSED] Clock 324540 BPP 24 DSC enabled
[20:14:14] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[20:14:14] ============== drm_test_dp_mst_calc_pbn_div  ===============
[20:14:14] [PASSED] Link rate 2000000 lane count 4
[20:14:14] [PASSED] Link rate 2000000 lane count 2
[20:14:14] [PASSED] Link rate 2000000 lane count 1
[20:14:14] [PASSED] Link rate 1350000 lane count 4
[20:14:14] [PASSED] Link rate 1350000 lane count 2
[20:14:14] [PASSED] Link rate 1350000 lane count 1
[20:14:14] [PASSED] Link rate 1000000 lane count 4
[20:14:14] [PASSED] Link rate 1000000 lane count 2
[20:14:14] [PASSED] Link rate 1000000 lane count 1
[20:14:14] [PASSED] Link rate 810000 lane count 4
[20:14:14] [PASSED] Link rate 810000 lane count 2
[20:14:14] [PASSED] Link rate 810000 lane count 1
[20:14:14] [PASSED] Link rate 540000 lane count 4
[20:14:14] [PASSED] Link rate 540000 lane count 2
[20:14:14] [PASSED] Link rate 540000 lane count 1
[20:14:14] [PASSED] Link rate 270000 lane count 4
[20:14:14] [PASSED] Link rate 270000 lane count 2
[20:14:14] [PASSED] Link rate 270000 lane count 1
[20:14:14] [PASSED] Link rate 162000 lane count 4
[20:14:14] [PASSED] Link rate 162000 lane count 2
[20:14:14] [PASSED] Link rate 162000 lane count 1
[20:14:14] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[20:14:14] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[20:14:14] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[20:14:14] [PASSED] DP_POWER_UP_PHY with port number
[20:14:14] [PASSED] DP_POWER_DOWN_PHY with port number
[20:14:14] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[20:14:14] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[20:14:14] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[20:14:14] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[20:14:14] [PASSED] DP_QUERY_PAYLOAD with port number
[20:14:14] [PASSED] DP_QUERY_PAYLOAD with VCPI
[20:14:14] [PASSED] DP_REMOTE_DPCD_READ with port number
[20:14:14] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[20:14:14] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[20:14:14] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[20:14:14] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[20:14:14] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[20:14:14] [PASSED] DP_REMOTE_I2C_READ with port number
[20:14:14] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[20:14:14] [PASSED] DP_REMOTE_I2C_READ with transactions array
[20:14:14] [PASSED] DP_REMOTE_I2C_WRITE with port number
[20:14:14] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[20:14:14] [PASSED] DP_REMOTE_I2C_WRITE with data array
[20:14:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[20:14:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[20:14:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[20:14:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[20:14:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[20:14:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[20:14:14] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[20:14:14] ================ [PASSED] drm_dp_mst_helper ================
[20:14:14] ================== drm_exec (7 subtests) ===================
[20:14:14] [PASSED] sanitycheck
[20:14:14] [PASSED] test_lock
[20:14:14] [PASSED] test_lock_unlock
[20:14:14] [PASSED] test_duplicates
[20:14:14] [PASSED] test_prepare
[20:14:14] [PASSED] test_prepare_array
[20:14:14] [PASSED] test_multiple_loops
[20:14:14] ==================== [PASSED] drm_exec =====================
[20:14:14] =========== drm_format_helper_test (17 subtests) ===========
[20:14:14] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[20:14:14] [PASSED] single_pixel_source_buffer
[20:14:14] [PASSED] single_pixel_clip_rectangle
[20:14:14] [PASSED] well_known_colors
[20:14:14] [PASSED] destination_pitch
[20:14:14] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[20:14:14] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[20:14:14] [PASSED] single_pixel_source_buffer
[20:14:14] [PASSED] single_pixel_clip_rectangle
[20:14:14] [PASSED] well_known_colors
[20:14:14] [PASSED] destination_pitch
[20:14:14] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[20:14:14] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[20:14:14] [PASSED] single_pixel_source_buffer
[20:14:14] [PASSED] single_pixel_clip_rectangle
[20:14:14] [PASSED] well_known_colors
[20:14:14] [PASSED] destination_pitch
[20:14:14] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[20:14:14] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[20:14:14] [PASSED] single_pixel_source_buffer
[20:14:14] [PASSED] single_pixel_clip_rectangle
[20:14:14] [PASSED] well_known_colors
[20:14:14] [PASSED] destination_pitch
[20:14:14] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[20:14:14] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[20:14:14] [PASSED] single_pixel_source_buffer
[20:14:14] [PASSED] single_pixel_clip_rectangle
[20:14:14] [PASSED] well_known_colors
[20:14:14] [PASSED] destination_pitch
[20:14:14] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[20:14:14] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[20:14:14] [PASSED] single_pixel_source_buffer
[20:14:14] [PASSED] single_pixel_clip_rectangle
[20:14:14] [PASSED] well_known_colors
[20:14:14] [PASSED] destination_pitch
[20:14:14] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[20:14:14] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[20:14:14] [PASSED] single_pixel_source_buffer
[20:14:14] [PASSED] single_pixel_clip_rectangle
[20:14:14] [PASSED] well_known_colors
[20:14:14] [PASSED] destination_pitch
[20:14:14] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[20:14:14] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[20:14:14] [PASSED] single_pixel_source_buffer
[20:14:14] [PASSED] single_pixel_clip_rectangle
[20:14:14] [PASSED] well_known_colors
[20:14:14] [PASSED] destination_pitch
[20:14:14] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[20:14:14] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[20:14:14] [PASSED] single_pixel_source_buffer
[20:14:14] [PASSED] single_pixel_clip_rectangle
[20:14:14] [PASSED] well_known_colors
[20:14:14] [PASSED] destination_pitch
[20:14:14] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[20:14:14] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[20:14:14] [PASSED] single_pixel_source_buffer
[20:14:14] [PASSED] single_pixel_clip_rectangle
[20:14:14] [PASSED] well_known_colors
[20:14:14] [PASSED] destination_pitch
[20:14:14] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[20:14:14] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[20:14:14] [PASSED] single_pixel_source_buffer
[20:14:14] [PASSED] single_pixel_clip_rectangle
[20:14:14] [PASSED] well_known_colors
[20:14:14] [PASSED] destination_pitch
[20:14:14] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[20:14:14] ============== drm_test_fb_xrgb8888_to_mono  ===============
[20:14:14] [PASSED] single_pixel_source_buffer
[20:14:14] [PASSED] single_pixel_clip_rectangle
[20:14:14] [PASSED] well_known_colors
[20:14:14] [PASSED] destination_pitch
[20:14:14] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[20:14:14] ==================== drm_test_fb_swab  =====================
[20:14:14] [PASSED] single_pixel_source_buffer
[20:14:14] [PASSED] single_pixel_clip_rectangle
[20:14:14] [PASSED] well_known_colors
[20:14:14] [PASSED] destination_pitch
[20:14:14] ================ [PASSED] drm_test_fb_swab =================
[20:14:14] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[20:14:14] [PASSED] single_pixel_source_buffer
[20:14:14] [PASSED] single_pixel_clip_rectangle
[20:14:14] [PASSED] well_known_colors
[20:14:14] [PASSED] destination_pitch
[20:14:14] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[20:14:14] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[20:14:14] [PASSED] single_pixel_source_buffer
[20:14:14] [PASSED] single_pixel_clip_rectangle
[20:14:14] [PASSED] well_known_colors
[20:14:14] [PASSED] destination_pitch
[20:14:14] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[20:14:14] ================= drm_test_fb_clip_offset  =================
[20:14:14] [PASSED] pass through
[20:14:14] [PASSED] horizontal offset
[20:14:14] [PASSED] vertical offset
[20:14:14] [PASSED] horizontal and vertical offset
[20:14:14] [PASSED] horizontal offset (custom pitch)
[20:14:14] [PASSED] vertical offset (custom pitch)
[20:14:14] [PASSED] horizontal and vertical offset (custom pitch)
[20:14:14] ============= [PASSED] drm_test_fb_clip_offset =============
[20:14:14] =================== drm_test_fb_memcpy  ====================
[20:14:14] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[20:14:14] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[20:14:14] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[20:14:14] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[20:14:14] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[20:14:14] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[20:14:14] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[20:14:14] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[20:14:14] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[20:14:14] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[20:14:14] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[20:14:14] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[20:14:14] =============== [PASSED] drm_test_fb_memcpy ================
[20:14:14] ============= [PASSED] drm_format_helper_test ==============
[20:14:14] ================= drm_format (18 subtests) =================
[20:14:14] [PASSED] drm_test_format_block_width_invalid
[20:14:14] [PASSED] drm_test_format_block_width_one_plane
[20:14:14] [PASSED] drm_test_format_block_width_two_plane
[20:14:14] [PASSED] drm_test_format_block_width_three_plane
[20:14:14] [PASSED] drm_test_format_block_width_tiled
[20:14:14] [PASSED] drm_test_format_block_height_invalid
[20:14:14] [PASSED] drm_test_format_block_height_one_plane
[20:14:14] [PASSED] drm_test_format_block_height_two_plane
[20:14:14] [PASSED] drm_test_format_block_height_three_plane
[20:14:14] [PASSED] drm_test_format_block_height_tiled
[20:14:14] [PASSED] drm_test_format_min_pitch_invalid
[20:14:14] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[20:14:14] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[20:14:14] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[20:14:14] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[20:14:14] [PASSED] drm_test_format_min_pitch_two_plane
[20:14:14] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[20:14:14] [PASSED] drm_test_format_min_pitch_tiled
[20:14:14] =================== [PASSED] drm_format ====================
[20:14:14] ============== drm_framebuffer (10 subtests) ===============
[20:14:14] ========== drm_test_framebuffer_check_src_coords  ==========
[20:14:14] [PASSED] Success: source fits into fb
[20:14:14] [PASSED] Fail: overflowing fb with x-axis coordinate
[20:14:14] [PASSED] Fail: overflowing fb with y-axis coordinate
[20:14:14] [PASSED] Fail: overflowing fb with source width
[20:14:14] [PASSED] Fail: overflowing fb with source height
[20:14:14] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[20:14:14] [PASSED] drm_test_framebuffer_cleanup
[20:14:14] =============== drm_test_framebuffer_create  ===============
[20:14:14] [PASSED] ABGR8888 normal sizes
[20:14:14] [PASSED] ABGR8888 max sizes
[20:14:14] [PASSED] ABGR8888 pitch greater than min required
[20:14:14] [PASSED] ABGR8888 pitch less than min required
[20:14:14] [PASSED] ABGR8888 Invalid width
[20:14:14] [PASSED] ABGR8888 Invalid buffer handle
[20:14:14] [PASSED] No pixel format
[20:14:14] [PASSED] ABGR8888 Width 0
[20:14:14] [PASSED] ABGR8888 Height 0
[20:14:14] [PASSED] ABGR8888 Out of bound height * pitch combination
[20:14:14] [PASSED] ABGR8888 Large buffer offset
[20:14:14] [PASSED] ABGR8888 Buffer offset for inexistent plane
[20:14:14] [PASSED] ABGR8888 Invalid flag
[20:14:14] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[20:14:14] [PASSED] ABGR8888 Valid buffer modifier
[20:14:14] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[20:14:14] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[20:14:14] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[20:14:14] [PASSED] NV12 Normal sizes
[20:14:14] [PASSED] NV12 Max sizes
[20:14:14] [PASSED] NV12 Invalid pitch
[20:14:14] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[20:14:14] [PASSED] NV12 different  modifier per-plane
[20:14:14] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[20:14:14] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[20:14:14] [PASSED] NV12 Modifier for inexistent plane
[20:14:14] [PASSED] NV12 Handle for inexistent plane
[20:14:14] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[20:14:14] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[20:14:14] [PASSED] YVU420 Normal sizes
[20:14:14] [PASSED] YVU420 Max sizes
[20:14:14] [PASSED] YVU420 Invalid pitch
[20:14:14] [PASSED] YVU420 Different pitches
[20:14:14] [PASSED] YVU420 Different buffer offsets/pitches
[20:14:14] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[20:14:14] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[20:14:14] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[20:14:14] [PASSED] YVU420 Valid modifier
[20:14:14] [PASSED] YVU420 Different modifiers per plane
[20:14:14] [PASSED] YVU420 Modifier for inexistent plane
[20:14:14] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[20:14:14] [PASSED] X0L2 Normal sizes
[20:14:14] [PASSED] X0L2 Max sizes
[20:14:14] [PASSED] X0L2 Invalid pitch
[20:14:14] [PASSED] X0L2 Pitch greater than minimum required
[20:14:14] [PASSED] X0L2 Handle for inexistent plane
[20:14:14] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[20:14:14] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[20:14:14] [PASSED] X0L2 Valid modifier
[20:14:14] [PASSED] X0L2 Modifier for inexistent plane
[20:14:14] =========== [PASSED] drm_test_framebuffer_create ===========
[20:14:14] [PASSED] drm_test_framebuffer_free
[20:14:14] [PASSED] drm_test_framebuffer_init
[20:14:14] [PASSED] drm_test_framebuffer_init_bad_format
[20:14:14] [PASSED] drm_test_framebuffer_init_dev_mismatch
[20:14:14] [PASSED] drm_test_framebuffer_lookup
[20:14:14] [PASSED] drm_test_framebuffer_lookup_inexistent
[20:14:14] [PASSED] drm_test_framebuffer_modifiers_not_supported
[20:14:14] ================= [PASSED] drm_framebuffer =================
[20:14:14] ================ drm_gem_shmem (8 subtests) ================
[20:14:14] [PASSED] drm_gem_shmem_test_obj_create
[20:14:14] [PASSED] drm_gem_shmem_test_obj_create_private
[20:14:14] [PASSED] drm_gem_shmem_test_pin_pages
[20:14:14] [PASSED] drm_gem_shmem_test_vmap
[20:14:14] [PASSED] drm_gem_shmem_test_get_sg_table
[20:14:14] [PASSED] drm_gem_shmem_test_get_pages_sgt
[20:14:14] [PASSED] drm_gem_shmem_test_madvise
[20:14:14] [PASSED] drm_gem_shmem_test_purge
[20:14:14] ================== [PASSED] drm_gem_shmem ==================
[20:14:14] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[20:14:14] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[20:14:14] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[20:14:14] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[20:14:14] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[20:14:14] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[20:14:14] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[20:14:14] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[20:14:14] [PASSED] Automatic
[20:14:14] [PASSED] Full
[20:14:14] [PASSED] Limited 16:235
[20:14:14] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[20:14:14] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[20:14:14] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[20:14:14] [PASSED] drm_test_check_disable_connector
[20:14:14] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[20:14:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[20:14:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[20:14:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[20:14:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[20:14:14] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[20:14:14] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[20:14:14] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[20:14:14] [PASSED] drm_test_check_output_bpc_dvi
[20:14:14] [PASSED] drm_test_check_output_bpc_format_vic_1
[20:14:14] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[20:14:14] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[20:14:14] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[20:14:14] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[20:14:14] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[20:14:14] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[20:14:14] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[20:14:14] ============ drm_test_check_hdmi_color_format  =============
[20:14:14] [PASSED] AUTO -> RGB
[20:14:14] [PASSED] YCBCR422 -> YUV422
[20:14:14] [PASSED] YCBCR420 -> YUV420
[20:14:14] [PASSED] YCBCR444 -> YUV444
[20:14:14] [PASSED] RGB -> RGB
[20:14:14] ======== [PASSED] drm_test_check_hdmi_color_format =========
[20:14:14] ======== drm_test_check_hdmi_color_format_420_only  ========
[20:14:14] [PASSED] RGB should fail
[20:14:14] [PASSED] YUV444 should fail
[20:14:14] [PASSED] YUV422 should fail
[20:14:14] [PASSED] YUV420 should work
[20:14:14] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[20:14:14] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[20:14:14] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[20:14:14] [PASSED] drm_test_check_broadcast_rgb_value
[20:14:14] [PASSED] drm_test_check_bpc_8_value
[20:14:14] [PASSED] drm_test_check_bpc_10_value
[20:14:14] [PASSED] drm_test_check_bpc_12_value
[20:14:14] [PASSED] drm_test_check_format_value
[20:14:14] [PASSED] drm_test_check_tmds_char_value
[20:14:14] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[20:14:14] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[20:14:14] [PASSED] drm_test_check_mode_valid
[20:14:14] [PASSED] drm_test_check_mode_valid_reject
[20:14:14] [PASSED] drm_test_check_mode_valid_reject_rate
[20:14:14] [PASSED] drm_test_check_mode_valid_reject_max_clock
[20:14:14] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[20:14:14] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[20:14:14] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[20:14:14] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[20:14:14] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[20:14:14] [PASSED] drm_test_check_infoframes
[20:14:14] [PASSED] drm_test_check_reject_avi_infoframe
[20:14:14] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[20:14:14] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[20:14:14] [PASSED] drm_test_check_reject_audio_infoframe
[20:14:14] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[20:14:14] ================= drm_managed (2 subtests) =================
[20:14:14] [PASSED] drm_test_managed_release_action
[20:14:14] [PASSED] drm_test_managed_run_action
[20:14:14] =================== [PASSED] drm_managed ===================
[20:14:14] =================== drm_mm (6 subtests) ====================
[20:14:14] [PASSED] drm_test_mm_init
[20:14:14] [PASSED] drm_test_mm_debug
[20:14:14] [PASSED] drm_test_mm_align32
[20:14:14] [PASSED] drm_test_mm_align64
[20:14:14] [PASSED] drm_test_mm_lowest
[20:14:14] [PASSED] drm_test_mm_highest
[20:14:14] ===================== [PASSED] drm_mm ======================
[20:14:14] ============= drm_modes_analog_tv (5 subtests) =============
[20:14:14] [PASSED] drm_test_modes_analog_tv_mono_576i
[20:14:14] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[20:14:14] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[20:14:14] [PASSED] drm_test_modes_analog_tv_pal_576i
[20:14:14] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[20:14:14] =============== [PASSED] drm_modes_analog_tv ===============
[20:14:14] ============== drm_plane_helper (2 subtests) ===============
[20:14:14] =============== drm_test_check_plane_state  ================
[20:14:14] [PASSED] clipping_simple
[20:14:14] [PASSED] clipping_rotate_reflect
[20:14:14] [PASSED] positioning_simple
[20:14:14] [PASSED] upscaling
[20:14:14] [PASSED] downscaling
[20:14:14] [PASSED] rounding1
[20:14:14] [PASSED] rounding2
[20:14:14] [PASSED] rounding3
[20:14:14] [PASSED] rounding4
[20:14:14] =========== [PASSED] drm_test_check_plane_state ============
[20:14:14] =========== drm_test_check_invalid_plane_state  ============
[20:14:14] [PASSED] positioning_invalid
[20:14:14] [PASSED] upscaling_invalid
[20:14:14] [PASSED] downscaling_invalid
[20:14:14] ======= [PASSED] drm_test_check_invalid_plane_state ========
[20:14:14] ================ [PASSED] drm_plane_helper =================
[20:14:14] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[20:14:14] ====== drm_test_connector_helper_tv_get_modes_check  =======
[20:14:14] [PASSED] None
[20:14:14] [PASSED] PAL
[20:14:14] [PASSED] NTSC
[20:14:14] [PASSED] Both, NTSC Default
[20:14:14] [PASSED] Both, PAL Default
[20:14:14] [PASSED] Both, NTSC Default, with PAL on command-line
[20:14:14] [PASSED] Both, PAL Default, with NTSC on command-line
[20:14:14] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[20:14:14] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[20:14:14] ================== drm_rect (9 subtests) ===================
[20:14:14] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[20:14:14] [PASSED] drm_test_rect_clip_scaled_not_clipped
[20:14:14] [PASSED] drm_test_rect_clip_scaled_clipped
[20:14:14] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[20:14:14] ================= drm_test_rect_intersect  =================
[20:14:14] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[20:14:14] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[20:14:14] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[20:14:14] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[20:14:14] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[20:14:14] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[20:14:14] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[20:14:14] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[20:14:14] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[20:14:14] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[20:14:14] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[20:14:14] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[20:14:14] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[20:14:14] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[20:14:14] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[20:14:14] ============= [PASSED] drm_test_rect_intersect =============
[20:14:14] ================ drm_test_rect_calc_hscale  ================
[20:14:14] [PASSED] normal use
[20:14:14] [PASSED] out of max range
[20:14:14] [PASSED] out of min range
[20:14:14] [PASSED] zero dst
[20:14:14] [PASSED] negative src
[20:14:14] [PASSED] negative dst
[20:14:14] ============ [PASSED] drm_test_rect_calc_hscale ============
[20:14:14] ================ drm_test_rect_calc_vscale  ================
[20:14:14] [PASSED] normal use
[20:14:14] [PASSED] out of max range
[20:14:14] [PASSED] out of min range
[20:14:14] [PASSED] zero dst
[20:14:14] [PASSED] negative src
[20:14:14] [PASSED] negative dst
[20:14:14] ============ [PASSED] drm_test_rect_calc_vscale ============
[20:14:14] ================== drm_test_rect_rotate  ===================
[20:14:14] [PASSED] reflect-x
[20:14:14] [PASSED] reflect-y
[20:14:14] [PASSED] rotate-0
[20:14:14] [PASSED] rotate-90
[20:14:14] [PASSED] rotate-180
[20:14:14] [PASSED] rotate-270
[20:14:14] ============== [PASSED] drm_test_rect_rotate ===============
[20:14:14] ================ drm_test_rect_rotate_inv  =================
[20:14:14] [PASSED] reflect-x
[20:14:14] [PASSED] reflect-y
[20:14:14] [PASSED] rotate-0
[20:14:14] [PASSED] rotate-90
[20:14:14] [PASSED] rotate-180
[20:14:14] [PASSED] rotate-270
[20:14:14] ============ [PASSED] drm_test_rect_rotate_inv =============
[20:14:14] ==================== [PASSED] drm_rect =====================
[20:14:14] ============ drm_sysfb_modeset_test (1 subtest) ============
[20:14:14] ============ drm_test_sysfb_build_fourcc_list  =============
[20:14:14] [PASSED] no native formats
[20:14:14] [PASSED] XRGB8888 as native format
[20:14:14] [PASSED] remove duplicates
[20:14:14] [PASSED] convert alpha formats
[20:14:14] [PASSED] random formats
[20:14:14] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[20:14:14] ============= [PASSED] drm_sysfb_modeset_test ==============
[20:14:14] ================== drm_fixp (2 subtests) ===================
[20:14:14] [PASSED] drm_test_int2fixp
[20:14:14] [PASSED] drm_test_sm2fixp
[20:14:14] ==================== [PASSED] drm_fixp =====================
[20:14:14] ============================================================
[20:14:14] Testing complete. Ran 637 tests: passed: 637
[20:14:14] Elapsed time: 26.713s total, 1.839s configuring, 24.658s building, 0.191s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[20:14:14] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:14:16] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:14:26] Starting KUnit Kernel (1/1)...
[20:14:26] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:14:26] ================= ttm_device (5 subtests) ==================
[20:14:26] [PASSED] ttm_device_init_basic
[20:14:26] [PASSED] ttm_device_init_multiple
[20:14:26] [PASSED] ttm_device_fini_basic
[20:14:26] [PASSED] ttm_device_init_no_vma_man
[20:14:26] ================== ttm_device_init_pools  ==================
[20:14:26] [PASSED] No DMA allocations, no DMA32 required
[20:14:26] [PASSED] DMA allocations, DMA32 required
[20:14:26] [PASSED] No DMA allocations, DMA32 required
[20:14:26] [PASSED] DMA allocations, no DMA32 required
[20:14:26] ============== [PASSED] ttm_device_init_pools ==============
[20:14:26] =================== [PASSED] ttm_device ====================
[20:14:26] ================== ttm_pool (8 subtests) ===================
[20:14:26] ================== ttm_pool_alloc_basic  ===================
[20:14:26] [PASSED] One page
[20:14:26] [PASSED] More than one page
[20:14:26] [PASSED] Above the allocation limit
[20:14:26] [PASSED] One page, with coherent DMA mappings enabled
[20:14:26] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[20:14:26] ============== [PASSED] ttm_pool_alloc_basic ===============
[20:14:26] ============== ttm_pool_alloc_basic_dma_addr  ==============
[20:14:26] [PASSED] One page
[20:14:26] [PASSED] More than one page
[20:14:26] [PASSED] Above the allocation limit
[20:14:26] [PASSED] One page, with coherent DMA mappings enabled
[20:14:26] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[20:14:26] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[20:14:26] [PASSED] ttm_pool_alloc_order_caching_match
[20:14:26] [PASSED] ttm_pool_alloc_caching_mismatch
[20:14:26] [PASSED] ttm_pool_alloc_order_mismatch
[20:14:26] [PASSED] ttm_pool_free_dma_alloc
[20:14:26] [PASSED] ttm_pool_free_no_dma_alloc
[20:14:26] [PASSED] ttm_pool_fini_basic
[20:14:26] ==================== [PASSED] ttm_pool =====================
[20:14:26] ================ ttm_resource (8 subtests) =================
[20:14:26] ================= ttm_resource_init_basic  =================
[20:14:26] [PASSED] Init resource in TTM_PL_SYSTEM
[20:14:26] [PASSED] Init resource in TTM_PL_VRAM
[20:14:26] [PASSED] Init resource in a private placement
[20:14:26] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[20:14:26] ============= [PASSED] ttm_resource_init_basic =============
[20:14:26] [PASSED] ttm_resource_init_pinned
[20:14:26] [PASSED] ttm_resource_fini_basic
[20:14:26] [PASSED] ttm_resource_manager_init_basic
[20:14:26] [PASSED] ttm_resource_manager_usage_basic
[20:14:26] [PASSED] ttm_resource_manager_set_used_basic
[20:14:26] [PASSED] ttm_sys_man_alloc_basic
[20:14:26] [PASSED] ttm_sys_man_free_basic
[20:14:26] ================== [PASSED] ttm_resource ===================
[20:14:26] =================== ttm_tt (15 subtests) ===================
[20:14:26] ==================== ttm_tt_init_basic  ====================
[20:14:26] [PASSED] Page-aligned size
[20:14:26] [PASSED] Extra pages requested
[20:14:26] ================ [PASSED] ttm_tt_init_basic ================
[20:14:26] [PASSED] ttm_tt_init_misaligned
[20:14:26] [PASSED] ttm_tt_fini_basic
[20:14:26] [PASSED] ttm_tt_fini_sg
[20:14:26] [PASSED] ttm_tt_fini_shmem
[20:14:26] [PASSED] ttm_tt_create_basic
[20:14:26] [PASSED] ttm_tt_create_invalid_bo_type
[20:14:26] [PASSED] ttm_tt_create_ttm_exists
[20:14:26] [PASSED] ttm_tt_create_failed
[20:14:26] [PASSED] ttm_tt_destroy_basic
[20:14:26] [PASSED] ttm_tt_populate_null_ttm
[20:14:26] [PASSED] ttm_tt_populate_populated_ttm
[20:14:26] [PASSED] ttm_tt_unpopulate_basic
[20:14:26] [PASSED] ttm_tt_unpopulate_empty_ttm
[20:14:26] [PASSED] ttm_tt_swapin_basic
[20:14:26] ===================== [PASSED] ttm_tt ======================
[20:14:26] =================== ttm_bo (14 subtests) ===================
[20:14:26] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[20:14:26] [PASSED] Cannot be interrupted and sleeps
[20:14:26] [PASSED] Cannot be interrupted, locks straight away
[20:14:26] [PASSED] Can be interrupted, sleeps
[20:14:26] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[20:14:26] [PASSED] ttm_bo_reserve_locked_no_sleep
[20:14:26] [PASSED] ttm_bo_reserve_no_wait_ticket
[20:14:26] [PASSED] ttm_bo_reserve_double_resv
[20:14:26] [PASSED] ttm_bo_reserve_interrupted
[20:14:26] [PASSED] ttm_bo_reserve_deadlock
[20:14:26] [PASSED] ttm_bo_unreserve_basic
[20:14:26] [PASSED] ttm_bo_unreserve_pinned
[20:14:26] [PASSED] ttm_bo_unreserve_bulk
[20:14:26] [PASSED] ttm_bo_fini_basic
[20:14:26] [PASSED] ttm_bo_fini_shared_resv
[20:14:26] [PASSED] ttm_bo_pin_basic
[20:14:26] [PASSED] ttm_bo_pin_unpin_resource
[20:14:26] [PASSED] ttm_bo_multiple_pin_one_unpin
[20:14:26] ===================== [PASSED] ttm_bo ======================
[20:14:26] ============== ttm_bo_validate (22 subtests) ===============
[20:14:26] ============== ttm_bo_init_reserved_sys_man  ===============
[20:14:26] [PASSED] Buffer object for userspace
[20:14:26] [PASSED] Kernel buffer object
[20:14:26] [PASSED] Shared buffer object
[20:14:26] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[20:14:26] ============== ttm_bo_init_reserved_mock_man  ==============
[20:14:26] [PASSED] Buffer object for userspace
[20:14:26] [PASSED] Kernel buffer object
[20:14:26] [PASSED] Shared buffer object
[20:14:26] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[20:14:26] [PASSED] ttm_bo_init_reserved_resv
[20:14:26] ================== ttm_bo_validate_basic  ==================
[20:14:26] [PASSED] Buffer object for userspace
[20:14:26] [PASSED] Kernel buffer object
[20:14:26] [PASSED] Shared buffer object
[20:14:26] ============== [PASSED] ttm_bo_validate_basic ==============
[20:14:26] [PASSED] ttm_bo_validate_invalid_placement
[20:14:26] ============= ttm_bo_validate_same_placement  ==============
[20:14:26] [PASSED] System manager
[20:14:26] [PASSED] VRAM manager
[20:14:26] ========= [PASSED] ttm_bo_validate_same_placement ==========
[20:14:26] [PASSED] ttm_bo_validate_failed_alloc
[20:14:26] [PASSED] ttm_bo_validate_pinned
[20:14:26] [PASSED] ttm_bo_validate_busy_placement
[20:14:26] ================ ttm_bo_validate_multihop  =================
[20:14:26] [PASSED] Buffer object for userspace
[20:14:26] [PASSED] Kernel buffer object
[20:14:26] [PASSED] Shared buffer object
[20:14:26] ============ [PASSED] ttm_bo_validate_multihop =============
[20:14:26] ========== ttm_bo_validate_no_placement_signaled  ==========
[20:14:26] [PASSED] Buffer object in system domain, no page vector
[20:14:26] [PASSED] Buffer object in system domain with an existing page vector
[20:14:26] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[20:14:26] ======== ttm_bo_validate_no_placement_not_signaled  ========
[20:14:26] [PASSED] Buffer object for userspace
[20:14:26] [PASSED] Kernel buffer object
[20:14:26] [PASSED] Shared buffer object
[20:14:26] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[20:14:26] [PASSED] ttm_bo_validate_move_fence_signaled
[20:14:26] ========= ttm_bo_validate_move_fence_not_signaled  =========
[20:14:26] [PASSED] Waits for GPU
[20:14:26] [PASSED] Tries to lock straight away
[20:14:26] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[20:14:26] [PASSED] ttm_bo_validate_swapout
[20:14:26] [PASSED] ttm_bo_validate_happy_evict
[20:14:26] [PASSED] ttm_bo_validate_all_pinned_evict
[20:14:26] [PASSED] ttm_bo_validate_allowed_only_evict
[20:14:26] [PASSED] ttm_bo_validate_deleted_evict
[20:14:26] [PASSED] ttm_bo_validate_busy_domain_evict
[20:14:26] [PASSED] ttm_bo_validate_evict_gutting
[20:14:26] [PASSED] ttm_bo_validate_recrusive_evict
[20:14:26] ================= [PASSED] ttm_bo_validate =================
[20:14:26] ============================================================
[20:14:26] Testing complete. Ran 102 tests: passed: 102
[20:14:26] Elapsed time: 12.018s total, 1.836s configuring, 9.917s building, 0.236s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[20:14:27] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:14:28] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:14:37] Starting KUnit Kernel (1/1)...
[20:14:37] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:14:37] =============== dma-buf-fence (12 subtests) ================
[20:14:37] [PASSED] test_sanitycheck
[20:14:37] [PASSED] test_signaling
[20:14:37] [PASSED] test_add_callback
[20:14:37] [PASSED] test_late_add_callback
[20:14:37] [PASSED] test_rm_callback
[20:14:37] [PASSED] test_late_rm_callback
[20:14:37] [PASSED] test_status
[20:14:37] [PASSED] test_error
[20:14:37] [PASSED] test_wait
[20:14:37] [PASSED] test_wait_timeout
[20:14:37] [PASSED] test_stub
[20:14:37] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[20:14:37] ================== [PASSED] dma-buf-fence ==================
[20:14:37] ============ dma-buf-fence-chain (11 subtests) =============
[20:14:37] [PASSED] test_sanitycheck
[20:14:37] [PASSED] test_find_seqno
[20:14:37] [PASSED] test_find_signaled
[20:14:37] [PASSED] test_find_out_of_order
[20:14:42] [PASSED] test_find_gap
[20:14:42] [PASSED] test_find_race
[20:14:42] [PASSED] test_signal_forward
[20:14:42] [PASSED] test_signal_backward
[20:14:42] [PASSED] test_wait_forward
[20:14:42] [PASSED] test_wait_backward
[20:14:42] [PASSED] test_wait_random
[20:14:42] =============== [PASSED] dma-buf-fence-chain ===============
[20:14:42] ============ dma-buf-fence-unwrap (10 subtests) ============
[20:14:42] [PASSED] test_sanitycheck
[20:14:42] [PASSED] test_unwrap_array
[20:14:42] [PASSED] test_unwrap_chain
[20:14:42] [PASSED] test_unwrap_chain_array
[20:14:42] [PASSED] test_unwrap_merge
[20:14:42] [PASSED] test_unwrap_merge_duplicate
[20:14:42] [PASSED] test_unwrap_merge_seqno
[20:14:42] [PASSED] test_unwrap_merge_order
[20:14:42] [PASSED] test_unwrap_merge_complex
[20:14:42] [PASSED] test_unwrap_merge_complex_seqno
[20:14:42] ============== [PASSED] dma-buf-fence-unwrap ===============
[20:14:42] ================ dma-buf-resv (5 subtests) =================
[20:14:42] [PASSED] test_sanitycheck
[20:14:42] ===================== test_signaling  ======================
[20:14:42] [PASSED] kernel
[20:14:42] [PASSED] write
[20:14:42] [PASSED] read
[20:14:42] [PASSED] bookkeep
[20:14:42] ================= [PASSED] test_signaling ==================
[20:14:42] ====================== test_for_each  ======================
[20:14:42] [PASSED] kernel
[20:14:42] [PASSED] write
[20:14:42] [PASSED] read
[20:14:42] [PASSED] bookkeep
[20:14:42] ================== [PASSED] test_for_each ==================
[20:14:42] ================= test_for_each_unlocked  ==================
[20:14:42] [PASSED] kernel
[20:14:42] [PASSED] write
[20:14:42] [PASSED] read
[20:14:42] [PASSED] bookkeep
[20:14:42] ============= [PASSED] test_for_each_unlocked ==============
[20:14:42] ===================== test_get_fences  =====================
[20:14:42] [PASSED] kernel
[20:14:42] [PASSED] write
[20:14:42] [PASSED] read
[20:14:42] [PASSED] bookkeep
[20:14:42] ================= [PASSED] test_get_fences =================
[20:14:42] ================== [PASSED] dma-buf-resv ===================
[20:14:42] ============================================================
[20:14:42] Testing complete. Ran 50 tests: passed: 49, skipped: 1
[20:14:42] Elapsed time: 15.834s total, 1.815s configuring, 8.697s building, 5.284s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel



^ permalink raw reply	[flat|nested] 19+ messages in thread

* ✓ Xe.CI.BAT: success for Modify the SW tail logic in OA
  2026-08-21 20:07 [PATCH 0/3] Modify the SW tail logic in OA Umesh Nerlige Ramappa
                   ` (3 preceding siblings ...)
  2026-08-21 20:14 ` ✓ CI.KUnit: success for Modify the SW tail logic in OA Patchwork
@ 2026-08-21 21:03 ` Patchwork
  2026-08-21 22:35 ` ✓ Xe.CI.FULL: " Patchwork
  5 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2026-08-21 21:03 UTC (permalink / raw)
  To: Umesh Nerlige Ramappa; +Cc: intel-xe

[-- Attachment #1: Type: text/plain, Size: 944 bytes --]

== Series Details ==

Series: Modify the SW tail logic in OA
URL   : https://patchwork.freedesktop.org/series/172609/
State : success

== Summary ==

CI Bug Log - changes from xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c_BAT -> xe-pw-172609v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c -> xe-pw-172609v1

  IGT_9070: 80b6e4c9b9cb853c63a9bcaa4784e0306d1f7fca @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c: 58d59a40e2a041d3c159fab8bf5d5dc19d28da6c
  xe-pw-172609v1: 172609v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/index.html

[-- Attachment #2: Type: text/html, Size: 1492 bytes --]

^ permalink raw reply	[flat|nested] 19+ messages in thread

* ✓ Xe.CI.FULL: success for Modify the SW tail logic in OA
  2026-08-21 20:07 [PATCH 0/3] Modify the SW tail logic in OA Umesh Nerlige Ramappa
                   ` (4 preceding siblings ...)
  2026-08-21 21:03 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-08-21 22:35 ` Patchwork
  5 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2026-08-21 22:35 UTC (permalink / raw)
  To: Umesh Nerlige Ramappa; +Cc: intel-xe

[-- Attachment #1: Type: text/plain, Size: 34436 bytes --]

== Series Details ==

Series: Modify the SW tail logic in OA
URL   : https://patchwork.freedesktop.org/series/172609/
State : success

== Summary ==

CI Bug Log - changes from xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c_FULL -> xe-pw-172609v1_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-172609v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@x-tiled-32bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][1] ([Intel XE#2327]) +1 other test skip
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-bmg:          NOTRUN -> [SKIP][2] ([Intel XE#1124]) +5 other tests skip
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-2/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_bw@connected-linear-tiling-4-displays-target-1920x1080p:
    - shard-bmg:          NOTRUN -> [SKIP][3] ([Intel XE#7679])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@kms_bw@connected-linear-tiling-4-displays-target-1920x1080p.html

  * igt@kms_bw@linear-tiling-1-displays-target-2560x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][4] ([Intel XE#367]) +1 other test skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-9/igt@kms_bw@linear-tiling-1-displays-target-2560x1440p.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#2887]) +8 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-bmg:          [PASS][6] -> [INCOMPLETE][7] ([Intel XE#7084] / [Intel XE#8150]) +1 other test incomplete
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-8/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-2/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#2652]) +17 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-a-dp-2.html

  * igt@kms_cdclk@plane-scaling:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#2724] / [Intel XE#7449])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-2/igt@kms_cdclk@plane-scaling.html

  * igt@kms_chamelium_color@gamma:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#2325] / [Intel XE#7358])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@kms_chamelium_color@gamma.html

  * igt@kms_chamelium_edid@dp-edid-change-during-hibernate:
    - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#2252]) +2 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@kms_chamelium_edid@dp-edid-change-during-hibernate.html

  * igt@kms_chamelium_sharpness_filter@filter-basic:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#6507])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@kms_chamelium_sharpness_filter@filter-basic.html

  * igt@kms_content_protection@content-type-change:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#7642])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@kms_content_protection@content-type-change.html

  * igt@kms_content_protection@lic-type-0@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][14] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) +1 other test fail
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@kms_content_protection@lic-type-0@pipe-a-dp-2.html

  * igt@kms_content_protection@uevent:
    - shard-bmg:          NOTRUN -> [FAIL][15] ([Intel XE#6707] / [Intel XE#7439]) +1 other test fail
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-9/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-random-32x32:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#2320]) +3 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@kms_cursor_crc@cursor-random-32x32.html

  * igt@kms_cursor_crc@cursor-sliding-512x512:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#2321] / [Intel XE#7355]) +1 other test skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-2/igt@kms_cursor_crc@cursor-sliding-512x512.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#8265]) +2 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-2/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-lnl:          [PASS][19] -> [FAIL][20] ([Intel XE#301]) +2 other tests fail
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#7178] / [Intel XE#7349])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#7178] / [Intel XE#7351]) +1 other test skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling.html

  * igt@kms_frontbuffer_tracking@drrs-abgr161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#7061] / [Intel XE#7356]) +5 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#4141]) +9 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#2352] / [Intel XE#7399])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#2311]) +40 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#2313]) +37 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-abgr161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#7061]) +1 other test skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsrhdr-abgr161616f-draw-render.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#1503])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@kms_hdr@invalid-hdr.html

  * igt@kms_joiner@basic-max-non-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#4298] / [Intel XE#5873])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@kms_joiner@basic-max-non-joiner.html

  * igt@kms_panel_fitting@legacy:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#2486])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@kms_panel_fitting@legacy.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-mc-ccs-modifier:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#7283]) +2 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@kms_plane@pixel-format-4-tiled-dg2-mc-ccs-modifier.html

  * igt@kms_plane@pixel-format-x-tiled-modifier@pipe-b-plane-5:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#8303]) +1 other test skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@kms_plane@pixel-format-x-tiled-modifier@pipe-b-plane-5.html

  * igt@kms_plane_lowres@tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#2393])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-2/igt@kms_plane_lowres@tiling-y.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#2763] / [Intel XE#6886]) +4 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-9/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b.html

  * igt@kms_pm_backlight@fade-with-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#7376] / [Intel XE#7760] / [Intel XE#870])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@kms_pm_backlight@fade-with-suspend.html

  * igt@kms_pm_dc@dc3co-vpb-framegap:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#8395] / [Intel XE#8396]) +1 other test skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-2/igt@kms_pm_dc@dc3co-vpb-framegap.html

  * igt@kms_pm_dc@dc3co-vpb-framegap@psr2-xrgb8888:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#8396]) +1 other test skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-2/igt@kms_pm_dc@dc3co-vpb-framegap@psr2-xrgb8888.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#1489]) +3 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#2387] / [Intel XE#7429]) +1 other test skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@fbc-psr2-cursor-plane-move:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#2234] / [Intel XE#2850]) +7 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@kms_psr@fbc-psr2-cursor-plane-move.html

  * igt@kms_psr@psr2-primary-render:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#2234])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-2/igt@kms_psr@psr2-primary-render.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
    - shard-bmg:          NOTRUN -> [SKIP][43] ([Intel XE#2330] / [Intel XE#5813]) +1 other test skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@sprite-rotation-90:
    - shard-bmg:          NOTRUN -> [SKIP][44] ([Intel XE#3904] / [Intel XE#7342])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@kms_rotation_crc@sprite-rotation-90.html

  * igt@kms_sharpness_filter@filter-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#6503]) +2 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-2/igt@kms_sharpness_filter@filter-suspend.html

  * igt@kms_vrr@seamless-rr-switch-virtual:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#1499]) +1 other test skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-9/igt@kms_vrr@seamless-rr-switch-virtual.html

  * igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
    - shard-lnl:          [PASS][47] -> [FAIL][48] ([Intel XE#7397]) +1 other test fail
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-lnl-4/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-lnl-6/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html

  * igt@sriov_basic@pf-unbind-with-vfs-enabled-numvfs-all:
    - shard-bmg:          NOTRUN -> [ABORT][49] ([Intel XE#8868])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-9/igt@sriov_basic@pf-unbind-with-vfs-enabled-numvfs-all.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          NOTRUN -> [INCOMPLETE][50] ([Intel XE#6321] / [Intel XE#8355])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-9/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate-race:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#2322] / [Intel XE#7372]) +5 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate-race.html

  * igt@xe_exec_fault_mode@twice-multi-queue-imm:
    - shard-bmg:          NOTRUN -> [SKIP][52] ([Intel XE#8374]) +9 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-2/igt@xe_exec_fault_mode@twice-multi-queue-imm.html

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-close-fd-smem:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#8364]) +19 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@xe_exec_multi_queue@one-queue-preempt-mode-close-fd-smem.html

  * igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-userptr:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#8378]) +6 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-9/igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-userptr.html

  * igt@xe_fault_injection@inject-fault-probe-function-xe_guc_log_init:
    - shard-bmg:          [PASS][55] -> [ABORT][56] ([Intel XE#8007])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-5/igt@xe_fault_injection@inject-fault-probe-function-xe_guc_log_init.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-4/igt@xe_fault_injection@inject-fault-probe-function-xe_guc_log_init.html

  * igt@xe_module_load@load:
    - shard-bmg:          ([PASS][57], [PASS][58], [PASS][59], [PASS][60], [PASS][61], [PASS][62], [PASS][63], [PASS][64], [PASS][65], [PASS][66], [PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71], [PASS][72], [PASS][73], [PASS][74], [PASS][75], [PASS][76], [PASS][77], [PASS][78], [PASS][79], [PASS][80], [PASS][81]) -> ([PASS][82], [PASS][83], [PASS][84], [PASS][85], [PASS][86], [PASS][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91], [PASS][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [SKIP][99], [PASS][100], [PASS][101], [PASS][102], [PASS][103], [PASS][104], [PASS][105], [PASS][106], [PASS][107]) ([Intel XE#2457] / [Intel XE#7405])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-5/igt@xe_module_load@load.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-10/igt@xe_module_load@load.html
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-4/igt@xe_module_load@load.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-1/igt@xe_module_load@load.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-9/igt@xe_module_load@load.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-4/igt@xe_module_load@load.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-7/igt@xe_module_load@load.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-1/igt@xe_module_load@load.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-7/igt@xe_module_load@load.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-1/igt@xe_module_load@load.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-10/igt@xe_module_load@load.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-3/igt@xe_module_load@load.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-3/igt@xe_module_load@load.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-6/igt@xe_module_load@load.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-8/igt@xe_module_load@load.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-6/igt@xe_module_load@load.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-8/igt@xe_module_load@load.html
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-8/igt@xe_module_load@load.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-9/igt@xe_module_load@load.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-2/igt@xe_module_load@load.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-10/igt@xe_module_load@load.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-2/igt@xe_module_load@load.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-5/igt@xe_module_load@load.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-5/igt@xe_module_load@load.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-3/igt@xe_module_load@load.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-1/igt@xe_module_load@load.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-2/igt@xe_module_load@load.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-1/igt@xe_module_load@load.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-3/igt@xe_module_load@load.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-2/igt@xe_module_load@load.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-2/igt@xe_module_load@load.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-3/igt@xe_module_load@load.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@xe_module_load@load.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@xe_module_load@load.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-9/igt@xe_module_load@load.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@xe_module_load@load.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-7/igt@xe_module_load@load.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-7/igt@xe_module_load@load.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-6/igt@xe_module_load@load.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-10/igt@xe_module_load@load.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-8/igt@xe_module_load@load.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-8/igt@xe_module_load@load.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-9/igt@xe_module_load@load.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-6/igt@xe_module_load@load.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-6/igt@xe_module_load@load.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-10/igt@xe_module_load@load.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-8/igt@xe_module_load@load.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-7/igt@xe_module_load@load.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-9/igt@xe_module_load@load.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-4/igt@xe_module_load@load.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-4/igt@xe_module_load@load.html

  * igt@xe_multigpu_svm@mgpu-concurrent-access-basic:
    - shard-bmg:          NOTRUN -> [SKIP][108] ([Intel XE#6964]) +1 other test skip
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@xe_multigpu_svm@mgpu-concurrent-access-basic.html

  * igt@xe_page_reclaim@boundary-split:
    - shard-bmg:          NOTRUN -> [SKIP][109] ([Intel XE#7793]) +2 other tests skip
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-9/igt@xe_page_reclaim@boundary-split.html

  * igt@xe_pm@s2idle-d3cold-basic-exec:
    - shard-bmg:          NOTRUN -> [SKIP][110] ([Intel XE#2284] / [Intel XE#7370]) +3 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-9/igt@xe_pm@s2idle-d3cold-basic-exec.html

  * igt@xe_prefetch_fault@prefetch-fault-svm:
    - shard-bmg:          NOTRUN -> [SKIP][111] ([Intel XE#7599])
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-2/igt@xe_prefetch_fault@prefetch-fault-svm.html

  * igt@xe_pxp@pxp-stale-bo-exec-post-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][112] ([Intel XE#4733] / [Intel XE#7417]) +1 other test skip
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@xe_pxp@pxp-stale-bo-exec-post-suspend.html

  
#### Possible fixes ####

  * igt@device_reset@unbind-reset-rebind:
    - shard-bmg:          [ABORT][113] ([Intel XE#8007]) -> [PASS][114] +2 other tests pass
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-10/igt@device_reset@unbind-reset-rebind.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@device_reset@unbind-reset-rebind.html

  * igt@kms_async_flips@alternate-sync-async-flip:
    - shard-bmg:          [FAIL][115] ([Intel XE#3718] / [Intel XE#6078]) -> [PASS][116]
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-3/igt@kms_async_flips@alternate-sync-async-flip.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-6/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-c-dp-2:
    - shard-bmg:          [FAIL][117] ([Intel XE#6078]) -> [PASS][118]
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-3/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-dp-2.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-6/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-dp-2.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-lnl:          [FAIL][119] ([Intel XE#301]) -> [PASS][120]
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-huge-nomemset:
    - shard-bmg:          [FAIL][121] ([Intel XE#8058] / [Intel XE#8528]) -> [PASS][122]
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-5/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-huge-nomemset.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-2/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-huge-nomemset.html

  
#### Warnings ####

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][123] ([Intel XE#2426] / [Intel XE#5848]) -> [SKIP][124] ([Intel XE#2509] / [Intel XE#7437])
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-8/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@xe_fault_injection@exec-queue-create-fail-xe_pxp_exec_queue_add:
    - shard-bmg:          [ABORT][125] ([Intel XE#8007]) -> [SKIP][126] ([Intel XE#6281] / [Intel XE#7426])
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c/shard-bmg-9/igt@xe_fault_injection@exec-queue-create-fail-xe_pxp_exec_queue_add.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/shard-bmg-5/igt@xe_fault_injection@exec-queue-create-fail-xe_pxp_exec_queue_add.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
  [Intel XE#2352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2352
  [Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
  [Intel XE#2393]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2393
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
  [Intel XE#2486]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2486
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3718
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4298]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4298
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#5813]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5813
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#5873]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5873
  [Intel XE#6078]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6078
  [Intel XE#6281]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6281
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#6507]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6507
  [Intel XE#6707]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6707
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7349]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7349
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
  [Intel XE#7376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7376
  [Intel XE#7397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7397
  [Intel XE#7399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7399
  [Intel XE#7405]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7405
  [Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
  [Intel XE#7426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7426
  [Intel XE#7429]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7429
  [Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
  [Intel XE#7439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7439
  [Intel XE#7449]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7449
  [Intel XE#7599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7599
  [Intel XE#7642]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7642
  [Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
  [Intel XE#7760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7760
  [Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#8058]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8058
  [Intel XE#8150]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8150
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#8303]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8303
  [Intel XE#8355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8355
  [Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
  [Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
  [Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
  [Intel XE#8395]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8395
  [Intel XE#8396]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8396
  [Intel XE#8528]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8528
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#8868]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8868


Build changes
-------------

  * Linux: xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c -> xe-pw-172609v1

  IGT_9070: 80b6e4c9b9cb853c63a9bcaa4784e0306d1f7fca @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5631-58d59a40e2a041d3c159fab8bf5d5dc19d28da6c: 58d59a40e2a041d3c159fab8bf5d5dc19d28da6c
  xe-pw-172609v1: 172609v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172609v1/index.html

[-- Attachment #2: Type: text/html, Size: 37158 bytes --]

^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH 0/3] Modify the SW tail logic in OA
@ 2026-08-21 22:23 Umesh Nerlige Ramappa
  2026-08-21 22:23 ` [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user Umesh Nerlige Ramappa
  0 siblings, 1 reply; 19+ messages in thread
From: Umesh Nerlige Ramappa @ 2026-08-21 22:23 UTC (permalink / raw)
  To: intel-xe, Ashutosh Dixit

OA unit updates the HW TAIL register to indicate that a new report is
available, although it does not guarantee that the report is visible in
memory. Also the currently running workload contributes to some latency
in seeing this report in memory. In the past we would set some fields in
the OA report and check if the fields are populated to non-zero values
by the HW, but this is no longer sufficient since some parts of the
report may land out of order under heavy workloads. Drop this WA and add
a new logic that just waits for a fixed number of HW TAIL report
increments before returning data to the user. User will always see the
reports lagging by this fixed number, however we do not have realtime
use cases for OAG since OAG reports are mainly post processed.

v2: Rebase
v3: Add Sashiko's review comments
v4: Rebase, checkpatch fixes
v5: Add Ashutosh's review comments
v6: Add Sashiko's review comment

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Umesh Nerlige Ramappa (3):
  drm/xe/xe_oa: Clear status only if relevant bits are set
  drm/xe/xe_oa: Avoid checking and setting fields in the OA report
  drm/xe/xe_oa: Add a lag to the reports that is exported to user

 drivers/gpu/drm/xe/xe_oa.c | 108 ++++++++-----------------------------
 1 file changed, 21 insertions(+), 87 deletions(-)

-- 
2.51.0

^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user
  2026-08-21 22:23 [PATCH 0/3] " Umesh Nerlige Ramappa
@ 2026-08-21 22:23 ` Umesh Nerlige Ramappa
  2026-08-21 22:37   ` sashiko-bot
  2026-08-24 15:57   ` Dixit, Ashutosh
  0 siblings, 2 replies; 19+ messages in thread
From: Umesh Nerlige Ramappa @ 2026-08-21 22:23 UTC (permalink / raw)
  To: intel-xe, Ashutosh Dixit

When running heavy workloads, reading the OA reports too soon does not
guarantee that the report has landed in memory. To make sure correct
reports are copied to user buffer, only return reports that lag the
current HW_TAIL register by 32 reports. This is an empirical number
based on a heavy render workload and several test iterations.

The reports that user reads will always lag the HW tail by 32 reports,
however since OA is used for post processing analysis, this should not
affect any current use cases. When the stream is closed or disabled, we
let the user read the remaining reports up until HW tail.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
v2: Fix the LAG logic by using sliding window (Sashiko)
v3: Fix checkpatch warning
v4: Update sw tail on stream disable (Ashutosh)
v5: Ensure read is not blocked forever (Sashiko)
---
 drivers/gpu/drm/xe/xe_oa.c | 23 +++++++++++++++--------
 1 file changed, 15 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
index d7647f37ab02..c8f2d7de1396 100644
--- a/drivers/gpu/drm/xe/xe_oa.c
+++ b/drivers/gpu/drm/xe/xe_oa.c
@@ -224,7 +224,7 @@ static bool mert_wa_14026633728(struct xe_oa_stream *s)
 static bool xe_oa_buffer_check_unlocked(struct xe_oa_stream *stream)
 {
 	u32 gtt_offset = xe_bo_ggtt_addr(stream->oa_buffer.bo);
-	u32 hw_tail, partial_report_size, available;
+	u32 hw_tail, partial_report_size, available, lag;
 	int report_size = stream->oa_buffer.format->size;
 	unsigned long flags;
 
@@ -234,17 +234,23 @@ static bool xe_oa_buffer_check_unlocked(struct xe_oa_stream *stream)
 	hw_tail -= gtt_offset;
 
 	/*
-	 * The tail pointer increases in 64 byte (cacheline size), not in report_size
+	 * The hw_tail pointer increases in 64 byte (cacheline size), not in report_size
 	 * increments. Also report size may not be a power of 2. Compute potential
 	 * partially landed report in OA buffer.
 	 */
 	partial_report_size = xe_oa_circ_diff(stream, hw_tail, stream->oa_buffer.tail);
 	partial_report_size %= report_size;
 
-	/* Subtract partial amount off the tail */
+	/* Subtract partial amount off the hw_tail */
 	hw_tail = xe_oa_circ_diff(stream, hw_tail, partial_report_size);
 
-	stream->oa_buffer.tail = hw_tail;
+#define LAG_REPORTS 32
+	lag = xe_oa_circ_diff(stream, hw_tail, stream->oa_buffer.tail);
+	if (!stream->enabled)
+		stream->oa_buffer.tail = hw_tail;
+	else if (lag > LAG_REPORTS * report_size)
+		stream->oa_buffer.tail = xe_oa_circ_diff(stream, hw_tail,
+							 LAG_REPORTS * report_size);
 
 	available = xe_oa_circ_diff(stream, stream->oa_buffer.tail, stream->oa_buffer.head);
 	stream->pollin = available >= stream->wait_num_reports * report_size;
@@ -1416,10 +1422,6 @@ static void xe_oa_stream_disable(struct xe_oa_stream *stream)
 
 	if (stream->sample)
 		hrtimer_cancel(&stream->poll_check_timer);
-
-	/* Update stream->oa_buffer.tail to allow any final reports to be read */
-	if (xe_oa_buffer_check_unlocked(stream))
-		wake_up(&stream->poll_wq);
 }
 
 static int xe_oa_enable_preempt_timeslice(struct xe_oa_stream *stream)
@@ -1490,6 +1492,11 @@ static int xe_oa_disable_locked(struct xe_oa_stream *stream)
 		ret = xe_oa_enable_preempt_timeslice(stream);
 
 	stream->enabled = false;
+
+	/* Update stream->oa_buffer.tail to allow any final reports to be read */
+	if (xe_oa_buffer_check_unlocked(stream))
+		wake_up(&stream->poll_wq);
+
 	return ret;
 }
 
-- 
2.51.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* Re: [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user
  2026-08-21 22:23 ` [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user Umesh Nerlige Ramappa
@ 2026-08-21 22:37   ` sashiko-bot
  2026-08-24 15:57   ` Dixit, Ashutosh
  1 sibling, 0 replies; 19+ messages in thread
From: sashiko-bot @ 2026-08-21 22:37 UTC (permalink / raw)
  To: Umesh Nerlige Ramappa; +Cc: intel-xe

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:

New issues:
- [High] The newly introduced 32-report lag reduces the maximum possible available reports, but `wait_num_reports` validation still allows values up to full buffer capacity, causing a permanent hang and `-EIO` on overflow.

Pre-existing issues:
- [High] Readers blocked in `read()` or `poll()` will hang indefinitely when the OA stream is disabled due to conditional wakeups and incomplete wait conditions.
--

--- Patch [3]: [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user ---
commit 73d1f6a4433c8e56a02c188bad978ed299d6d4b6
Author: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

drm/xe/xe_oa: Add a lag to the reports that is exported to user

This commit adds a 32-report lag to the OA stream reports exposed to the user.
It updates the buffer check logic to ensure the software tail stays behind the
hardware tail unless the stream is disabled, in which case all remaining reports
can be read.

> diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
> index 020b27c642268..a025e6c2753f2 100644
> --- a/drivers/gpu/drm/xe/xe_oa.c
> +++ b/drivers/gpu/drm/xe/xe_oa.c
[ ... ]
> @@ -234,17 +234,23 @@ static bool xe_oa_buffer_check_unlocked(struct xe_oa_stream *stream)
>  	hw_tail -= gtt_offset;
>  
>  	/*
> -	 * The tail pointer increases in 64 byte (cacheline size), not in report_size
> +	 * The hw_tail pointer increases in 64 byte (cacheline size), not in report_size
>  	 * increments. Also report size may not be a power of 2. Compute potential
>  	 * partially landed report in OA buffer.
>  	 */
>  	partial_report_size = xe_oa_circ_diff(stream, hw_tail, stream->oa_buffer.tail);
>  	partial_report_size %= report_size;
>  
> -	/* Subtract partial amount off the tail */
> +	/* Subtract partial amount off the hw_tail */
>  	hw_tail = xe_oa_circ_diff(stream, hw_tail, partial_report_size);
>  
> -	stream->oa_buffer.tail = hw_tail;
> +#define LAG_REPORTS 32
> +	lag = xe_oa_circ_diff(stream, hw_tail, stream->oa_buffer.tail);
> +	if (!stream->enabled)
> +		stream->oa_buffer.tail = hw_tail;
> +	else if (lag > LAG_REPORTS * report_size)
> +		stream->oa_buffer.tail = xe_oa_circ_diff(stream, hw_tail,
> +							 LAG_REPORTS * report_size);

[Severity: High]
Does this logic effectively reduce the maximum number of available reports
in the buffer by 32?

If so, userspace could now specify a wait_num_reports in
xe_oa_stream_open_ioctl() that is impossible to satisfy. The ioctl validation
still allows values up to the full buffer capacity:

drivers/gpu/drm/xe/xe_oa.c:xe_oa_stream_open_ioctl() {
    if (param.wait_num_reports > param.oa_buffer_size / f->size) {
        ...
        ret = -EINVAL;
    }
}

If userspace requests a wait amount greater than (capacity - 32),
the available amount will never reach wait_num_reports. The hardware
tail will wrap around and overwrite unread data, causing read() or poll()
to hang indefinitely until the overflow is processed and returns -EIO.

Should the validation limit in xe_oa_stream_open_ioctl() be updated to
subtract LAG_REPORTS?

>  
>  	available = xe_oa_circ_diff(stream, stream->oa_buffer.tail, stream->oa_buffer.head);
>  	stream->pollin = available >= stream->wait_num_reports * report_size;
[ ... ]
> @@ -1490,6 +1492,11 @@ static int xe_oa_disable_locked(struct xe_oa_stream *stream)
>  		ret = xe_oa_enable_preempt_timeslice(stream);
>  
>  	stream->enabled = false;
> +
> +	/* Update stream->oa_buffer.tail to allow any final reports to be read */
> +	if (xe_oa_buffer_check_unlocked(stream))
> +		wake_up(&stream->poll_wq);
> +

[Severity: High]
This is a pre-existing issue, but can readers blocked in read() or poll() hang
indefinitely when the OA stream is disabled here?

Because xe_oa_buffer_check_unlocked() returns true only when
available >= wait_num_reports, the wakeup is skipped entirely if there are
fewer pending reports than the wait threshold.

Furthermore, looking at xe_oa_wait_unlocked(), it doesn't check
!stream->enabled in its wait condition:

drivers/gpu/drm/xe/xe_oa.c:xe_oa_wait_unlocked() {
    return wait_event_interruptible(stream->poll_wq,
                                    xe_oa_buffer_check_unlocked(stream));
}

Even if an unconditional wakeup was performed here, wouldn't the thread
re-evaluate the condition and go back to sleep forever since the hardware
is stopped and timers are canceled?

>  	return ret;
>  }
>

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260821222338.1053887-5-umesh.nerlige.ramappa@intel.com?part=3

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user
  2026-08-21 22:23 ` [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user Umesh Nerlige Ramappa
  2026-08-21 22:37   ` sashiko-bot
@ 2026-08-24 15:57   ` Dixit, Ashutosh
  1 sibling, 0 replies; 19+ messages in thread
From: Dixit, Ashutosh @ 2026-08-24 15:57 UTC (permalink / raw)
  To: Umesh Nerlige Ramappa; +Cc: intel-xe

On Fri, 21 Aug 2026 15:23:42 -0700, Umesh Nerlige Ramappa wrote:
>

Hi Umesh,

> When running heavy workloads, reading the OA reports too soon does not
> guarantee that the report has landed in memory. To make sure correct
> reports are copied to user buffer, only return reports that lag the
> current HW_TAIL register by 32 reports. This is an empirical number
> based on a heavy render workload and several test iterations.
>
> The reports that user reads will always lag the HW tail by 32 reports,
> however since OA is used for post processing analysis, this should not
> affect any current use cases. When the stream is closed or disabled, we
> let the user read the remaining reports up until HW tail.
>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
> v2: Fix the LAG logic by using sliding window (Sashiko)
> v3: Fix checkpatch warning
> v4: Update sw tail on stream disable (Ashutosh)
> v5: Ensure read is not blocked forever (Sashiko)
> ---
>  drivers/gpu/drm/xe/xe_oa.c | 23 +++++++++++++++--------
>  1 file changed, 15 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
> index d7647f37ab02..c8f2d7de1396 100644
> --- a/drivers/gpu/drm/xe/xe_oa.c
> +++ b/drivers/gpu/drm/xe/xe_oa.c
> @@ -224,7 +224,7 @@ static bool mert_wa_14026633728(struct xe_oa_stream *s)
>  static bool xe_oa_buffer_check_unlocked(struct xe_oa_stream *stream)
>  {
>	u32 gtt_offset = xe_bo_ggtt_addr(stream->oa_buffer.bo);
> -	u32 hw_tail, partial_report_size, available;
> +	u32 hw_tail, partial_report_size, available, lag;
>	int report_size = stream->oa_buffer.format->size;
>	unsigned long flags;
>
> @@ -234,17 +234,23 @@ static bool xe_oa_buffer_check_unlocked(struct xe_oa_stream *stream)
>	hw_tail -= gtt_offset;
>
>	/*
> -	 * The tail pointer increases in 64 byte (cacheline size), not in report_size
> +	 * The hw_tail pointer increases in 64 byte (cacheline size), not in report_size
>	 * increments. Also report size may not be a power of 2. Compute potential
>	 * partially landed report in OA buffer.
>	 */
>	partial_report_size = xe_oa_circ_diff(stream, hw_tail, stream->oa_buffer.tail);
>	partial_report_size %= report_size;
>
> -	/* Subtract partial amount off the tail */
> +	/* Subtract partial amount off the hw_tail */
>	hw_tail = xe_oa_circ_diff(stream, hw_tail, partial_report_size);
>
> -	stream->oa_buffer.tail = hw_tail;
> +#define LAG_REPORTS 32
> +	lag = xe_oa_circ_diff(stream, hw_tail, stream->oa_buffer.tail);
> +	if (!stream->enabled)
> +		stream->oa_buffer.tail = hw_tail;

I was originally thinking we would do this in the disable code path
(xe_oa_disable_locked etc.), but who knows where hw_tail is going to be
(whether it will be multiple of report_size etc.), so instead of
replicating that code, it seems good to do it here and call
xe_oa_buffer_check_unlocked() from xe_oa_disable_locked() as is being done
below.

Also, because xe_oa_buffer_check_unlocked() is called from the read() code paths,
I considered the following situations:

* xe_oa_buffer_check_unlocked() called multiple times after stream disable
* xe_oa_buffer_check_unlocked() called before enabling the stream

And all this seems fine to me. We would just be setting
'stream->oa_buffer.tail' multiple times unnecessarily, but looks like we
will always set it to the correct value. So all seems ok.

> +	else if (lag > LAG_REPORTS * report_size)
> +		stream->oa_buffer.tail = xe_oa_circ_diff(stream, hw_tail,
> +							 LAG_REPORTS * report_size);
>
>	available = xe_oa_circ_diff(stream, stream->oa_buffer.tail, stream->oa_buffer.head);
>	stream->pollin = available >= stream->wait_num_reports * report_size;
> @@ -1416,10 +1422,6 @@ static void xe_oa_stream_disable(struct xe_oa_stream *stream)
>
>	if (stream->sample)
>		hrtimer_cancel(&stream->poll_check_timer);
> -
> -	/* Update stream->oa_buffer.tail to allow any final reports to be read */
> -	if (xe_oa_buffer_check_unlocked(stream))
> -		wake_up(&stream->poll_wq);
>  }
>
>  static int xe_oa_enable_preempt_timeslice(struct xe_oa_stream *stream)
> @@ -1490,6 +1492,11 @@ static int xe_oa_disable_locked(struct xe_oa_stream *stream)
>		ret = xe_oa_enable_preempt_timeslice(stream);
>
>	stream->enabled = false;
> +
> +	/* Update stream->oa_buffer.tail to allow any final reports to be read */
> +	if (xe_oa_buffer_check_unlocked(stream))
> +		wake_up(&stream->poll_wq);
> +
>	return ret;
>  }

Just a few more things to consider and maybe add to this or a new patch:

1. Address this saskhiko comment:

   [High] The newly introduced 32-report lag reduces the maximum possible
   available reports, but `wait_num_reports` validation still allows values
   up to full buffer capacity, causing a permanent hang and `-EIO` on
   overflow.

   Looks like wait_num_reports check here

	if (param.wait_num_reports > param.oa_buffer_size / f->size)

   should be reduced by LAG_REPORTS (maybe make LAG_REPORTS a xe_oa_stream
   property if needed?)

2. Should we do this:

   if (!stream->enabled)
	stream->pollin = available;
   else
	stream->pollin = available >= stream->wait_num_reports * report_size;

   So after stream is disabled, pollin is set even if less than
   wait_num_reports are available (pre-existing issue I think), to unblock
   and enable reading all remaining reports after stream disable?

3. Does the OA buffer now need to be zero'd out in xe_oa_init_oa_buffer(),
   at least we need to remove the comment there:

        /* Zero out the OA buffer since we rely on zero report id and timestamp fields */
        xe_map_memset(stream->oa->xe, &stream->oa_buffer.bo->vmap, 0, 0,
                      xe_bo_size(stream->oa_buffer.bo));

   If we remove the zero'ing out, not sure if any IGT's will need to
   change. Also zero'ing out might have to be re-introduced in the future
   when reading OA registers is removed.

Thanks.
--
Ashutosh

^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH 0/3] Modify the SW tail logic in OA
@ 2026-08-06 22:47 Umesh Nerlige Ramappa
  2026-08-06 22:47 ` [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user Umesh Nerlige Ramappa
  0 siblings, 1 reply; 19+ messages in thread
From: Umesh Nerlige Ramappa @ 2026-08-06 22:47 UTC (permalink / raw)
  To: intel-xe, Ashutosh Dixit

OA unit updates the HW TAIL register to indicate that a new report is
available, although it does not guarantee that the report is visible in
memory. Also the currently running workload contributes to some latency
in seeing this report in memory. In the past we would set some fields in
the OA report and check if the fields are populated to non-zero values
by the HW, but this is no longer sufficient since some parts of the
report may land out of order under heavy workloads. Drop this WA and add
a new logic that just waits for a fixed number of HW TAIL report
increments before returning data to the user. User will always see the
reports lagging by this fixed number, however we do not have realtime
use cases for OAG since OAG reports are mainly post processed.

v2: Rebase
v3: Add Sashiko's review comments
v4: Rebase, checkpatch fixes

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Umesh Nerlige Ramappa (3):
  drm/xe/xe_oa: Clear status only if relevant bits are set
  drm/xe/xe_oa: Avoid checking and setting fields in the OA report
  drm/xe/xe_oa: Add a lag to the reports that is exported to user

 drivers/gpu/drm/xe/xe_oa.c | 95 ++++++--------------------------------
 1 file changed, 13 insertions(+), 82 deletions(-)

-- 
2.51.0

^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user
  2026-08-06 22:47 [PATCH 0/3] Modify the SW tail logic in OA Umesh Nerlige Ramappa
@ 2026-08-06 22:47 ` Umesh Nerlige Ramappa
  2026-08-14 15:42   ` Dixit, Ashutosh
  0 siblings, 1 reply; 19+ messages in thread
From: Umesh Nerlige Ramappa @ 2026-08-06 22:47 UTC (permalink / raw)
  To: intel-xe, Ashutosh Dixit

When running heavy workloads, reading the OA reports too soon does not
guarantee that the report has landed in memory. To make sure correct
reports are copied to user buffer, only return reports that lag the
current HW_TAIL register by 32 reports. This is an empirical number
based on a heavy render workload and several test iterations.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
v2: Fix the LAG logic by using sliding window (Sashiko)
v3: Fix checkpatch warning
---
 drivers/gpu/drm/xe/xe_oa.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
index 5952010e8f51..dc8b402d059a 100644
--- a/drivers/gpu/drm/xe/xe_oa.c
+++ b/drivers/gpu/drm/xe/xe_oa.c
@@ -224,7 +224,7 @@ static bool mert_wa_14026633728(struct xe_oa_stream *s)
 static bool xe_oa_buffer_check_unlocked(struct xe_oa_stream *stream)
 {
 	u32 gtt_offset = xe_bo_ggtt_addr(stream->oa_buffer.bo);
-	u32 hw_tail, partial_report_size, available;
+	u32 hw_tail, partial_report_size, available, lag;
 	int report_size = stream->oa_buffer.format->size;
 	unsigned long flags;
 
@@ -234,17 +234,21 @@ static bool xe_oa_buffer_check_unlocked(struct xe_oa_stream *stream)
 	hw_tail -= gtt_offset;
 
 	/*
-	 * The tail pointer increases in 64 byte (cacheline size), not in report_size
+	 * The hw_tail pointer increases in 64 byte (cacheline size), not in report_size
 	 * increments. Also report size may not be a power of 2. Compute potential
 	 * partially landed report in OA buffer.
 	 */
 	partial_report_size = xe_oa_circ_diff(stream, hw_tail, stream->oa_buffer.tail);
 	partial_report_size %= report_size;
 
-	/* Subtract partial amount off the tail */
+	/* Subtract partial amount off the hw_tail */
 	hw_tail = xe_oa_circ_diff(stream, hw_tail, partial_report_size);
 
-	stream->oa_buffer.tail = hw_tail;
+#define LAG_REPORTS 32
+	lag = xe_oa_circ_diff(stream, hw_tail, stream->oa_buffer.tail);
+	if (lag > LAG_REPORTS * report_size)
+		stream->oa_buffer.tail = xe_oa_circ_diff(stream, hw_tail,
+							 LAG_REPORTS * report_size);
 
 	available = xe_oa_circ_diff(stream, stream->oa_buffer.tail, stream->oa_buffer.head);
 	stream->pollin = available >= stream->wait_num_reports * report_size;
-- 
2.51.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* Re: [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user
  2026-08-06 22:47 ` [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user Umesh Nerlige Ramappa
@ 2026-08-14 15:42   ` Dixit, Ashutosh
  2026-08-14 19:01     ` Umesh Nerlige Ramappa
  0 siblings, 1 reply; 19+ messages in thread
From: Dixit, Ashutosh @ 2026-08-14 15:42 UTC (permalink / raw)
  To: Umesh Nerlige Ramappa; +Cc: intel-xe

On Thu, 06 Aug 2026 15:47:06 -0700, Umesh Nerlige Ramappa wrote:
>

Hi Umesh,

> When running heavy workloads, reading the OA reports too soon does not
> guarantee that the report has landed in memory. To make sure correct
> reports are copied to user buffer, only return reports that lag the
> current HW_TAIL register by 32 reports. This is an empirical number
> based on a heavy render workload and several test iterations.

Looks good overall, but I want to discuss a couple of further points:

1. I know you are doing some verification of OA data in IGT, but I am
   thinking it would be good to have some verification of OA data (of the
   sort that is removed in Patch 2) also in the kernel. So e.g. after a
   report is read, we could set the timestamp field in the report to
   0. Then when we advance the SW tail pointer, we could check if the
   timestamp fields for new reports are non-zero. If we see a 0 timestamp
   value, this would mean that the 32 report delay is not sufficient (for
   who knows what will happen in future platforms). An error in dmesg if we
   see a 0 timestamp should suffise.

   I understand that, because cachelines are landing out of order, a
   non-zero timestamp value doesn't absolutely guarantee that all data is
   correct. But I am thinking statistially we should see 0 timestamp
   values, once in a while, if the 32 report delay were insufficient. So at
   least we'll have some indication from the kernel if that were to happen.

2. The second point is about "what happens in the end", the UMD never sees
   the last 32 reports? Maybe we could do the following to address this:
   when OA stream is disabled, we advance the SW tail pointer to the HW
   tail (overriding the 32 report delay). Then when UMD reads the last bit
   of data, after disabling the stream, they will get all data. Though all
   cachelines might still not have landed, but at least we will have
   advanced the SW tail pointer.

Thoughts?

Thanks.
--
Ashutosh

>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
> v2: Fix the LAG logic by using sliding window (Sashiko)
> v3: Fix checkpatch warning
> ---
>  drivers/gpu/drm/xe/xe_oa.c | 12 ++++++++----
>  1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
> index 5952010e8f51..dc8b402d059a 100644
> --- a/drivers/gpu/drm/xe/xe_oa.c
> +++ b/drivers/gpu/drm/xe/xe_oa.c
> @@ -224,7 +224,7 @@ static bool mert_wa_14026633728(struct xe_oa_stream *s)
>  static bool xe_oa_buffer_check_unlocked(struct xe_oa_stream *stream)
>  {
>	u32 gtt_offset = xe_bo_ggtt_addr(stream->oa_buffer.bo);
> -	u32 hw_tail, partial_report_size, available;
> +	u32 hw_tail, partial_report_size, available, lag;
>	int report_size = stream->oa_buffer.format->size;
>	unsigned long flags;
>
> @@ -234,17 +234,21 @@ static bool xe_oa_buffer_check_unlocked(struct xe_oa_stream *stream)
>	hw_tail -= gtt_offset;
>
>	/*
> -	 * The tail pointer increases in 64 byte (cacheline size), not in report_size
> +	 * The hw_tail pointer increases in 64 byte (cacheline size), not in report_size
>	 * increments. Also report size may not be a power of 2. Compute potential
>	 * partially landed report in OA buffer.
>	 */
>	partial_report_size = xe_oa_circ_diff(stream, hw_tail, stream->oa_buffer.tail);
>	partial_report_size %= report_size;
>
> -	/* Subtract partial amount off the tail */
> +	/* Subtract partial amount off the hw_tail */
>	hw_tail = xe_oa_circ_diff(stream, hw_tail, partial_report_size);
>
> -	stream->oa_buffer.tail = hw_tail;
> +#define LAG_REPORTS 32
> +	lag = xe_oa_circ_diff(stream, hw_tail, stream->oa_buffer.tail);
> +	if (lag > LAG_REPORTS * report_size)
> +		stream->oa_buffer.tail = xe_oa_circ_diff(stream, hw_tail,
> +							 LAG_REPORTS * report_size);
>
>	available = xe_oa_circ_diff(stream, stream->oa_buffer.tail, stream->oa_buffer.head);
>	stream->pollin = available >= stream->wait_num_reports * report_size;
> --
> 2.51.0
>

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user
  2026-08-14 15:42   ` Dixit, Ashutosh
@ 2026-08-14 19:01     ` Umesh Nerlige Ramappa
  2026-08-18  4:38       ` Dixit, Ashutosh
  0 siblings, 1 reply; 19+ messages in thread
From: Umesh Nerlige Ramappa @ 2026-08-14 19:01 UTC (permalink / raw)
  To: Dixit, Ashutosh; +Cc: intel-xe

On Fri, Aug 14, 2026 at 08:42:31AM -0700, Dixit, Ashutosh wrote:
>On Thu, 06 Aug 2026 15:47:06 -0700, Umesh Nerlige Ramappa wrote:
>>
>
>Hi Umesh,
>
>> When running heavy workloads, reading the OA reports too soon does not
>> guarantee that the report has landed in memory. To make sure correct
>> reports are copied to user buffer, only return reports that lag the
>> current HW_TAIL register by 32 reports. This is an empirical number
>> based on a heavy render workload and several test iterations.
>
>Looks good overall, but I want to discuss a couple of further points:
>
>1. I know you are doing some verification of OA data in IGT, but I am
>   thinking it would be good to have some verification of OA data (of the
>   sort that is removed in Patch 2) also in the kernel. So e.g. after a
>   report is read, we could set the timestamp field in the report to
>   0. Then when we advance the SW tail pointer, we could check if the
>   timestamp fields for new reports are non-zero. If we see a 0 timestamp
>   value, this would mean that the 32 report delay is not sufficient (for
>   who knows what will happen in future platforms). An error in dmesg if we
>   see a 0 timestamp should suffise.

I am hesitant to write to the OA buffer at all, especially due to the 
different coherence behavior between discrete and integrated. We should 
just address it as an issue/bug at that point. Let me think about it a 
bit and see what we can do if we see an error in future.

>
>   I understand that, because cachelines are landing out of order, a
>   non-zero timestamp value doesn't absolutely guarantee that all data is
>   correct. But I am thinking statistially we should see 0 timestamp
>   values, once in a while, if the 32 report delay were insufficient. So at
>   least we'll have some indication from the kernel if that were to happen.


>
>2. The second point is about "what happens in the end", the UMD never sees
>   the last 32 reports? Maybe we could do the following to address this:
>   when OA stream is disabled, we advance the SW tail pointer to the HW
>   tail (overriding the 32 report delay). Then when UMD reads the last bit
>   of data, after disabling the stream, they will get all data. Though all
>   cachelines might still not have landed, but at least we will have
>   advanced the SW tail pointer.

oh, I missed that part. Yeah, if the stream is disabled, I would need to 
drain the data. I think that would just add a delay for 32 reports, 
based on the timer period before updating the tail to the latest.

Thanks,
Umesh

>
>Thoughts?
>
>Thanks.
>--
>Ashutosh
>
>
>>
>> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>> ---
>> v2: Fix the LAG logic by using sliding window (Sashiko)
>> v3: Fix checkpatch warning
>> ---
>>  drivers/gpu/drm/xe/xe_oa.c | 12 ++++++++----
>>  1 file changed, 8 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
>> index 5952010e8f51..dc8b402d059a 100644
>> --- a/drivers/gpu/drm/xe/xe_oa.c
>> +++ b/drivers/gpu/drm/xe/xe_oa.c
>> @@ -224,7 +224,7 @@ static bool mert_wa_14026633728(struct xe_oa_stream *s)
>>  static bool xe_oa_buffer_check_unlocked(struct xe_oa_stream *stream)
>>  {
>>	u32 gtt_offset = xe_bo_ggtt_addr(stream->oa_buffer.bo);
>> -	u32 hw_tail, partial_report_size, available;
>> +	u32 hw_tail, partial_report_size, available, lag;
>>	int report_size = stream->oa_buffer.format->size;
>>	unsigned long flags;
>>
>> @@ -234,17 +234,21 @@ static bool xe_oa_buffer_check_unlocked(struct xe_oa_stream *stream)
>>	hw_tail -= gtt_offset;
>>
>>	/*
>> -	 * The tail pointer increases in 64 byte (cacheline size), not in report_size
>> +	 * The hw_tail pointer increases in 64 byte (cacheline size), not in report_size
>>	 * increments. Also report size may not be a power of 2. Compute potential
>>	 * partially landed report in OA buffer.
>>	 */
>>	partial_report_size = xe_oa_circ_diff(stream, hw_tail, stream->oa_buffer.tail);
>>	partial_report_size %= report_size;
>>
>> -	/* Subtract partial amount off the tail */
>> +	/* Subtract partial amount off the hw_tail */
>>	hw_tail = xe_oa_circ_diff(stream, hw_tail, partial_report_size);
>>
>> -	stream->oa_buffer.tail = hw_tail;
>> +#define LAG_REPORTS 32
>> +	lag = xe_oa_circ_diff(stream, hw_tail, stream->oa_buffer.tail);
>> +	if (lag > LAG_REPORTS * report_size)
>> +		stream->oa_buffer.tail = xe_oa_circ_diff(stream, hw_tail,
>> +							 LAG_REPORTS * report_size);
>>
>>	available = xe_oa_circ_diff(stream, stream->oa_buffer.tail, stream->oa_buffer.head);
>>	stream->pollin = available >= stream->wait_num_reports * report_size;
>> --
>> 2.51.0
>>

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user
  2026-08-14 19:01     ` Umesh Nerlige Ramappa
@ 2026-08-18  4:38       ` Dixit, Ashutosh
  0 siblings, 0 replies; 19+ messages in thread
From: Dixit, Ashutosh @ 2026-08-18  4:38 UTC (permalink / raw)
  To: Umesh Nerlige Ramappa; +Cc: intel-xe

On Fri, 14 Aug 2026 12:01:50 -0700, Umesh Nerlige Ramappa wrote:
>
> On Fri, Aug 14, 2026 at 08:42:31AM -0700, Dixit, Ashutosh wrote:
> > On Thu, 06 Aug 2026 15:47:06 -0700, Umesh Nerlige Ramappa wrote:
> >>
> >
> > Hi Umesh,
> >
> >> When running heavy workloads, reading the OA reports too soon does not
> >> guarantee that the report has landed in memory. To make sure correct
> >> reports are copied to user buffer, only return reports that lag the
> >> current HW_TAIL register by 32 reports. This is an empirical number
> >> based on a heavy render workload and several test iterations.
> >
> > Looks good overall, but I want to discuss a couple of further points:
> >
> > 1. I know you are doing some verification of OA data in IGT, but I am
> >   thinking it would be good to have some verification of OA data (of the
> >   sort that is removed in Patch 2) also in the kernel. So e.g. after a
> >   report is read, we could set the timestamp field in the report to
> >   0. Then when we advance the SW tail pointer, we could check if the
> >   timestamp fields for new reports are non-zero. If we see a 0 timestamp
> >   value, this would mean that the 32 report delay is not sufficient (for
> >   who knows what will happen in future platforms). An error in dmesg if we
> >   see a 0 timestamp should suffise.
>
> I am hesitant to write to the OA buffer at all, especially due to the
> different coherence behavior between discrete and integrated.
> We should just address it as an issue/bug at that point. Let me think
> about it a bit and see what we can do if we see an error in future.

OK, we can leave the validation in IGT, instead of the kernel, but we
should do it for a long enough time, like several passes through the OA
buffer, to catch any out of order cache lines, if the 32 report delay is
too short. Thanks.

> >
> >   I understand that, because cachelines are landing out of order, a
> >   non-zero timestamp value doesn't absolutely guarantee that all data is
> >   correct. But I am thinking statistially we should see 0 timestamp
> >   values, once in a while, if the 32 report delay were insufficient. So at
> >   least we'll have some indication from the kernel if that were to happen.
>
>
> >
> > 2. The second point is about "what happens in the end", the UMD never sees
> >   the last 32 reports? Maybe we could do the following to address this:
> >   when OA stream is disabled, we advance the SW tail pointer to the HW
> >   tail (overriding the 32 report delay). Then when UMD reads the last bit
> >   of data, after disabling the stream, they will get all data. Though all
> >   cachelines might still not have landed, but at least we will have
> >   advanced the SW tail pointer.
>
> oh, I missed that part. Yeah, if the stream is disabled, I would need to
> drain the data. I think that would just add a delay for 32 reports, based
> on the timer period before updating the tail to the latest.
>
> Thanks,
> Umesh
>
> >
> > Thoughts?
> >
> > Thanks.
> > --
> > Ashutosh
> >
> >
> >>
> >> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> >> ---
> >> v2: Fix the LAG logic by using sliding window (Sashiko)
> >> v3: Fix checkpatch warning
> >> ---
> >>  drivers/gpu/drm/xe/xe_oa.c | 12 ++++++++----
> >>  1 file changed, 8 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
> >> index 5952010e8f51..dc8b402d059a 100644
> >> --- a/drivers/gpu/drm/xe/xe_oa.c
> >> +++ b/drivers/gpu/drm/xe/xe_oa.c
> >> @@ -224,7 +224,7 @@ static bool mert_wa_14026633728(struct xe_oa_stream *s)
> >>  static bool xe_oa_buffer_check_unlocked(struct xe_oa_stream *stream)
> >>  {
> >>	u32 gtt_offset = xe_bo_ggtt_addr(stream->oa_buffer.bo);
> >> -	u32 hw_tail, partial_report_size, available;
> >> +	u32 hw_tail, partial_report_size, available, lag;
> >>	int report_size = stream->oa_buffer.format->size;
> >>	unsigned long flags;
> >>
> >> @@ -234,17 +234,21 @@ static bool xe_oa_buffer_check_unlocked(struct xe_oa_stream *stream)
> >>	hw_tail -= gtt_offset;
> >>
> >>	/*
> >> -	 * The tail pointer increases in 64 byte (cacheline size), not in report_size
> >> +	 * The hw_tail pointer increases in 64 byte (cacheline size), not in report_size
> >>	 * increments. Also report size may not be a power of 2. Compute potential
> >>	 * partially landed report in OA buffer.
> >>	 */
> >>	partial_report_size = xe_oa_circ_diff(stream, hw_tail, stream->oa_buffer.tail);
> >>	partial_report_size %= report_size;
> >>
> >> -	/* Subtract partial amount off the tail */
> >> +	/* Subtract partial amount off the hw_tail */
> >>	hw_tail = xe_oa_circ_diff(stream, hw_tail, partial_report_size);
> >>
> >> -	stream->oa_buffer.tail = hw_tail;
> >> +#define LAG_REPORTS 32
> >> +	lag = xe_oa_circ_diff(stream, hw_tail, stream->oa_buffer.tail);
> >> +	if (lag > LAG_REPORTS * report_size)
> >> +		stream->oa_buffer.tail = xe_oa_circ_diff(stream, hw_tail,
> >> +							 LAG_REPORTS * report_size);
> >>
> >>	available = xe_oa_circ_diff(stream, stream->oa_buffer.tail, stream->oa_buffer.head);
> >>	stream->pollin = available >= stream->wait_num_reports * report_size;
> >> --
> >> 2.51.0
> >>

^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH 0/3] Modify the SW tail logic in OA
@ 2026-07-30 23:35 Umesh Nerlige Ramappa
  2026-07-30 23:35 ` [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user Umesh Nerlige Ramappa
  0 siblings, 1 reply; 19+ messages in thread
From: Umesh Nerlige Ramappa @ 2026-07-30 23:35 UTC (permalink / raw)
  To: intel-xe, Ashutosh Dixit

OA unit updates the HW TAIL register to indicate that a new report is
available, although it does not guarantee that the report is visible in
memory. Also the currently running workload contributes to some latency
in seeing this report in memory. In the past we would set some fields in
the OA report and check if the fields are populated to non-zero values
by the HW, but this is no longer sufficient since some parts of the
report may land out of order under heavy workloads. Drop this WA and add
a new logic that just waits for a fixed number of HW TAIL report
increments before returning data to the user. User will always see the
reports lagging by this fixed number, however we do not have realtime
use cases for OAG since OAG reports are mainly post processed.

v2: Rebase
v3: Add Sashiko's review comments

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Umesh Nerlige Ramappa (3):
  drm/xe/xe_oa: Clear status only if relevant bits are set
  drm/xe/xe_oa: Avoid checking and setting fields in the OA report
  drm/xe/xe_oa: Add a lag to the reports that is exported to user

 drivers/gpu/drm/xe/xe_oa.c | 94 +++++---------------------------------
 1 file changed, 12 insertions(+), 82 deletions(-)

-- 
2.51.0

^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user
  2026-07-30 23:35 [PATCH 0/3] Modify the SW tail logic in OA Umesh Nerlige Ramappa
@ 2026-07-30 23:35 ` Umesh Nerlige Ramappa
  0 siblings, 0 replies; 19+ messages in thread
From: Umesh Nerlige Ramappa @ 2026-07-30 23:35 UTC (permalink / raw)
  To: intel-xe, Ashutosh Dixit

When running heavy workloads, reading the OA reports too soon does not
guarantee that the report has landed in memory. To make sure correct
reports are copied to user buffer, only return reports that lag the
current HW_TAIL register by 32 reports. This is an empirical number
based on a heavy render workload and several test iterations.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
v2: Fix the LAG logic by using sliding window (Sashiko)
---
 drivers/gpu/drm/xe/xe_oa.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
index c7f9c3955cb5..731b56684439 100644
--- a/drivers/gpu/drm/xe/xe_oa.c
+++ b/drivers/gpu/drm/xe/xe_oa.c
@@ -224,7 +224,7 @@ static bool mert_wa_14026633728(struct xe_oa_stream *s)
 static bool xe_oa_buffer_check_unlocked(struct xe_oa_stream *stream)
 {
 	u32 gtt_offset = xe_bo_ggtt_addr(stream->oa_buffer.bo);
-	u32 hw_tail, partial_report_size, available;
+	u32 hw_tail, partial_report_size, available, lag;
 	int report_size = stream->oa_buffer.format->size;
 	unsigned long flags;
 
@@ -234,17 +234,20 @@ static bool xe_oa_buffer_check_unlocked(struct xe_oa_stream *stream)
 	hw_tail -= gtt_offset;
 
 	/*
-	 * The tail pointer increases in 64 byte (cacheline size), not in report_size
+	 * The hw_tail pointer increases in 64 byte (cacheline size), not in report_size
 	 * increments. Also report size may not be a power of 2. Compute potential
 	 * partially landed report in OA buffer.
 	 */
 	partial_report_size = xe_oa_circ_diff(stream, hw_tail, stream->oa_buffer.tail);
 	partial_report_size %= report_size;
 
-	/* Subtract partial amount off the tail */
+	/* Subtract partial amount off the hw_tail */
 	hw_tail = xe_oa_circ_diff(stream, hw_tail, partial_report_size);
 
-	stream->oa_buffer.tail = hw_tail;
+#define LAG_REPORTS 32
+	lag = xe_oa_circ_diff(stream, hw_tail, stream->oa_buffer.tail);
+	if (lag > LAG_REPORTS * report_size)
+		stream->oa_buffer.tail = xe_oa_circ_diff(stream, hw_tail, LAG_REPORTS * report_size);
 
 	available = xe_oa_circ_diff(stream, stream->oa_buffer.tail, stream->oa_buffer.head);
 	stream->pollin = available >= stream->wait_num_reports * report_size;
-- 
2.51.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH 0/3] Modify the SW tail logic in OA
@ 2026-07-22 21:54 Umesh Nerlige Ramappa
  2026-07-22 21:54 ` [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user Umesh Nerlige Ramappa
  0 siblings, 1 reply; 19+ messages in thread
From: Umesh Nerlige Ramappa @ 2026-07-22 21:54 UTC (permalink / raw)
  To: intel-xe, Ashutosh Dixit

OA unit updates the HW TAIL register to indicate that a new report is
available, although it does not guarantee that the report is visible in
memory. Also the currently running workload contributes to some latency
in seeing this report in memory. In the past we would set some fields in
the OA report and check if the fields are populated to non-zero values
by the HW, but this is no longer sufficient since some parts of the
report may land out of order under heavy workloads. Drop this WA and add
a new logic that just waits for a fixed number of HW TAIL report
increments before returning data to the user. User will always see the
reports lagging by this fixed number, however we do not have realtime
use cases for OAG since OAG reports are mainly post processed.

v2: Rebase

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Umesh Nerlige Ramappa (3):
  drm/xe/xe_oa: Clear status only if relevant bits are set
  drm/xe/xe_oa: Avoid checking and setting fields in the OA report
  drm/xe/xe_oa: Add a lag to the reports that is exported to user

 drivers/gpu/drm/xe/xe_oa.c | 94 +++++---------------------------------
 1 file changed, 12 insertions(+), 82 deletions(-)

-- 
2.51.0

^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user
  2026-07-22 21:54 [PATCH 0/3] Modify the SW tail logic in OA Umesh Nerlige Ramappa
@ 2026-07-22 21:54 ` Umesh Nerlige Ramappa
  0 siblings, 0 replies; 19+ messages in thread
From: Umesh Nerlige Ramappa @ 2026-07-22 21:54 UTC (permalink / raw)
  To: intel-xe, Ashutosh Dixit

When running heavy workloads, reading the OA reports too soon does not
guarantee that the report has landed in memory. To make sure correct
reports are copied to user buffer, only return reports that lag the
current HW_TAIL register by 32 reports. This is an empirical number
based on a heavy render workload and several test iterations.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 drivers/gpu/drm/xe/xe_oa.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
index c7f9c3955cb5..87cbd15eb7a2 100644
--- a/drivers/gpu/drm/xe/xe_oa.c
+++ b/drivers/gpu/drm/xe/xe_oa.c
@@ -224,7 +224,7 @@ static bool mert_wa_14026633728(struct xe_oa_stream *s)
 static bool xe_oa_buffer_check_unlocked(struct xe_oa_stream *stream)
 {
 	u32 gtt_offset = xe_bo_ggtt_addr(stream->oa_buffer.bo);
-	u32 hw_tail, partial_report_size, available;
+	u32 hw_tail, partial_report_size, available, lag;
 	int report_size = stream->oa_buffer.format->size;
 	unsigned long flags;
 
@@ -234,17 +234,20 @@ static bool xe_oa_buffer_check_unlocked(struct xe_oa_stream *stream)
 	hw_tail -= gtt_offset;
 
 	/*
-	 * The tail pointer increases in 64 byte (cacheline size), not in report_size
+	 * The hw_tail pointer increases in 64 byte (cacheline size), not in report_size
 	 * increments. Also report size may not be a power of 2. Compute potential
 	 * partially landed report in OA buffer.
 	 */
 	partial_report_size = xe_oa_circ_diff(stream, hw_tail, stream->oa_buffer.tail);
 	partial_report_size %= report_size;
 
-	/* Subtract partial amount off the tail */
+	/* Subtract partial amount off the hw_tail */
 	hw_tail = xe_oa_circ_diff(stream, hw_tail, partial_report_size);
 
-	stream->oa_buffer.tail = hw_tail;
+#define LAG_REPORTS 32
+	lag = xe_oa_circ_diff(stream, hw_tail, stream->oa_buffer.tail);
+	if (lag >= LAG_REPORTS * report_size)
+		stream->oa_buffer.tail = hw_tail;
 
 	available = xe_oa_circ_diff(stream, stream->oa_buffer.tail, stream->oa_buffer.head);
 	stream->pollin = available >= stream->wait_num_reports * report_size;
-- 
2.51.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH 0/3] Modify the SW tail logic in OA
@ 2026-07-21 23:48 Umesh Nerlige Ramappa
  2026-07-21 23:48 ` [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user Umesh Nerlige Ramappa
  0 siblings, 1 reply; 19+ messages in thread
From: Umesh Nerlige Ramappa @ 2026-07-21 23:48 UTC (permalink / raw)
  To: intel-xe, Ashutosh Dixit

OA unit updates the HW TAIL register to indicate that a new report is
available, although it does not guarantee that the report is visible in
memory. Also the currently running workload contributes to some latency
in seeing this report in memory. In the past we would set some fields in
the OA report and check if the fields are populated to non-zero values
by the HW, but this is no longer sufficient since some parts of the
report may land out of order under heavy workloads. Drop this WA and add
a new logic that just waits for a fixed number of HW TAIL report
increments before returning data to the user. User will always see the
reports lagging by this fixed number, however we do not have realtime
use cases for OAG since OAG reports are mainly post processed.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Umesh Nerlige Ramappa (3):
  drm/xe/xe_oa: Clear status only if relevant bits are set
  drm/xe/xe_oa: Avoid checking and setting fields in the OA report
  drm/xe/xe_oa: Add a lag to the reports that is exported to user

 drivers/gpu/drm/xe/xe_oa.c | 88 ++++++--------------------------------
 1 file changed, 12 insertions(+), 76 deletions(-)

-- 
2.51.0

^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user
  2026-07-21 23:48 [PATCH 0/3] Modify the SW tail logic in OA Umesh Nerlige Ramappa
@ 2026-07-21 23:48 ` Umesh Nerlige Ramappa
  0 siblings, 0 replies; 19+ messages in thread
From: Umesh Nerlige Ramappa @ 2026-07-21 23:48 UTC (permalink / raw)
  To: intel-xe, Ashutosh Dixit

When running heavy workloads, reading the OA reports too soon does not
guarantee that the report has landed in memory. To make sure correct
reports are copied to user buffer, only return reports that lag the
current HW_TAIL register by 32 reports. This is an empirical number
based on a heavy render workload and several test iterations.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 drivers/gpu/drm/xe/xe_oa.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
index c5c4c4186e58..62eae544714a 100644
--- a/drivers/gpu/drm/xe/xe_oa.c
+++ b/drivers/gpu/drm/xe/xe_oa.c
@@ -216,7 +216,7 @@ static u32 xe_oa_hw_tail_read(struct xe_oa_stream *stream)
 static bool xe_oa_buffer_check_unlocked(struct xe_oa_stream *stream)
 {
 	u32 gtt_offset = xe_bo_ggtt_addr(stream->oa_buffer.bo);
-	u32 hw_tail, partial_report_size, available;
+	u32 hw_tail, partial_report_size, available, lag;
 	int report_size = stream->oa_buffer.format->size;
 	unsigned long flags;
 
@@ -226,17 +226,20 @@ static bool xe_oa_buffer_check_unlocked(struct xe_oa_stream *stream)
 	hw_tail -= gtt_offset;
 
 	/*
-	 * The tail pointer increases in 64 byte (cacheline size), not in report_size
+	 * The hw_tail pointer increases in 64 byte (cacheline size), not in report_size
 	 * increments. Also report size may not be a power of 2. Compute potential
 	 * partially landed report in OA buffer.
 	 */
 	partial_report_size = xe_oa_circ_diff(stream, hw_tail, stream->oa_buffer.tail);
 	partial_report_size %= report_size;
 
-	/* Subtract partial amount off the tail */
+	/* Subtract partial amount off the hw_tail */
 	hw_tail = xe_oa_circ_diff(stream, hw_tail, partial_report_size);
 
-	stream->oa_buffer.tail = hw_tail;
+#define LAG_REPORTS 32
+	lag = xe_oa_circ_diff(stream, hw_tail, stream->oa_buffer.tail);
+	if (lag >= LAG_REPORTS * report_size)
+		stream->oa_buffer.tail = hw_tail;
 
 	available = xe_oa_circ_diff(stream, stream->oa_buffer.tail, stream->oa_buffer.head);
 	stream->pollin = available >= stream->wait_num_reports * report_size;
-- 
2.51.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

end of thread, other threads:[~2026-08-24 15:57 UTC | newest]

Thread overview: 19+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-08-21 20:07 [PATCH 0/3] Modify the SW tail logic in OA Umesh Nerlige Ramappa
2026-08-21 20:07 ` [PATCH 1/3] drm/xe/xe_oa: Clear status only if relevant bits are set Umesh Nerlige Ramappa
2026-08-21 20:07 ` [PATCH 2/3] drm/xe/xe_oa: Avoid checking and setting fields in the OA report Umesh Nerlige Ramappa
2026-08-21 20:24   ` sashiko-bot
2026-08-21 20:07 ` [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user Umesh Nerlige Ramappa
2026-08-21 20:21   ` sashiko-bot
2026-08-21 20:14 ` ✓ CI.KUnit: success for Modify the SW tail logic in OA Patchwork
2026-08-21 21:03 ` ✓ Xe.CI.BAT: " Patchwork
2026-08-21 22:35 ` ✓ Xe.CI.FULL: " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2026-08-21 22:23 [PATCH 0/3] " Umesh Nerlige Ramappa
2026-08-21 22:23 ` [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user Umesh Nerlige Ramappa
2026-08-21 22:37   ` sashiko-bot
2026-08-24 15:57   ` Dixit, Ashutosh
2026-08-06 22:47 [PATCH 0/3] Modify the SW tail logic in OA Umesh Nerlige Ramappa
2026-08-06 22:47 ` [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user Umesh Nerlige Ramappa
2026-08-14 15:42   ` Dixit, Ashutosh
2026-08-14 19:01     ` Umesh Nerlige Ramappa
2026-08-18  4:38       ` Dixit, Ashutosh
2026-07-30 23:35 [PATCH 0/3] Modify the SW tail logic in OA Umesh Nerlige Ramappa
2026-07-30 23:35 ` [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user Umesh Nerlige Ramappa
2026-07-22 21:54 [PATCH 0/3] Modify the SW tail logic in OA Umesh Nerlige Ramappa
2026-07-22 21:54 ` [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user Umesh Nerlige Ramappa
2026-07-21 23:48 [PATCH 0/3] Modify the SW tail logic in OA Umesh Nerlige Ramappa
2026-07-21 23:48 ` [PATCH 3/3] drm/xe/xe_oa: Add a lag to the reports that is exported to user Umesh Nerlige Ramappa

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.