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From: sashiko-bot@kernel.org
To: "Jia Wang" <wangjia@ultrarisc.com>
Cc: conor+dt@kernel.org, vkoul@kernel.org,
	devicetree@vger.kernel.org, Frank.Li@kernel.org,
	dmaengine@vger.kernel.org, robh@kernel.org
Subject: Re: [PATCH 11/12] riscv: dts: ultrarisc: Add Shenzhen Rongda M0 board device tree
Date: Tue, 25 Aug 2026 06:16:15 +0000	[thread overview]
Message-ID: <20260825061615.732861F00A3D@smtp.kernel.org> (raw)
In-Reply-To: <20260824-ultrarisc-dts-v1-11-61ab7aebe9e5@ultrarisc.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Device tree binding header is placed in the local architecture directory instead of the standard include/dt-bindings/ path.
--

--- Patch [11]: [PATCH 11/12] riscv: dts: ultrarisc: Add Shenzhen Rongda M0 board device tree ---
commit 67b0db49374b5791844e1a3b66fc62faab120bb7
Author: Jia Wang <wangjia@ultrarisc.com>

riscv: dts: ultrarisc: Add Shenzhen Rongda M0 board device tree

Adds the device tree and pinctrl configurations for the Shenzhen Rongda M0
mATX motherboard, which is based on the UltraRISC DP1000 SoC.

> diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h b/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h
> new file mode 100644
> index 0000000000000..4668e45d2335d
> --- /dev/null
> +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h
> @@ -0,0 +1,63 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.
> + */
> +
> +#ifndef _DP1000_PINCTRL_H
> +#define _DP1000_PINCTRL_H
> +
> +#define PA0		0
> +#define PA1		1

[Severity: Low]
Should this device tree binding header be placed in the standard
include/dt-bindings/pinctrl/ directory instead of the local architecture
directory?

Keeping it here might prevent the pinctrl driver from naturally sharing these
hardware ABI constants without violating include paths or duplicating
definitions.

[ ... ]

> diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi
> new file mode 100644
> index 0000000000000..ab927c6cd6146
> --- /dev/null
> +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi
> @@ -0,0 +1,79 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.
> + */
> +
> +#include "dp1000.dtsi"
> +#include "dp1000-pinctrl.h"

[Severity: Low]
If the header is moved to the standard include/dt-bindings/ path, would this
inclusion need to be updated to use the standard <dt-bindings/...> format?

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824-ultrarisc-dts-v1-0-61ab7aebe9e5@ultrarisc.com?part=11

  parent reply	other threads:[~2026-08-25  6:16 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-24  5:54 [PATCH 00/12] riscv: Add device tree support for UltraRISC DP1000 Jia Wang via B4 Relay
2026-08-24  5:54 ` [PATCH 01/12] dt-bindings: riscv: cpus: Fix yamllint style issues Jia Wang via B4 Relay
2026-08-24 16:35   ` Conor Dooley
2026-09-02  1:15     ` Paul Walmsley
2026-08-24  5:54 ` [PATCH 02/12] dt-bindings: vendor-prefixes: Add shenrongda Jia Wang via B4 Relay
2026-08-24 17:03   ` Conor Dooley
2026-08-24  5:54 ` [PATCH 03/12] dt-bindings: riscv: cpus: Add UltraRISC CP100 compatible Jia Wang via B4 Relay
2026-08-24 17:02   ` Conor Dooley
2026-08-24  5:54 ` [PATCH 04/12] dt-bindings: riscv: Add UltraRISC DP1000 board compatibles Jia Wang via B4 Relay
2026-08-24 17:04   ` Conor Dooley
2026-08-24  5:54 ` [PATCH 05/12] dt-bindings: timer: Add UltraRISC DP1000 CLINT Jia Wang via B4 Relay
2026-08-24 17:05   ` Conor Dooley
2026-08-24  5:54 ` [PATCH 06/12] spi: dt-bindings: snps,dw-apb-ssi: Add compatible for UltraRISC DP1000 SoC Jia Wang via B4 Relay
2026-08-24 17:07   ` Conor Dooley
2026-08-24 17:15     ` Conor Dooley
2026-08-25  8:16       ` Jia Wang
2026-08-31 21:27   ` Mark Brown
2026-08-24  5:54 ` [PATCH 07/12] dt-bindings: i2c: dw: " Jia Wang via B4 Relay
2026-08-24 17:07   ` Conor Dooley
2026-08-24 17:14     ` Conor Dooley
2026-08-25  8:45       ` Jia Wang
2026-08-24  5:54 ` [PATCH 08/12] dt-bindings: net: snps,dwmac: " Jia Wang via B4 Relay
2026-08-24 17:09   ` Conor Dooley
2026-08-24 17:13     ` Conor Dooley
2026-08-25 10:12       ` Jia Wang
2026-08-27  8:17         ` Jia Wang
2026-08-25  6:16   ` sashiko-bot
2026-08-24  5:54 ` [PATCH 09/12] dt-bindings: dma: snps,dw-axi-dmac: Add UltraRISC DP1000 compatible Jia Wang via B4 Relay
2026-08-24 17:03   ` Conor Dooley
2026-08-24 17:11     ` Conor Dooley
2026-08-26  5:31       ` Jia Wang
2026-08-24  5:54 ` [PATCH 10/12] riscv: dts: ultrarisc: Add initial device tree for UltraRISC DP1000 Jia Wang via B4 Relay
2026-08-25  6:16   ` sashiko-bot
2026-08-24  5:54 ` [PATCH 11/12] riscv: dts: ultrarisc: Add Shenzhen Rongda M0 board device tree Jia Wang via B4 Relay
2026-08-24 13:02   ` Andrew Lunn
2026-08-27  2:19     ` Jia Wang
2026-08-27  2:46       ` Andrew Lunn
2026-08-27  4:54         ` Jia Wang
2026-08-25  6:16   ` sashiko-bot [this message]
2026-08-24  5:54 ` [PATCH 12/12] riscv: dts: ultrarisc: Add Milk-V Titan " Jia Wang via B4 Relay
2026-08-24 13:06   ` Andrew Lunn
2026-08-27  2:24     ` Jia Wang
2026-08-25  6:16   ` sashiko-bot

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