From: Conor Dooley <conor@kernel.org>
To: "Ousherovitch, Alex" <aousherovitch@rambus.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>,
Conor Dooley <conor+dt@kernel.org>,
"David S. Miller" <davem@davemloft.net>,
Herbert Xu <herbert@gondor.apana.org.au>,
Jonathan Corbet <corbet@lwn.net>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <pjw@kernel.org>, Rob Herring <robh@kernel.org>,
"Krishnamoorthy, Saravanakrishnan" <skrishnamoorthy@rambus.com>,
Shuah Khan <shuah@kernel.org>, Alexandre Ghiti <alex@ghiti.fr>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"Wittenauer, Joel" <Joel.Wittenauer@cryptography.com>,
"linux-api@vger.kernel.org" <linux-api@vger.kernel.org>,
"linux-crypto@vger.kernel.org" <linux-crypto@vger.kernel.org>,
"linux-doc@vger.kernel.org" <linux-doc@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-kselftest@vger.kernel.org"
<linux-kselftest@vger.kernel.org>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
Shuah Khan <skhan@linuxfoundation.org>,
"Nguyen, Thi" <thin@rambus.com>
Subject: Re: [PATCH v4 01/19] dt-bindings: crypto: add Rambus CryptoManager Hub
Date: Thu, 27 Aug 2026 18:14:21 +0100 [thread overview]
Message-ID: <20260827-crust-giddy-6888a52871a5@spud> (raw)
In-Reply-To: <SA3PR04MB9001B48FBE7B7C3EB81C5338D7AD2@SA3PR04MB9001.namprd04.prod.outlook.com>
[-- Attachment #1: Type: text/plain, Size: 3957 bytes --]
On Thu, Aug 27, 2026 at 01:39:35AM +0000, Ousherovitch, Alex wrote:
> On Wed, Aug 26, 2026 at 06:02:16PM +0100, Conor Dooley wrote:
> > On Tue, Aug 25, 2026 at 03:15:20PM -0700, Alex Ousherovitch wrote:
> > > + command ABI). A specific SoC integration should list its own
> > > + "<vendor>,<soc>-cmh" compatible first with "rambus,cmh-v1030" as a
> > > + fallback; that extended form will be added when such a platform is
> > > + upstreamed.
> >
> > This commentary should just not be here.
> > Instead, do what's been done in sifive,clint.yaml for the clint2.
>
> Will do -- I'll drop the prose and model the compatible on sifive,clint2
> so the schema itself requires an SoC-specific compatible ahead of the IP
> fallback:
>
> compatible:
> items:
> - {}
> - const: rambus,cmh-v1030
>
> Since that makes the two-item form the only valid one, I'll also move the
> binding example (and our test DTs) to it, using a placeholder SoC-specific
> compatible under the now-registered rambus prefix, e.g.
>
> compatible = "rambus,<soc>-cmh", "rambus,cmh-v1030";
>
> and swap in the real "<vendor>,<soc>-cmh" string once the first integrating
> platform is upstreamed.
With the correct syntax, which I think the sifive example I copied from
doesn't have, but
Documentation/devicetree/bindings/crypto/inside-secure,safexcel-eip93.yaml
does, fake compatibles won't be permitted (and we would probably object
to seeing them too). What we want is the binding to force people to use
a soc-specific one to pass validation. Unfortunately this does mean you
can't have an example because it won't pass the validation, which is
annoying!
>
> > > + rambus,cores:
> > > + $ref: /schemas/types.yaml#/definitions/uint32-array
> > > + items:
> > > + enum: [0x02, 0x03, 0x04, 0x05, 0x08, 0x09, 0x0a, 0x18]
> > [...]
> >
> > You could just make this a string array, and then you'd not need this
> > mapping of unintelligible hex values. Of course then your driver has to
> > do it, but I'd rather see understandable (and portable, since a new
> > revision could change the IDs) values in DT.
>
> Agreed, that's clearly better. The next revision makes rambus,cores a
> string array and maps the names to core IDs in the driver, so the
> numbering can change across IP revisions without touching the DT:
>
> rambus,cores:
> $ref: /schemas/types.yaml#/definitions/string-array
> items:
> enum: [hc, aes, sm4, sm3, hcq, qse, pke, ccp]
>
> (keeping the affinity semantics in the description -- a core appears on at
> most one queue, unlisted cores are load-balanced -- just without the hex
> table.)
>
> > > +required:
> > > + - compatible
> > > + - reg
> > > + - "#address-cells"
> > > + - "#size-cells"
> >
> > Surely clocks are also mandatory?
>
> They can't be mandatory for this binding -- there may be no clock provider
> for the node to reference:
>
> - CMH is shared between hosts. The SIC presents up to four host
> interfaces; a designated management host owns the privileged
> configuration (clock, reset and power) while the other hosts are
> granted only a subset of mailboxes. A node describing a non-management
> host therefore has no clock/reset provider to point at -- those lines
> are driven by the management host or an SoC power controller.
>
> - Even where a provider exists, only the main "core" clock is always
> fitted; "core-div2" is present only on builds that include the
> side-channel-protected slow cores, and "rt" is the real-time tick,
> which is why clock-names is a oneOf of subsets rather than a fixed
> list.
>
> So I'd keep clocks (and reset-gpios) optional. I can add a one-line,
> hardware-framed note to the description if you'd like that rationale on
> record.
Please do, yeah.
Thanks,
Conor.
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WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: "Ousherovitch, Alex" <aousherovitch@rambus.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>,
Conor Dooley <conor+dt@kernel.org>,
"David S. Miller" <davem@davemloft.net>,
Herbert Xu <herbert@gondor.apana.org.au>,
Jonathan Corbet <corbet@lwn.net>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <pjw@kernel.org>, Rob Herring <robh@kernel.org>,
"Krishnamoorthy, Saravanakrishnan" <skrishnamoorthy@rambus.com>,
Shuah Khan <shuah@kernel.org>, Alexandre Ghiti <alex@ghiti.fr>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"Wittenauer, Joel" <Joel.Wittenauer@cryptography.com>,
"linux-api@vger.kernel.org" <linux-api@vger.kernel.org>,
"linux-crypto@vger.kernel.org" <linux-crypto@vger.kernel.org>,
"linux-doc@vger.kernel.org" <linux-doc@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-kselftest@vger.kernel.org"
<linux-kselftest@vger.kernel.org>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
Shuah Khan <skhan@linuxfoundation.org>,
"Nguyen, Thi" <thin@rambus.com>
Subject: Re: [PATCH v4 01/19] dt-bindings: crypto: add Rambus CryptoManager Hub
Date: Thu, 27 Aug 2026 18:14:21 +0100 [thread overview]
Message-ID: <20260827-crust-giddy-6888a52871a5@spud> (raw)
In-Reply-To: <SA3PR04MB9001B48FBE7B7C3EB81C5338D7AD2@SA3PR04MB9001.namprd04.prod.outlook.com>
[-- Attachment #1.1: Type: text/plain, Size: 3957 bytes --]
On Thu, Aug 27, 2026 at 01:39:35AM +0000, Ousherovitch, Alex wrote:
> On Wed, Aug 26, 2026 at 06:02:16PM +0100, Conor Dooley wrote:
> > On Tue, Aug 25, 2026 at 03:15:20PM -0700, Alex Ousherovitch wrote:
> > > + command ABI). A specific SoC integration should list its own
> > > + "<vendor>,<soc>-cmh" compatible first with "rambus,cmh-v1030" as a
> > > + fallback; that extended form will be added when such a platform is
> > > + upstreamed.
> >
> > This commentary should just not be here.
> > Instead, do what's been done in sifive,clint.yaml for the clint2.
>
> Will do -- I'll drop the prose and model the compatible on sifive,clint2
> so the schema itself requires an SoC-specific compatible ahead of the IP
> fallback:
>
> compatible:
> items:
> - {}
> - const: rambus,cmh-v1030
>
> Since that makes the two-item form the only valid one, I'll also move the
> binding example (and our test DTs) to it, using a placeholder SoC-specific
> compatible under the now-registered rambus prefix, e.g.
>
> compatible = "rambus,<soc>-cmh", "rambus,cmh-v1030";
>
> and swap in the real "<vendor>,<soc>-cmh" string once the first integrating
> platform is upstreamed.
With the correct syntax, which I think the sifive example I copied from
doesn't have, but
Documentation/devicetree/bindings/crypto/inside-secure,safexcel-eip93.yaml
does, fake compatibles won't be permitted (and we would probably object
to seeing them too). What we want is the binding to force people to use
a soc-specific one to pass validation. Unfortunately this does mean you
can't have an example because it won't pass the validation, which is
annoying!
>
> > > + rambus,cores:
> > > + $ref: /schemas/types.yaml#/definitions/uint32-array
> > > + items:
> > > + enum: [0x02, 0x03, 0x04, 0x05, 0x08, 0x09, 0x0a, 0x18]
> > [...]
> >
> > You could just make this a string array, and then you'd not need this
> > mapping of unintelligible hex values. Of course then your driver has to
> > do it, but I'd rather see understandable (and portable, since a new
> > revision could change the IDs) values in DT.
>
> Agreed, that's clearly better. The next revision makes rambus,cores a
> string array and maps the names to core IDs in the driver, so the
> numbering can change across IP revisions without touching the DT:
>
> rambus,cores:
> $ref: /schemas/types.yaml#/definitions/string-array
> items:
> enum: [hc, aes, sm4, sm3, hcq, qse, pke, ccp]
>
> (keeping the affinity semantics in the description -- a core appears on at
> most one queue, unlisted cores are load-balanced -- just without the hex
> table.)
>
> > > +required:
> > > + - compatible
> > > + - reg
> > > + - "#address-cells"
> > > + - "#size-cells"
> >
> > Surely clocks are also mandatory?
>
> They can't be mandatory for this binding -- there may be no clock provider
> for the node to reference:
>
> - CMH is shared between hosts. The SIC presents up to four host
> interfaces; a designated management host owns the privileged
> configuration (clock, reset and power) while the other hosts are
> granted only a subset of mailboxes. A node describing a non-management
> host therefore has no clock/reset provider to point at -- those lines
> are driven by the management host or an SoC power controller.
>
> - Even where a provider exists, only the main "core" clock is always
> fitted; "core-div2" is present only on builds that include the
> side-channel-protected slow cores, and "rt" is the real-time tick,
> which is why clock-names is a oneOf of subsets rather than a fixed
> list.
>
> So I'd keep clocks (and reset-gpios) optional. I can add a one-line,
> hardware-framed note to the description if you'd like that rationale on
> record.
Please do, yeah.
Thanks,
Conor.
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next prev parent reply other threads:[~2026-08-27 17:14 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-25 22:15 [PATCH v4 00/19] crypto: cmh - add Rambus CryptoManager Hub driver Alex Ousherovitch
2026-08-25 22:15 ` Alex Ousherovitch
2026-08-25 22:15 ` [PATCH v4 01/19] dt-bindings: crypto: add Rambus CryptoManager Hub Alex Ousherovitch
2026-08-25 22:15 ` Alex Ousherovitch
2026-08-25 22:28 ` sashiko-bot
2026-08-26 17:02 ` Conor Dooley
2026-08-26 17:02 ` Conor Dooley
2026-08-27 1:39 ` Ousherovitch, Alex
2026-08-27 1:39 ` Ousherovitch, Alex
2026-08-27 17:14 ` Conor Dooley [this message]
2026-08-27 17:14 ` Conor Dooley
2026-08-27 18:21 ` Ousherovitch, Alex
2026-08-27 18:21 ` Ousherovitch, Alex
2026-08-25 22:15 ` [PATCH v4 02/19] crypto: cmh - add core platform driver Alex Ousherovitch
2026-08-25 22:15 ` Alex Ousherovitch
2026-08-25 22:34 ` sashiko-bot
2026-08-25 22:15 ` [PATCH v4 03/19] crypto: cmh - add key provisioning and management Alex Ousherovitch
2026-08-25 22:15 ` Alex Ousherovitch
2026-08-25 22:30 ` sashiko-bot
2026-08-25 22:15 ` [PATCH v4 04/19] crypto: cmh - add SHA-2/SHA-3/SHAKE ahash Alex Ousherovitch
2026-08-25 22:15 ` Alex Ousherovitch
2026-08-25 22:27 ` sashiko-bot
2026-09-11 4:31 ` Herbert Xu
2026-09-11 4:31 ` Herbert Xu
2026-09-11 21:29 ` Ousherovitch, Alex
2026-09-11 21:29 ` Ousherovitch, Alex
2026-08-25 22:15 ` [PATCH v4 05/19] crypto: cmh - add HMAC ahash Alex Ousherovitch
2026-08-25 22:15 ` Alex Ousherovitch
2026-08-25 22:30 ` sashiko-bot
2026-08-25 22:15 ` [PATCH v4 06/19] crypto: cmh - add CSHAKE/KMAC ahash Alex Ousherovitch
2026-08-25 22:15 ` Alex Ousherovitch
2026-08-25 22:30 ` sashiko-bot
2026-08-25 22:15 ` [PATCH v4 07/19] crypto: cmh - add SM3 ahash Alex Ousherovitch
2026-08-25 22:15 ` Alex Ousherovitch
2026-08-25 22:28 ` sashiko-bot
2026-08-25 22:15 ` [PATCH v4 08/19] crypto: cmh - add AES skcipher/aead/cmac Alex Ousherovitch
2026-08-25 22:15 ` Alex Ousherovitch
2026-08-25 22:28 ` sashiko-bot
2026-08-25 22:15 ` [PATCH v4 09/19] crypto: cmh - add SM4 skcipher/aead/cmac/xcbc Alex Ousherovitch
2026-08-25 22:15 ` Alex Ousherovitch
2026-08-25 22:25 ` sashiko-bot
2026-08-25 22:15 ` [PATCH v4 10/19] crypto: cmh - add ChaCha20-Poly1305 Alex Ousherovitch
2026-08-25 22:15 ` Alex Ousherovitch
2026-08-25 22:30 ` sashiko-bot
2026-08-25 22:15 ` [PATCH v4 11/19] crypto: cmh - add DRBG hwrng Alex Ousherovitch
2026-08-25 22:15 ` Alex Ousherovitch
2026-08-25 22:32 ` sashiko-bot
2026-08-25 22:15 ` [PATCH v4 12/19] crypto: cmh - add RSA akcipher Alex Ousherovitch
2026-08-25 22:15 ` Alex Ousherovitch
2026-08-25 22:15 ` [PATCH v4 13/19] crypto: cmh - add ECDSA/SM2 sig Alex Ousherovitch
2026-08-25 22:15 ` Alex Ousherovitch
2026-08-25 22:15 ` [PATCH v4 14/19] crypto: cmh - add ECDH/X25519 kpp Alex Ousherovitch
2026-08-25 22:15 ` Alex Ousherovitch
2026-08-25 22:41 ` sashiko-bot
2026-08-25 22:15 ` [PATCH v4 15/19] crypto: cmh - add ML-KEM/ML-DSA (QSE) Alex Ousherovitch
2026-08-25 22:15 ` Alex Ousherovitch
2026-08-25 22:36 ` sashiko-bot
2026-08-25 22:15 ` [PATCH v4 16/19] crypto: cmh - add SLH-DSA/LMS/XMSS (HCQ) Alex Ousherovitch
2026-08-25 22:15 ` Alex Ousherovitch
2026-08-25 22:37 ` sashiko-bot
2026-08-25 22:15 ` [PATCH v4 17/19] Documentation: ioctl: add CMH ioctl documentation and register 'J' Alex Ousherovitch
2026-08-25 22:15 ` Alex Ousherovitch
2026-08-25 22:34 ` sashiko-bot
2026-08-25 22:15 ` [PATCH v4 18/19] selftests: crypto: cmh - add kselftest for management ioctl Alex Ousherovitch
2026-08-25 22:15 ` Alex Ousherovitch
2026-08-25 22:15 ` [PATCH v4 19/19] MAINTAINERS: add Rambus CryptoManager Hub (CMH) Alex Ousherovitch
2026-08-25 22:15 ` Alex Ousherovitch
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