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From: Chinmay Rath <rathc@linux.ibm.com>
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org,
	harshpb@linux.ibm.com, milesg@linux.ibm.com
Cc: npiggin@gmail.com, richard.henderson@linaro.org,
	vishalc@linux.ibm.com, tshah@linux.ibm.com,
	shivangu@linux.ibm.com, ojaswin@linux.ibm.com,
	aboorvad@linux.ibm.com, amachhiw@linux.ibm.com,
	shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com,
	nikhilks@linux.ibm.com, Chinmay Rath <rathc@linux.ibm.com>
Subject: [PATCH v3 08/37] target/ppc: convert sraw[i] instruction via decode spec
Date: Thu, 27 Aug 2026 18:59:23 +0530	[thread overview]
Message-ID: <20260827133010.278889-9-rathc@linux.ibm.com> (raw)
In-Reply-To: <20260827133010.278889-1-rathc@linux.ibm.com>

From: "Mukesh Kumar Chaurasiya (IBM)" <mkchauras@gmail.com>

Move sraw and srawi to decodetree specification using the @X_rc
format. The existing shift-masking logic from gen_sraw/gen_srawi is
preserved verbatim in the new trans_SRAW/trans_SRAWI handlers.

Signed-off-by: Mukesh Kumar Chaurasiya (IBM) <mkchauras@gmail.com>
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
Reviewed-by: Amit Machhiwal <amachhiw@linux.ibm.com>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
---
 target/ppc/helper.h                        |  2 +-
 target/ppc/insn32.decode                   |  2 ++
 target/ppc/int_helper.c                    |  2 +-
 target/ppc/translate.c                     | 42 ----------------------
 target/ppc/translate/fixedpoint-impl.c.inc | 41 +++++++++++++++++++++
 5 files changed, 45 insertions(+), 44 deletions(-)

diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index a0d08d6192..d4a9334ce8 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -64,7 +64,7 @@ DEF_HELPER_4(DIVWE, tl, env, tl, tl, i32)
 
 DEF_HELPER_FLAGS_1(POPCNTB, TCG_CALL_NO_RWG_SE, tl, tl)
 DEF_HELPER_FLAGS_2(CMPB, TCG_CALL_NO_RWG_SE, tl, tl, tl)
-DEF_HELPER_3(sraw, tl, env, tl, tl)
+DEF_HELPER_3(SRAW, tl, env, tl, tl)
 DEF_HELPER_FLAGS_2(CFUGED, TCG_CALL_NO_RWG_SE, i64, i64, i64)
 DEF_HELPER_FLAGS_2(PDEPD, TCG_CALL_NO_RWG_SE, i64, i64, i64)
 DEF_HELPER_FLAGS_2(PEXTD, TCG_CALL_NO_RWG_SE, i64, i64, i64)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 189f9c6fe7..ef0fe12959 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -509,6 +509,8 @@ HASHCHKP        011111 ..... ..... ..... 1010110010 .   @X_DW
 
 SLW             011111 ..... ..... ..... 0000011000 .   @X_rc
 SRW             011111 ..... ..... ..... 1000011000 .   @X_rc
+SRAW            011111 ..... ..... ..... 1100011000 .   @X_rc
+SRAWI           011111 ..... ..... ..... 1100111000 .   @X_rc
 
 ## BCD Assist
 
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index dc55ccadf7..b161f930ec 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -235,7 +235,7 @@ target_ulong helper_CMPB(target_ulong rs, target_ulong rb)
 }
 
 /* shift right arithmetic helper */
-target_ulong helper_sraw(CPUPPCState *env, target_ulong value,
+target_ulong helper_SRAW(CPUPPCState *env, target_ulong value,
                          target_ulong shift)
 {
     int32_t ret;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 3d26e1144e..53acd54ad4 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -2316,46 +2316,6 @@ GEN_PPC64_R4(rldimi, 0x1E, 0x06);
 /***                             Integer shift                             ***/
 
 
-/* sraw & sraw. */
-static void gen_sraw(DisasContext *ctx)
-{
-    gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], tcg_env,
-                    cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
-    if (unlikely(Rc(ctx->opcode) != 0)) {
-        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
-    }
-}
-
-/* srawi & srawi. */
-static void gen_srawi(DisasContext *ctx)
-{
-    int sh = SH(ctx->opcode);
-    TCGv dst = cpu_gpr[rA(ctx->opcode)];
-    TCGv src = cpu_gpr[rS(ctx->opcode)];
-    if (sh == 0) {
-        tcg_gen_ext32s_tl(dst, src);
-        tcg_gen_movi_tl(cpu_ca, 0);
-        if (is_isa300(ctx)) {
-            tcg_gen_movi_tl(cpu_ca32, 0);
-        }
-    } else {
-        TCGv t0;
-        tcg_gen_ext32s_tl(dst, src);
-        tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
-        t0 = tcg_temp_new();
-        tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
-        tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
-        tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
-        if (is_isa300(ctx)) {
-            tcg_gen_mov_tl(cpu_ca32, cpu_ca);
-        }
-        tcg_gen_sari_tl(dst, dst, sh);
-    }
-    if (unlikely(Rc(ctx->opcode) != 0)) {
-        gen_set_Rc0(ctx, dst);
-    }
-}
-
 #if defined(TARGET_PPC64)
 /* sld & sld. */
 static void gen_sld(DisasContext *ctx)
@@ -5717,8 +5677,6 @@ GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300),
 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
-GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
-GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
 #if defined(TARGET_PPC64)
 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 9d04b96316..234404e459 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -1454,3 +1454,44 @@ static bool trans_SRW(DisasContext *ctx, arg_SRW *a)
     }
     return true;
 }
+
+/* sraw & sraw. */
+static bool trans_SRAW(DisasContext *ctx, arg_SRAW *a)
+{
+    gen_helper_SRAW(cpu_gpr[a->ra], tcg_env,
+                    cpu_gpr[a->rt], cpu_gpr[a->rb]);
+    if (unlikely(a->rc)) {
+        gen_set_Rc0(ctx, cpu_gpr[a->ra]);
+    }
+    return true;
+}
+
+/* srawi & srawi. */
+static bool trans_SRAWI(DisasContext *ctx, arg_SRAWI *a)
+{
+    TCGv dst = cpu_gpr[a->ra];
+    TCGv src = cpu_gpr[a->rt];
+    if (a->rb == 0) {
+        tcg_gen_ext32s_tl(dst, src);
+        tcg_gen_movi_tl(cpu_ca, 0);
+        if (is_isa300(ctx)) {
+            tcg_gen_movi_tl(cpu_ca32, 0);
+        }
+    } else {
+        TCGv t0;
+        tcg_gen_ext32s_tl(dst, src);
+        tcg_gen_andi_tl(cpu_ca, dst, (1ULL << a->rb) - 1);
+        t0 = tcg_temp_new();
+        tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
+        tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
+        tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
+        if (is_isa300(ctx)) {
+            tcg_gen_mov_tl(cpu_ca32, cpu_ca);
+        }
+        tcg_gen_sari_tl(dst, dst, a->rb);
+    }
+    if (unlikely(a->rc)) {
+        gen_set_Rc0(ctx, dst);
+    }
+    return true;
+}
-- 
2.55.0



  parent reply	other threads:[~2026-08-27 13:32 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-27 13:29 [PATCH v3 00/37] target/ppc: PPC TCG Improvements (decodetree migrations + ISA 2.07 flag updates) Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 01/37] target/ppc: Migrate extswsli to decodetree Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 02/37] target/ppc: Migrate atomic loads " Chinmay Rath
2026-08-27 14:29   ` Amit Machhiwal
2026-08-27 13:29 ` [PATCH v3 03/37] target/ppc: Convert cache instructions " Chinmay Rath
2026-08-27 14:56   ` Amit Machhiwal
2026-08-27 13:29 ` [PATCH v3 04/37] target/ppc: Move vector merge " Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 05/37] target/ppc: Move vector pack " Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 06/37] target/ppc: Move st{b, h, w, d, q}cx " Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 07/37] target/ppc: convert slw, srw instruction via decode spec Chinmay Rath
2026-08-27 13:29 ` Chinmay Rath [this message]
2026-08-27 13:29 ` [PATCH v3 09/37] target/ppc: Convert mcrf to decode tree Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 10/37] target/ppc: Move fixed-point Shift insns to decodetree Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 11/37] target/ppc: Move fixed-point byte-reversal store " Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 12/37] target/ppc: Move GPR atomic load/store instructions " Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 13/37] target/ppc: Move isync instruction " Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 14/37] target/ppc: Convert b{a, l, la} to decode tree Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 15/37] target/ppc: move various conditional branch insns to decodetree Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 16/37] target/ppc: Fix TRANS* macro variadic arguments handling Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 17/37] target/ppc: Move wait instruction to decodetree Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 18/37] target/ppc: Move sleep & friends " Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 19/37] target/ppc: Refactor sleep and its variants to use a common helper Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 20/37] target/ppc: Move Condition Register access instructions to decodetree Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 21/37] target/ppc: Move Condition Register logical " Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 22/37] target/ppc: make do_ea_calc_ra available for 32 bit builds Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 23/37] target/ppc: Move Fixed-Point Load/Store String instructions to decodetree Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 24/37] target/ppc: Move VMX integer arithmetic and BCD " Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 25/37] target/ppc: Move rlwimi, rlwinm " Chinmay Rath
2026-08-27 15:37   ` Amit Machhiwal
2026-08-27 13:29 ` [PATCH v3 26/37] target/ppc: Move lmw, stmw " Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 27/37] target/ppc: Move mfmsr, mtmsr[d] " Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 28/37] target/ppc: Move byte-reverse " Chinmay Rath
2026-08-27 15:40   ` Amit Machhiwal
2026-08-27 13:29 ` [PATCH v3 29/37] target/ppc: Move system call and rfi " Chinmay Rath
2026-08-27 16:00   ` Amit Machhiwal
2026-08-28  4:30     ` Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 30/37] target/ppc: Replace PPC2_VSX207 flag with PPC2_ISA207 Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 31/37] target/ppc: Use PPC2_ISA207 instead of PPC2_BCTAR_ISA207 Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 32/37] target/ppc: Use PPC2_ISA207 instead of PPC2_LSQ_ISA207 Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 33/37] target/ppc: Use PPC2_ISA207 instead of PPC2_ALTIVEC_207 Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 34/37] target/ppc: Use PPC2_ISA207 instead of PPC2_ISA207S Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 35/37] target/ppc: Reorder PPC2 flags Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 36/37] target/ppc: Add ICBT support for ISA version 2.07 Chinmay Rath
2026-08-27 13:29 ` [PATCH v3 37/37] target/ppc: Add self as maintainer for PowerPC TCG CPUs Chinmay Rath
2026-08-27 13:37 ` [PATCH v3 00/37] target/ppc: PPC TCG Improvements (decodetree migrations + ISA 2.07 flag updates) Chinmay Rath
2026-08-28  5:23 ` Aniket Sahu

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