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From: Chen Pei <cp0613@linux.alibaba.com>
To: Junjie Cao <junjie.cao@intel.com>
Cc: palmer@dabbelt.com, alistair.francis@wdc.com, mst@redhat.com,
	imammedo@redhat.com, sunilvl@ventanamicro.com,
	sunilvl@oss.qualcomm.com, jic23@kernel.org, pbonzini@redhat.com,
	liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com,
	zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com,
	anisinha@redhat.com, dave.jiang@intel.com,
	alison.schofield@intel.com, guoren@kernel.org,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	linux-cxl@vger.kernel.org
Subject: Re: [PATCH 4/4] tests/qtest: Add RISC-V ACPI bios tables test for CXL
Date: Thu, 27 Aug 2026 20:24:39 +0800	[thread overview]
Message-ID: <20260827201758.300003-1-cp0613@linux.alibaba.com> (raw)
In-Reply-To: <20260826133812.355470-1-junjie.cao@intel.com>

Hi Junjie,

Thanks for the reminder.

I will first work on 3/4 along the extra-pci-roots line (and the
end-to-end verification on a booting CXL guest), then regenerate the
golden tables and respin this patch accordingly.

Thanks,
Pei

  reply	other threads:[~2026-08-27 12:24 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-21  8:19 [PATCH 0/4] hw/riscv/virt: Add CXL support to the RISC-V virt machine Chen Pei
2026-08-21  8:19 ` [PATCH 1/4] " Chen Pei
2026-08-21  8:19 ` [PATCH 2/4] hw/riscv/virt-acpi-build: Add _DEP to ACPI0017 for CXL host bridge dependency Chen Pei
2026-08-21  8:19 ` [PATCH 3/4] hw/riscv/virt: Provide a 32-bit MMIO window for CXL host bridges Chen Pei
2026-08-26 13:37   ` Junjie Cao
2026-08-27 12:17     ` Chen Pei
2026-08-28 10:05       ` Chen Pei
2026-08-21  8:19 ` [PATCH 4/4] tests/qtest: Add RISC-V ACPI bios tables test for CXL Chen Pei
2026-08-26 13:38   ` Junjie Cao
2026-08-27 12:24     ` Chen Pei [this message]
2026-08-21  8:43 ` [PATCH 0/4] hw/riscv/virt: Add CXL support to the RISC-V virt machine Chen Pei
2026-08-26 13:37 ` Junjie Cao

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