[PATCH] KVM: x86/pmu: Add mediated vPMU PerfMon v5 support

[Zide Chen <zide.chen@intel.com>]

KVM currently caps the guest Intel architectural PMU version at 2. This
series bumps it to PerfMon v5 and adds support for some features that
are introduced in PerfMon v3-v5.

- CPUID.0AH:ECX fixed-counter bitmap (v5): supersedes EDX[4:0] and
  lets KVM/guests represent non-contiguous fixed counters (e.g. some
  E-core server parts skip fixed counter 3).
- Add support for IA32_PERF_GLOBAL_STATUS_SET (v4): lets software set
  individual bits in the global status MSR.
- Add support for IA32_PERF_GLOBAL_INUSE (v4): reports which counters
  and PMI are currently claimed.
- Implement ANYTHREAD_DEPRECATION capability.

Intel PerfMon v5 doesn't support non-contiguous GP counters; however,
this series lays the groundwork for GP counter bitmap support anyway,
for consistency with the host perf API interface, and prepares for
Perfmon Masking support.

Freeze_PerfMon_On_PMI virtualization is not implemented because, as
commit 3daa96d67274 ("perf/intel: Remove Perfmon-v4 counter_freezing
support") states, the Freeze-on-PMI mechanism violates the perf counter
independence.

Streamlined Freeze_LBRs_On_PMI is not implemented because LBR is not
yet supported on mediated vPMU.

Tested on SPR and CWF:

- Ran "perf test" on both L0 and L1; no issues attributable to this
  series have been observed so far.

- Ran KVM selftests on both L0 and L1.

- Passed AnyThread tests on both fixed and gp counters:
  $ perf stat -e r20003c,r2000c4,r2000c0 -- sleep 1

- Tested various guest fixed-counter configurations:
      CPUID.0AH:ECX = 0x7   CPUID.0AH:EDX[4:0]=3
      CPUID.0AH:ECX = 0x2   CPUID.0AH:EDX[4:0]=0
      CPUID.0AH:ECX = 0x6   CPUID.0AH:EDX[4:0]=0
      CPUID.0AH:ECX = 0x5   CPUID.0AH:EDX[4:0]=1
      CPUID.0AH:ECX = 0x0   CPUID.0AH:EDX[4:0]=0

  Verified that the guest PMU reflected the configured fixed-counter
  and that the following command used fixed or general-purpose counters
  as expected:

  $ perf stat -e instructions,cpu-cycles,ref-cycles -- sleep 1

- Manually tested IA32_PERF_GLOBAL_INUSE.

- Ran some additional perf tests on both L0 and L1.

- Sanity testing on nested VMs.

Patch series summary:
patch 1-4: Code cleanup and a fix.
patch 5-10: Implement PMC bitmap support.
patch 11-14: Implement PerfMon v3-v5 new features.
patch 15: Advertise PerfMon version up to v5.
patch 16: Fix pmu_counters_test selftests fixed counter test case.

Rebased to kvm-x86/next: 76671054f9a1

v2 changes:
- Dropped v1 11/15: KVM: x86/pmu: Emulate streamlined Freeze-LBR-on-PMI
- New patch 4/15 to gate BUFFER_OVF reserved bit on guest DS feature.
- Some renames:
  - all_valid_pmc_mask to pmc_exists;
  - add _is to kvm_{gp,fixed}_pmc_supported();
  - split kvm_for_each_set_pmc_idx() to kvm_for_each_{gp,fixed}_counter().
- Add missing AnyThr handling in IA32_FIXED_CTR_CTRL and advertise
  anythread_deprecated only if kvm_pmu_cap.version >= 5.
- Cap vPMU v3/v4 to v2, as AnyThread cannot be safely virtualized.
- Miscellaneous updates to changelogs and some minor fixes.

Dapeng Mi (6):
  KVM: x86/pmu: Drop nr_arch_{gp,fixed}_counters from kvm_pmu
  perf/x86: Plumb counter bitmap from x86_pmu to x86_pmu_cap
  KVM: x86/pmu: Switch to bitmask-based KVM PMU capabilities
  perf/x86: Remove num_counters_{gp,fixed} from x86_pmu_capability
  KVM: x86/pmu: Advertise PerfMon version 5 on Intel hosts
  KVM: selftests: Support fixed counters bitmap in pmu_counters_test

Zide Chen (10):
  KVM: x86/pmu: Remove redundant Perf Global Status MSR bit definitions
  KVM: x86/pmu: Rename all_valid_pmc_idx to pmc_exists
  KVM: x86/pmu: Rename reserved_bits to eventsel_rsvd in kvm_pmu
  KVM: x86/pmu: Gate BUFFER_OVF reserved bit on guest DS
  KVM: x86/pmu: Add PMC bitmap accessor helpers
  KVM: x86/pmu: Expose kvm_host_pmu to vendor modules
  KVM: x86/pmu: Emulate the GLOBAL_STATUS_SET and GLOBAL_INUSE MSRs
  KVM: x86/pmu: Populate CPUID.0AH:ECX fixed-counter bitmap
  KVM: x86/pmu: Factor out fixed counter control bit calculation
  KVM: x86/pmu: Ignore AnyThread bit if CPUID.0AH:EDX[15] is set

 arch/x86/events/core.c                        |   8 +-
 arch/x86/include/asm/kvm_host.h               |   9 +-
 arch/x86/include/asm/msr-index.h              |  12 +-
 arch/x86/include/asm/perf_event.h             |  10 +-
 arch/x86/kvm/cpuid.c                          |  21 ++-
 arch/x86/kvm/msrs.c                           |  12 +-
 arch/x86/kvm/pmu.c                            |  85 ++++++---
 arch/x86/kvm/pmu.h                            |  54 +++++-
 arch/x86/kvm/svm/pmu.c                        |  37 ++--
 arch/x86/kvm/svm/svm.c                        |  17 +-
 arch/x86/kvm/vmx/nested.c                     |   8 +-
 arch/x86/kvm/vmx/pmu_intel.c                  | 167 +++++++++++++-----
 arch/x86/kvm/vmx/vmx.c                        |  19 +-
 .../selftests/kvm/include/x86/processor.h     |   6 +-
 .../selftests/kvm/x86/pmu_counters_test.c     |  26 ++-
 15 files changed, 349 insertions(+), 142 deletions(-)

-- 
2.55.0