From: Junjie Cao <junjie.cao@intel.com>
To: Shrihari E S <shrihari.s@samsung.com>
Cc: jic23@kernel.org, fan.ni@samsung.com, mst@redhat.com,
marcel.apfelbaum@gmail.com, dave@stgolabs.net,
arun.george@samsung.com, dongjoo.seo1@samsung.com,
s.neeraj@samsung.com, vikash.k5@samsung.com, cpgs@samsung.com,
gost.dev@samsung.com, linux-cxl@vger.kernel.org,
linux-pci@vger.kernel.org, qemu-devel@nongnu.org
Subject: Re: [RFC V2 10/10] cxl: Add documentation for CXL UIO support.
Date: Sun, 30 Aug 2026 15:23:30 +0800 [thread overview]
Message-ID: <20260830072330.399591-1-junjie.cao@intel.com> (raw)
In-Reply-To: <124323713.61787732282965.JavaMail.epsvc@epcpadp2new>
Hi Shrihari,
On Wed, 26 Aug 2026 11:04:10 +0530, Shrihari E S wrote:
> +3. **Device 3 Extended Capability**: Enabled via ``x-uio`` on CXL type3
x-uio on its own doesn't get you Dev3: ct3_realize() adds it only when
x-svc and x-256b-flit are set as well. It does set the HDM UIO bit
with neither of them, which is the asymmetry I raised on 9/10.
> +An example of 3 type3 devices with volatile memory below a switch. All the devices
> +and ports support Unordered IO (UIO) feature which requires Streamlined Virtual Channel
The topology below this doesn't advertise UIO through the switch. I
ran it -- joined onto single lines, the indented continuations don't
survive a paste -- and the upstream port reads 0x00000382 in its HDM
Decoder Capability register, UIO clear, against 0x00042312 on cxl-rp.
That's the gate in 7/10; worth re-running the example once it's
settled.
Many thanks,
Junjie
next prev parent reply other threads:[~2026-08-30 7:24 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20260826052014epcas5p11846c6a40fcec4ec4ba441ceb26e5dcc@epcas5p1.samsung.com>
[not found] ` <20260826053410.1322176-1-shrihari.s@samsung.com>
2026-08-26 5:34 ` [RFC V2 01/10] hw/pci: Refactor flitmode from PCIESlot to PCIEPort Shrihari E S
2026-08-26 5:34 ` [RFC V2 02/10] hw/pci: Move 'x-256b-flit' property from cxl_root_port to pcie_root_port Shrihari E S
2026-08-30 7:20 ` Junjie Cao
2026-08-26 5:34 ` [RFC V2 03/10] hw/pci: Add SVC capability and UIO properties to PCIe ports Shrihari E S
2026-08-30 7:20 ` Junjie Cao
2026-08-26 5:34 ` [RFC V2 04/10] hw/cxl: Add Streamlined Virtual Channel (SVC) property to CXL ports Shrihari E S
2026-08-26 5:34 ` [RFC V2 05/10] hw/cxl: Wire UIO capability into HDM decoder and DVSEC registers Shrihari E S
2026-08-30 7:21 ` Junjie Cao
2026-09-10 9:37 ` Shrihari E S
2026-08-26 5:34 ` [RFC V2 06/10] hw/pci: Add PCIe Streamlined Virtual Channel (SVC) capability Shrihari E S
2026-08-30 7:21 ` Junjie Cao
2026-09-10 8:40 ` Shrihari E S
2026-08-26 5:34 ` [RFC V2 07/10] hw/pci: hw/cxl: Wire SVC initialization into port realize functions Shrihari E S
2026-08-30 7:22 ` Junjie Cao
2026-08-26 5:34 ` [RFC V2 08/10] hw/pci: Add PCIe Device3 capability support Shrihari E S
2026-08-30 7:22 ` Junjie Cao
2026-08-26 5:34 ` [RFC V2 09/10] hw/cxl: Wire SVC and Dev3 capability to CXL Type 3 device Shrihari E S
2026-08-30 7:23 ` Junjie Cao
2026-08-26 5:34 ` [RFC V2 10/10] cxl: Add documentation for CXL UIO support Shrihari E S
2026-08-30 7:23 ` Junjie Cao [this message]
[not found] <CGME20260826051958epcas5p3db6cf2ef9115168c5d8dcec7bdb9b8c3@epcas5p3.samsung.com>
2026-08-26 5:34 ` [RFC V2 0/9] hw/pci: hw/cxl: Add UIO support in CXL and PCIe stack Shrihari E S
2026-08-30 7:19 ` Junjie Cao
2026-09-10 8:22 ` Shrihari E S
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