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From: Shrihari E S <shrihari.s@samsung.com>
To: Junjie Cao <junjie.cao@intel.com>
Cc: jic23@kernel.org, mst@redhat.com, marcel.apfelbaum@gmail.com,
	dave@stgolabs.net, arun.george@samsung.com,
	dongjoo.seo1@samsung.com, s.neeraj@samsung.com,
	vikash.k5@samsung.com, cpgs@samsung.com, gost.dev@samsung.com,
	linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
	qemu-devel@nongnu.org, shrihari.s@samsung.com
Subject: Re: [RFC V2 06/10] hw/pci: Add PCIe Streamlined Virtual Channel (SVC) capability.
Date: Thu, 10 Sep 2026 14:10:52 +0530	[thread overview]
Message-ID: <973576304.21789064282642.JavaMail.epsvc@epcpadp2new> (raw)
In-Reply-To: <20260830072144.399508-1-junjie.cao@intel.com>

[-- Attachment #1: Type: text/plain, Size: 602 bytes --]

On 30/08/26 03:21PM, Junjie Cao wrote:
>On the register defines: v1 ended with routing these through
>pci_regs.h plus a note on when the kernel header picks them up; they
>went into QEMU's pcie_regs.h instead.  Still the plan for a later
>spin, or intentional?
>
>Many thanks,
>Junjie

Hi Junjie,

The register definitions are intentionally placed in QEMU's
include/hw/pci/pci_regs.h for now. Once The corresponding macros are
merged into Linux Kernel's include/uapi/linux/pci_regs.h, will sync
them through include/standard headers/linux/pci_regs.h in a follow-up
patch.

Thanks and regards,
Shrihari

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  reply	other threads:[~2026-09-10 18:18 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20260826052014epcas5p11846c6a40fcec4ec4ba441ceb26e5dcc@epcas5p1.samsung.com>
     [not found] ` <20260826053410.1322176-1-shrihari.s@samsung.com>
2026-08-26  5:34   ` [RFC V2 01/10] hw/pci: Refactor flitmode from PCIESlot to PCIEPort Shrihari E S
2026-08-26  5:34   ` [RFC V2 02/10] hw/pci: Move 'x-256b-flit' property from cxl_root_port to pcie_root_port Shrihari E S
2026-08-30  7:20     ` Junjie Cao
2026-08-26  5:34   ` [RFC V2 03/10] hw/pci: Add SVC capability and UIO properties to PCIe ports Shrihari E S
2026-08-30  7:20     ` Junjie Cao
2026-08-26  5:34   ` [RFC V2 04/10] hw/cxl: Add Streamlined Virtual Channel (SVC) property to CXL ports Shrihari E S
2026-08-26  5:34   ` [RFC V2 05/10] hw/cxl: Wire UIO capability into HDM decoder and DVSEC registers Shrihari E S
2026-08-30  7:21     ` Junjie Cao
2026-09-10  9:37       ` Shrihari E S
2026-08-26  5:34   ` [RFC V2 06/10] hw/pci: Add PCIe Streamlined Virtual Channel (SVC) capability Shrihari E S
2026-08-30  7:21     ` Junjie Cao
2026-09-10  8:40       ` Shrihari E S [this message]
2026-08-26  5:34   ` [RFC V2 07/10] hw/pci: hw/cxl: Wire SVC initialization into port realize functions Shrihari E S
2026-08-30  7:22     ` Junjie Cao
2026-08-26  5:34   ` [RFC V2 08/10] hw/pci: Add PCIe Device3 capability support Shrihari E S
2026-08-30  7:22     ` Junjie Cao
2026-08-26  5:34   ` [RFC V2 09/10] hw/cxl: Wire SVC and Dev3 capability to CXL Type 3 device Shrihari E S
2026-08-30  7:23     ` Junjie Cao
2026-08-26  5:34   ` [RFC V2 10/10] cxl: Add documentation for CXL UIO support Shrihari E S
2026-08-30  7:23     ` Junjie Cao
     [not found] <CGME20260826051958epcas5p3db6cf2ef9115168c5d8dcec7bdb9b8c3@epcas5p3.samsung.com>
2026-08-26  5:34 ` [RFC V2 0/9] hw/pci: hw/cxl: Add UIO support in CXL and PCIe stack Shrihari E S
2026-08-30  7:19   ` Junjie Cao
2026-09-10  8:22     ` Shrihari E S

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