Re: [PATCH v2 1/4] dt-bindings: phy: qcom: add Nord QMP PCIe PHY binding

From: Krzysztof Kozlowski <krzk@kernel.org>
To: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Cc: "Vinod Koul" <vkoul@kernel.org>,
	"Neil Armstrong" <neil.armstrong@linaro.org>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Bjorn Andersson" <andersson@kernel.org>,
	"Maxime Chevallier" <maxime.chevallier@bootlin.com>,
	"Philipp Zabel" <p.zabel@pengutronix.de>,
	linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-pci@vger.kernel.org
Subject: Re: [PATCH v2 1/4] dt-bindings: phy: qcom: add Nord QMP PCIe PHY binding
Date: Mon, 31 Aug 2026 10:43:03 +0200	[thread overview]
Message-ID: <20260831-bizarre-invincible-badger-e4a7cc@quoll> (raw)
In-Reply-To: <20260828-nord-v2-1-18bf59d19d6f@oss.qualcomm.com>

On Fri, Aug 28, 2026 at 02:13:35PM +0530, Krishna Chaitanya Chundru wrote:
> diff --git a/Documentation/devicetree/bindings/phy/qcom,nord-qmp-gen5x16-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,nord-qmp-gen5x16-pcie-phy.yaml
> new file mode 100644
> index 000000000000..37198f82c611
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,nord-qmp-gen5x16-pcie-phy.yaml
> @@ -0,0 +1,276 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/qcom,nord-qmp-gen5x16-pcie-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Nord QMP Bifurcated PCIe PHY
> +
> +maintainers:
> +  - Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> +
> +description: |
> +  The Qualcomm Nord PCIe PHY is a Gen5-capable QMP PCIe PHY composed
> +  of four PHY ports (A/B/C/D). The ports can be combined to support
> +  multiple lane topologies, including x16, x8+x8, x8+x4+x4 and
> +  x8+x4+x2+x2 configurations.
> +
> +  The selected topology is determined by the PCIe link configuration mode
> +  programmed in TCSR registers. Depending on the selected mode, PHY ports
> +  may operate independently or be grouped together to form wider PCIe links.
> +
> +  Each port provides dedicated register space, clocks, resets and power
> +  resources required for PHY operation.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - qcom,nord-qmp-gen5x16-pcie-phy
> +
> +  reg:
> +    minItems: 4

Drop minItems, not needed.

> +    maxItems: 4
> +
> +  reg-names:
> +    items:
> +      - const: port_a
> +      - const: port_b
> +      - const: port_c
> +      - const: port_d
> +
> +  clocks:
> +    minItems: 17

Similarly, you can look at other examples.

> +    maxItems: 17
> +
> +  clock-names:
> +    items:
> +      - const: aux_a
> +      - const: cfg_ahb_a
> +      - const: rchng_a
> +      - const: pipe_a
> +      - const: aux_b
> +      - const: cfg_ahb_b
> +      - const: rchng_b
> +      - const: pipe_b
> +      - const: aux_c
> +      - const: cfg_ahb_c
> +      - const: rchng_c
> +      - const: pipe_c
> +      - const: aux_d
> +      - const: cfg_ahb_d
> +      - const: rchng_d
> +      - const: pipe_d
> +      - const: ref

To match other variants, ref should be the third clock.

> +
> +  power-domains:
> +    minItems: 4

Dop

> +    maxItems: 4
> +
> +  power-domain-names:
> +    items:
> +      - const: port_a
> +      - const: port_b
> +      - const: port_c
> +      - const: port_d
> +
> +  resets:
> +    minItems: 8

Drop

> +    maxItems: 8

Best regards,
Krzysztof