[PATCH 7/7] drm/amd/pm: stage od reset for smu vega20

[Kevin Wang <kevin.wang@amd.com>]

Vega20 handles PP_OD_RESTORE_DEFAULT_TABLE by reading the current
OverDrive table from the SMU. This discards uncommitted driver-side
edits, but does not restore the boot OD settings.

Rebuild the pp_od_clk_voltage-editable table fields from the OD8 defaults
saved during initialization. Leave the rebuilt table in the driver cache
until PP_OD_COMMIT_DPM_TABLE uploads it. Preserve a pending GFXCLK/UCLK
DPM-table refresh whenever reset stages different limits, so c keeps the
driver cache synchronized with PMFW.

Signed-off-by: Kevin Wang <kevin.wang@amd.com>
---
 .../drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c | 75 ++++++++++++++++---
 1 file changed, 66 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
index e9c194056e32..aee9a26b1809 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
@@ -2948,6 +2948,71 @@ static int vega20_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
 	return 0;
 }
 
+static void vega20_od8_restore_default_settings(struct vega20_hwmgr *data)
+{
+	struct vega20_od8_single_setting *od8_settings =
+		data->od8_settings.od8_settings_array;
+	OverDriveTable_t *od_table = &data->smc_state_table.overdrive_table;
+
+	if (data->od8_settings.overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
+		if (od_table->GfxclkFmin !=
+			    od8_settings[OD8_SETTING_GFXCLK_FMIN].default_value ||
+		    od_table->GfxclkFmax !=
+			    od8_settings[OD8_SETTING_GFXCLK_FMAX].default_value)
+			data->gfxclk_overdrive = true;
+
+		od_table->GfxclkFmin =
+			od8_settings[OD8_SETTING_GFXCLK_FMIN].default_value;
+		od_table->GfxclkFmax =
+			od8_settings[OD8_SETTING_GFXCLK_FMAX].default_value;
+		od8_settings[OD8_SETTING_GFXCLK_FMIN].current_value =
+			od8_settings[OD8_SETTING_GFXCLK_FMIN].default_value;
+		od8_settings[OD8_SETTING_GFXCLK_FMAX].current_value =
+			od8_settings[OD8_SETTING_GFXCLK_FMAX].default_value;
+	}
+
+	if (data->od8_settings.overdrive8_capabilities & OD8_GFXCLK_CURVE) {
+		od_table->GfxclkFreq1 =
+			od8_settings[OD8_SETTING_GFXCLK_FREQ1].default_value;
+		od_table->GfxclkVolt1 =
+			od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].default_value *
+			VOLTAGE_SCALE;
+		od_table->GfxclkFreq2 =
+			od8_settings[OD8_SETTING_GFXCLK_FREQ2].default_value;
+		od_table->GfxclkVolt2 =
+			od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].default_value *
+			VOLTAGE_SCALE;
+		od_table->GfxclkFreq3 =
+			od8_settings[OD8_SETTING_GFXCLK_FREQ3].default_value;
+		od_table->GfxclkVolt3 =
+			od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].default_value *
+			VOLTAGE_SCALE;
+		od8_settings[OD8_SETTING_GFXCLK_FREQ1].current_value =
+			od8_settings[OD8_SETTING_GFXCLK_FREQ1].default_value;
+		od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].current_value =
+			od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].default_value;
+		od8_settings[OD8_SETTING_GFXCLK_FREQ2].current_value =
+			od8_settings[OD8_SETTING_GFXCLK_FREQ2].default_value;
+		od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].current_value =
+			od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].default_value;
+		od8_settings[OD8_SETTING_GFXCLK_FREQ3].current_value =
+			od8_settings[OD8_SETTING_GFXCLK_FREQ3].default_value;
+		od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].current_value =
+			od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].default_value;
+	}
+
+	if (data->od8_settings.overdrive8_capabilities & OD8_UCLK_MAX) {
+		if (od_table->UclkFmax !=
+		    od8_settings[OD8_SETTING_UCLK_FMAX].default_value)
+			data->memclk_overdrive = true;
+
+		od_table->UclkFmax =
+			od8_settings[OD8_SETTING_UCLK_FMAX].default_value;
+		od8_settings[OD8_SETTING_UCLK_FMAX].current_value =
+			od8_settings[OD8_SETTING_UCLK_FMAX].default_value;
+	}
+}
+
 static int vega20_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
 					enum PP_OD_DPM_TABLE_COMMAND type,
 					long *input, uint32_t size)
@@ -3117,15 +3182,7 @@ static int vega20_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
 		break;
 
 	case PP_OD_RESTORE_DEFAULT_TABLE:
-		data->gfxclk_overdrive = false;
-		data->memclk_overdrive = false;
-
-		ret = smum_smc_table_manager(hwmgr,
-					     (uint8_t *)od_table,
-					     TABLE_OVERDRIVE, true);
-		PP_ASSERT_WITH_CODE(!ret,
-				"Failed to export overdrive table!",
-				return ret);
+		vega20_od8_restore_default_settings(data);
 		break;
 
 	case PP_OD_COMMIT_DPM_TABLE:
-- 
2.55.0