Re: [PATCH v16 20/22] media: i2c: maxim-serdes: add MAX96724 driver

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Incorrect clock polarity configuration for 4-lane mode on PHY 2.
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commit feec3c7ecf801109d27fdda12bede738f83b8546
Author: Cosmin Tanislav <demonsingur@gmail.com>

media: i2c: maxim-serdes: add MAX96724 driver

This commit adds support for the Maxim MAX96724 Quad Deserializer and
integrates it with the common deserializer framework.

> diff --git a/drivers/media/i2c/maxim-serdes/max96724.c b/drivers/media/i2c/maxim-serdes/max96724.c
> new file mode 100644
> index 0000000000000..458e78f285111
> --- /dev/null
> +++ b/drivers/media/i2c/maxim-serdes/max96724.c
[ ... ]
> +static int max96724_init_phy(struct max_des *des, struct max_des_phy *phy)
> +{
[ ... ]
> +	if (num_hw_data_lanes == 4) {
> +		ret = regmap_update_bits(priv->regmap, MAX96724_MIPI_PHY5(index),
> +					 MAX96724_MIPI_PHY5_PHY_POL_MAP_4_0_1 |
> +					 MAX96724_MIPI_PHY5_PHY_POL_MAP_4_2_3,
> +					 FIELD_PREP(MAX96724_MIPI_PHY5_PHY_POL_MAP_4_0_1,
> +						    val) |
> +					 FIELD_PREP(MAX96724_MIPI_PHY5_PHY_POL_MAP_4_2_3,
> +						    val >> 2));
> +		if (ret)
> +			return ret;
> +
> +		ret = regmap_assign_bits(priv->regmap, MAX96724_MIPI_PHY5(index),
> +					 MAX96724_MIPI_PHY5_PHY_POL_MAP_4_CLK,
                                         ^^^^

[Severity: High]
Does this hardcoded assignment to MAX96724_MIPI_PHY5_PHY_POL_MAP_4_CLK cause
an issue for the second port in a 4-lane configuration?

The macro MAX96724_MIPI_PHY5_PHY_POL_MAP_4_CLK unconditionally evaluates to
BIT(5). While this is correct for PHY 1 (the master for the PHY 0+1 group),
it seems incorrect for PHY 2 (the master for the PHY 2+3 group). For PHY 2,
it looks like the correct clock polarity bit should be BIT(2) in register
0x8a6.

Writing to BIT(5) when configuring PHY 2 leaves its own clock polarity
unconfigured (falling back to default) and inadvertently overwrites PHY 3's
clock polarity instead. This could break MIPI D-PHY links on the second
4-lane port when configured via the device tree.

> +					 phy->mipi.lane_polarities[0]);
> +		if (ret)
> +			return ret;
> +	} else {
[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260831-gmsl2-3_serdes-v16-0-4fa6e08bb514@analog.com?part=20