Re: [PATCH RESEND] xor: add missing vzeroupper to AVX code

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Incomplete fix: Missing `vzeroupper` in parallel AVX2/AVX-512 RAID6 and crypto implementations causes severe AVX-to-SSE transition penalties.
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commit 0dc8e5aa3bec5867a6cc446b05765378e42b49c6
Author: Eric Biggers <ebiggers@kernel.org>

xor: add missing vzeroupper to AVX code

This commit adds a missing vzeroupper instruction to the AVX optimized XOR
code. This clears the upper bits of the YMM registers before returning,
preventing severe performance degradation when later SSE code is executed.

> diff --git a/lib/raid/xor/x86/xor-avx.c b/lib/raid/xor/x86/xor-avx.c
> index f7777d7aa269b..95b21e7225e8d 100644
> --- a/lib/raid/xor/x86/xor-avx.c
> +++ b/lib/raid/xor/x86/xor-avx.c
> @@ -147,6 +147,7 @@ static void xor_gen_avx(void *dest, void **srcs, unsigned int src_cnt,
>  {
>  	kernel_fpu_begin();
>  	xor_gen_avx_inner(dest, srcs, src_cnt, bytes);
> +	asm volatile("vzeroupper");
>  	kernel_fpu_end();

[Severity: High]
This is a pre-existing issue, but this fix appears incomplete. While this
solves the missing vzeroupper in xor_gen_avx(), are there other parallel
AVX2/AVX-512 RAID6 and crypto implementations that suffer from this same
AVX-to-SSE transition penalty?

For instance, raid6_avx21_gen_syndrome() in lib/raid/raid6/x86/avx2.c and
raid6_avx5121_gen_syndrome() in lib/raid/raid6/x86/avx512.c both heavily use
YMM/ZMM registers but call kernel_fpu_end() without clearing the upper
halves:

lib/raid/raid6/x86/avx2.c:raid6_avx21_gen_syndrome() {
	...
	asm volatile("sfence" : : : "memory");
	kernel_fpu_end();
}

Similarly, raid6_2data_recov_avx2() in lib/raid/raid6/x86/recov_avx2.c
returns without executing vzeroupper:

lib/raid/raid6/x86/recov_avx2.c:raid6_2data_recov_avx2() {
	...
	kernel_fpu_end();
}

Also outside the RAID subsystem, routines like __aria_aesni_avx2_crypt_32way()
in arch/x86/crypto/aria-aesni-avx2-asm_64.S seem to have the exact same
omission:

arch/x86/crypto/aria-aesni-avx2-asm_64.S:__aria_aesni_avx2_crypt_32way() {
	...
	FRAME_END
	RET;
}

Could these functions also leave the CPU in a dirty AVX state and cause
severe performance regressions for subsequent legacy SSE instructions?

>  }

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260831212248.213805-1-ebiggers@kernel.org?part=1