* [PATCH v5 0/6] ppc/spapr: Add RTAS error injection support for VFIO EEH
@ 2026-09-01 17:41 Narayana Murty N
2026-09-01 17:41 ` [PATCH v5 1/6] ppc/spapr: Add VFIO EEH error injection backend Narayana Murty N
` (5 more replies)
0 siblings, 6 replies; 7+ messages in thread
From: Narayana Murty N @ 2026-09-01 17:41 UTC (permalink / raw)
To: qemu-devel, qemu-ppc, mahesh, sbhat, anushree.mathur, clg,
sourabhjain, adityag, nikhilks
Cc: pierrick.bouvier, rathc, npiggin, harshpb, amachhiw, hbathini,
shivangu
This patch series implements comprehensive RTAS-based error injection
support for VFIO EEH (Enhanced Error Handling) on PowerPC sPAPR platforms.
The implementation enables guest-initiated PCI error injection for improved
testing and diagnostics of EEH recovery mechanisms.
Background
----------
EEH is a critical feature on PowerPC platforms that provides error detection,
isolation, and recovery for PCI devices. Testing EEH recovery paths requires
the ability to inject various types of errors into the system. While physical
hardware supports error injection through firmware interfaces, QEMU's VFIO
implementation previously lacked this capability.
This series bridges that gap by implementing the IBM RTAS error injection
interface, allowing guests to inject PCI errors through the same firmware
calls used on physical hardware. This enables comprehensive testing of device
drivers' EEH recovery code paths in virtualized environments.
Implementation Overview
-----------------------
The patch series introduces three new RTAS calls:
- ibm,open-errinjct: Opens an error injection session
- ibm,errinjct: Injects a specific error type
- ibm,close-errinjct: Closes the error injection session
The implementation supports multiple error types including:
- IOA bus errors (32-bit and 64-bit addressing)
For IOA bus-error types, QEMU uses the BUID from the RTAS parameter buffer to
select the target PHB. For address-scoped IOA injections, QEMU translates the
guest BAR address to the corresponding host resource address before invoking
the VFIO EEH backend.
RTAS IOA error types are converted to the EEH type values expected by
VFIO_EEH_PE_INJECT_ERR:
- RTAS_ERR_TYPE_IOA_BUS_ERROR -> EEH_ERR_TYPE_32
- RTAS_ERR_TYPE_IOA_BUS_ERROR_64 -> EEH_ERR_TYPE_64
Requests with addr=0 and mask=0 are treated as non-address-scoped IOA
injections and are forwarded without address translation.
Non-IOA RTAS error types are parsed and validated, but return
RTAS_OUT_NOT_SUPPORTED in this series because their RTAS work buffers do not
carry enough target information to safely select a VFIO PE.
Tested on pseries and PowerNV hosts with KVM guests using the powerpc-utils
errinjct tool, together with the corresponding host kernel EEH RTAS error
injection patches:
https://lore.kernel.org/all/20260831065441.48654-1-nnmlinux@linux.ibm.com/
Patch Organization
------------------
Patch 1: Adds the VFIO backend for error injection
Patch 2: Implements the ibm,errinjct RTAS call handler
Patch 3: Adds session management (open/close) RTAS calls
Patch 4: Advertises capabilities via device tree properties
Patch 5: Refactors EEH specific code/stubs to new files.
Patch 6: Updates MAINTAINERS file
Changelog:
v5:
- added the missing files on patch 0005.
- move the VFIO EEH stubs into a separate stub file.
- Keep spapr_pci_vfio.c as the Linux/non-VFIO fallback path
and build the real EEH implementation from spapr_eeh.c
when CONFIG_VFIO_PCI is enabled.
v4:
- Removed the first-PHB assumption in ibm,errinjct.
- Use BUID from the IOA RTAS parameter buffer to select the target PHB.
- Added guest BAR to host resource address translation for address-scoped
IOA injections.
- Skip address translation for addr=0 and mask=0 IOA requests.
- Convert RTAS IOA error types to VFIO EEH type values before issuing
VFIO_EEH_PE_INJECT_ERR.
- Keep spapr_phb_vfio_errinjct() signature unchanged.
- Validate non-IOA RTAS error types but return RTAS_OUT_NOT_SUPPORTED.
- Removed host /proc/device-tree/rtas/ibm,errinjct-tokens probing.
- Always build the guest-facing ibm,errinjct-tokens blob in QEMU.
- Fixed ibm,open-errinjct return-cell layout on error paths.
- Fixed ibm,close-errinjct token validation when no session is open.
- Initialized errinject_tokens to NULL.
- Removed stale CONFIG_DEVICES include after dropping the associated ifdefs
- Renamed the split EEH file to hw/ppc/spapr_eeh.c.
- Added Pierrick's Reviewed-by tag on the refactor patch.
- Added sPAPR VFIO EEH reviewer entry in MAINTAINERS.
v3:
- Fixed the build failure reported at https://github.com/p-b-o/qemu-ci/actions/runs/26094993976
- Also fixed a gitlab CI breakage in patch 2 (qemu_log_mask LOG_UNIMP)
v2: Addressed refactor suggestions from Cedric, Pierrick
v1: https://lore.kernel.org/all/20260512071112.9675-1-nnmlinux@linux.ibm.com/
Narayana Murty N (6):
ppc/spapr: Add VFIO EEH error injection backend
ppc/spapr: Add ibm,errinjct RTAS call handler
ppc/spapr: Add support for ibm, open-errinjct and ibm, close-errinjct
ppc/spapr: Advertise RTAS error injection call support via FDT
property
ppc/spapr: Split VFIO EEH support from general VFIO code
MAINTAINERS: Add self as sPAPR EEH reviewer under PPC RAS
include/hw/pci-host/spapr.h | 37 +--
include/hw/ppc/spapr.h | 69 ++++-
include/hw/ppc/spapr_vfio.h | 31 ++
hw/ppc/spapr.c | 61 ++++
hw/ppc/spapr_eeh.c | 571 +++++++++++++++++++++++++++++++++++
hw/ppc/spapr_pci.c | 193 ++++++++++++
hw/ppc/spapr_pci_vfio.c | 315 +------------------
stubs/spapr_phb_vfio-stubs.c | 62 ++++
MAINTAINERS | 2 +
hw/ppc/Kconfig | 2 +-
hw/ppc/meson.build | 1 +
stubs/meson.build | 1 +
12 files changed, 994 insertions(+), 351 deletions(-)
create mode 100644 include/hw/ppc/spapr_vfio.h
create mode 100644 hw/ppc/spapr_eeh.c
create mode 100644 stubs/spapr_phb_vfio-stubs.c
--
2.51.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v5 1/6] ppc/spapr: Add VFIO EEH error injection backend
2026-09-01 17:41 [PATCH v5 0/6] ppc/spapr: Add RTAS error injection support for VFIO EEH Narayana Murty N
@ 2026-09-01 17:41 ` Narayana Murty N
2026-09-01 17:41 ` [PATCH v5 2/6] ppc/spapr: Add ibm,errinjct RTAS call handler Narayana Murty N
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Narayana Murty N @ 2026-09-01 17:41 UTC (permalink / raw)
To: qemu-devel, qemu-ppc, mahesh, sbhat, anushree.mathur, clg,
sourabhjain, adityag, nikhilks
Cc: pierrick.bouvier, rathc, npiggin, harshpb, amachhiw, hbathini,
shivangu
Add spapr_phb_vfio_errinjct() to the VFIO EEH backend in
spapr_pci_vfio.c. The function maps guest RTAS IOA bus-error types to
the corresponding VFIO EEH ioctl error types:
RTAS_ERR_TYPE_IOA_BUS_ERROR -> EEH_ERR_TYPE_32
RTAS_ERR_TYPE_IOA_BUS_ERROR_64 -> EEH_ERR_TYPE_64
EEH_ERR_TYPE_32 / EEH_ERR_TYPE_64 are imported from the powerpc UAPI
EEH header where available; fallback numeric definitions are provided
to guard against older build environments.
The backend consumes type, func, addr, and mask from the caller. It
does not accept or interpret config_addr; PHB/PE selection is the
caller's responsibility via the sphb pointer.
Supporting type definitions are added to include/hw/ppc/spapr.h:
- EEH_ERR_FUNC_* and EEH_ERR_FUNC_MAX
- EEH_ERR_TYPE_32 / EEH_ERR_TYPE_64 (with #ifndef guards)
- enum rtas_err_type (RTAS ibm,errinjct error token values)
- RTAS_IBM_ERRINJCT token
The function prototype is added to include/hw/pci-host/spapr.h inside
the CONFIG_LINUX ifdef block alongside the other EEH hooks.
Signed-off-by: Narayana Murty N <nnmlinux@linux.ibm.com>
---
include/hw/pci-host/spapr.h | 8 ++++
include/hw/ppc/spapr.h | 60 ++++++++++++++++++++++++++++-
hw/ppc/spapr_pci_vfio.c | 75 +++++++++++++++++++++++++++++++++++++
3 files changed, 142 insertions(+), 1 deletion(-)
diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h
index 0db87f1281..24109409f4 100644
--- a/include/hw/pci-host/spapr.h
+++ b/include/hw/pci-host/spapr.h
@@ -125,6 +125,8 @@ int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, int *state);
int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option);
int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb);
void spapr_phb_vfio_reset(DeviceState *qdev);
+int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t type,
+ uint32_t func, uint64_t addr, uint64_t mask);
#else
static inline bool spapr_phb_eeh_available(SpaprPhbState *sphb)
{
@@ -151,6 +153,12 @@ static inline int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb)
static inline void spapr_phb_vfio_reset(DeviceState *qdev)
{
}
+static inline int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t type,
+ uint32_t func, uint64_t addr,
+ uint64_t mask)
+{
+ return RTAS_OUT_NOT_SUPPORTED;
+}
#endif
void spapr_phb_dma_reset(SpaprPhbState *sphb);
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 9acda15d4f..253dc0e862 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -682,6 +682,63 @@ void push_sregs_to_kvm_pr(SpaprMachineState *spapr);
#define RTAS_EEH_PE_UNAVAIL_INFO 1000
#define RTAS_EEH_PE_RECOVER_INFO 0
+/* EEH error injection types and functions */
+#define EEH_ERR_FUNC_MIN 0
+#define EEH_ERR_FUNC_LD_MEM_ADDR 0 /* Memory load */
+#define EEH_ERR_FUNC_LD_MEM_DATA 1
+#define EEH_ERR_FUNC_LD_IO_ADDR 2 /* IO load */
+#define EEH_ERR_FUNC_LD_IO_DATA 3
+#define EEH_ERR_FUNC_LD_CFG_ADDR 4 /* Config load */
+#define EEH_ERR_FUNC_LD_CFG_DATA 5
+#define EEH_ERR_FUNC_ST_MEM_ADDR 6 /* Memory store */
+#define EEH_ERR_FUNC_ST_MEM_DATA 7
+#define EEH_ERR_FUNC_ST_IO_ADDR 8 /* IO store */
+#define EEH_ERR_FUNC_ST_IO_DATA 9
+#define EEH_ERR_FUNC_ST_CFG_ADDR 10 /* Config store */
+#define EEH_ERR_FUNC_ST_CFG_DATA 11
+#define EEH_ERR_FUNC_DMA_RD_ADDR 12 /* DMA read */
+#define EEH_ERR_FUNC_DMA_RD_DATA 13
+#define EEH_ERR_FUNC_DMA_RD_MASTER 14
+#define EEH_ERR_FUNC_DMA_RD_TARGET 15
+#define EEH_ERR_FUNC_DMA_WR_ADDR 16 /* DMA write */
+#define EEH_ERR_FUNC_DMA_WR_DATA 17
+#define EEH_ERR_FUNC_DMA_WR_MASTER 18
+#define EEH_ERR_FUNC_DMA_WR_TARGET 19
+#define EEH_ERR_FUNC_MAX EEH_ERR_FUNC_DMA_WR_TARGET
+
+/*
+ * RTAS ibm,errinjct error type byte values. These are RTAS ABI token
+ * numbers, not the same as the VFIO EEH ABI type values consumed by
+ * VFIO_EEH_PE_INJECT_ERR. An explicit mapping is required.
+ */
+/* Use powerpc EEH UAPI constants where available; define locally otherwise. */
+#ifndef EEH_ERR_TYPE_32
+#define EEH_ERR_TYPE_32 0
+#endif
+#ifndef EEH_ERR_TYPE_64
+#define EEH_ERR_TYPE_64 1
+#endif
+
+/* RTAS PCI Error Injection Token Types */
+enum rtas_err_type {
+ RTAS_ERR_TYPE_FATAL = 0x1,
+ RTAS_ERR_TYPE_RECOVERED_RANDOM_EVENT = 0x2,
+ RTAS_ERR_TYPE_RECOVERED_SPECIAL_EVENT = 0x3,
+ RTAS_ERR_TYPE_CORRUPTED_PAGE = 0x4,
+ RTAS_ERR_TYPE_CORRUPTED_SLB = 0x5,
+ RTAS_ERR_TYPE_TRANSLATOR_FAILURE = 0x6,
+ RTAS_ERR_TYPE_IOA_BUS_ERROR = 0x7,
+ RTAS_ERR_TYPE_PLATFORM_SPECIFIC = 0x8,
+ RTAS_ERR_TYPE_CORRUPTED_DCACHE_START = 0x9,
+ RTAS_ERR_TYPE_CORRUPTED_DCACHE_END = 0xA,
+ RTAS_ERR_TYPE_CORRUPTED_ICACHE_START = 0xB,
+ RTAS_ERR_TYPE_CORRUPTED_ICACHE_END = 0xC,
+ RTAS_ERR_TYPE_CORRUPTED_TLB_START = 0xD,
+ RTAS_ERR_TYPE_CORRUPTED_TLB_END = 0xE,
+ RTAS_ERR_TYPE_IOA_BUS_ERROR_64 = 0xF,
+ RTAS_ERR_TYPE_UPSTREAM_IO_ERROR = 0x10
+};
+
/* ibm,set-slot-reset */
#define RTAS_SLOT_RESET_DEACTIVATE 0
#define RTAS_SLOT_RESET_HOT 1
@@ -764,8 +821,9 @@ void push_sregs_to_kvm_pr(SpaprMachineState *spapr);
#define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x2B)
#define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C)
#define RTAS_CONFIGURE_KERNEL_DUMP (RTAS_TOKEN_BASE + 0x2D)
+#define RTAS_IBM_ERRINJCT (RTAS_TOKEN_BASE + 0x2E)
-#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2E)
+#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2F)
/* RTAS ibm,get-system-parameter token values */
#define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20
diff --git a/hw/ppc/spapr_pci_vfio.c b/hw/ppc/spapr_pci_vfio.c
index a748a0bf4c..7afca0cec6 100644
--- a/hw/ppc/spapr_pci_vfio.c
+++ b/hw/ppc/spapr_pci_vfio.c
@@ -26,6 +26,7 @@
#include "hw/pci/pci_device.h"
#include "hw/vfio/vfio-container-legacy.h"
#include "qemu/error-report.h"
+#include "hw/vfio/pci.h"
#include CONFIG_DEVICES /* CONFIG_VFIO_PCI */
/*
@@ -317,6 +318,74 @@ int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb)
return RTAS_OUT_SUCCESS;
}
+static int spapr_vfio_errinjct_rtas_type_to_vfio(uint32_t rtas_type)
+{
+ switch (rtas_type) {
+ case RTAS_ERR_TYPE_IOA_BUS_ERROR:
+ return EEH_ERR_TYPE_32;
+ case RTAS_ERR_TYPE_IOA_BUS_ERROR_64:
+ return EEH_ERR_TYPE_64;
+ default:
+ return -1;
+ }
+}
+
+static bool spapr_vfio_errinjct_func_valid(uint32_t func)
+{
+ return func <= EEH_ERR_FUNC_MAX;
+}
+
+int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t type,
+ uint32_t func, uint64_t addr, uint64_t mask)
+{
+ VFIOLegacyContainer *container;
+ struct vfio_eeh_pe_op op = {
+ .op = VFIO_EEH_PE_INJECT_ERR,
+ .argsz = sizeof(op),
+ };
+ int vfio_type;
+
+ if (!sphb) {
+ return RTAS_OUT_PARAM_ERROR;
+ }
+
+ if (!spapr_vfio_errinjct_func_valid(func)) {
+ return RTAS_OUT_PARAM_ERROR;
+ }
+
+ vfio_type = spapr_vfio_errinjct_rtas_type_to_vfio(type);
+ if (vfio_type < 0) {
+ return RTAS_OUT_NOT_SUPPORTED;
+ }
+
+ container = vfio_eeh_as_container(&sphb->iommu_as);
+ if (!container) {
+ error_report("vfio/eeh errinjct: no VFIO EEH container for PHB");
+ return RTAS_OUT_NOT_SUPPORTED;
+ }
+
+ op.err.type = vfio_type;
+ op.err.func = func;
+ op.err.addr = addr;
+ op.err.mask = mask;
+
+ if (ioctl(container->fd, VFIO_EEH_PE_OP, &op) < 0) {
+ error_report("vfio/eeh errinjct: VFIO_EEH_PE_OP failed: %s",
+ strerror(errno));
+ switch (errno) {
+ case EINVAL:
+ return RTAS_OUT_PARAM_ERROR;
+ case ENOTTY:
+ case EOPNOTSUPP:
+ return RTAS_OUT_NOT_SUPPORTED;
+ default:
+ return RTAS_OUT_HW_ERROR;
+ }
+ }
+
+ return RTAS_OUT_SUCCESS;
+}
+
#else
bool spapr_phb_eeh_available(SpaprPhbState *sphb)
@@ -349,4 +418,10 @@ int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb)
return RTAS_OUT_NOT_SUPPORTED;
}
+int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t type,
+ uint32_t func, uint64_t addr, uint64_t mask)
+{
+ return RTAS_OUT_NOT_SUPPORTED;
+}
+
#endif /* CONFIG_VFIO_PCI */
--
2.51.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v5 2/6] ppc/spapr: Add ibm,errinjct RTAS call handler
2026-09-01 17:41 [PATCH v5 0/6] ppc/spapr: Add RTAS error injection support for VFIO EEH Narayana Murty N
2026-09-01 17:41 ` [PATCH v5 1/6] ppc/spapr: Add VFIO EEH error injection backend Narayana Murty N
@ 2026-09-01 17:41 ` Narayana Murty N
2026-09-01 17:41 ` [PATCH v5 3/6] ppc/spapr: Add support for ibm, open-errinjct and ibm, close-errinjct Narayana Murty N
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Narayana Murty N @ 2026-09-01 17:41 UTC (permalink / raw)
To: qemu-devel, qemu-ppc, mahesh, sbhat, anushree.mathur, clg,
sourabhjain, adityag, nikhilks
Cc: pierrick.bouvier, rathc, npiggin, harshpb, amachhiw, hbathini,
shivangu
Implement the 'ibm,errinjct' RTAS call for PHB-level PCI error injection
via firmware. The handler decodes the RTAS parameter buffer, validates
arguments, selects the target PHB by BUID, and delegates the injection
to the VFIO EEH backend.
IOA bus-error injection (types 0x7 and 0xF) is fully supported:
- The BUID field in the RTAS parameter block selects the target PHB
via spapr_pci_find_phb();
- For addr != 0 or mask != 0 the guest BAR address is translated to
the corresponding host resource base address before calling the VFIO
backend. Translation matches the guest BAR layout under the
selected PHB, computes offset = guest_addr - guest_bar, reads the
host sysfs resource file for the matching BAR, and yields
host_addr = host_bar + offset.
- For addr == 0 and mask == 0 translation is skipped and zero
addr/mask are forwarded directly (powerpc-utils errinjct -a 0 -m 0).
Non-IOA error types (corrupted-page, dcache, icache, tlb,
recovered-special-event) are decoded and validated, then rejected with
RTAS_OUT_NOT_SUPPORTED because their RTAS work buffers do not carry a
BUID, making safe VFIO PHB/PE selection impossible.
The translation helpers added to spapr_pci_vfio.c:
- spapr_phb_vfio_translate_errinjct_addr() - public entry point
- spapr_vfio_errinjct_find_bar_cb() - per-device BAR scan
- spapr_vfio_errinjct_get_host_bar() - host sysfs BAR reader
config_addr is retained as a logging/debug parameter only; PHB
selection relies on BUID.
Signed-off-by: Narayana Murty N <nnmlinux@linux.ibm.com>
---
include/hw/pci-host/spapr.h | 11 ++
include/hw/ppc/spapr.h | 3 +
hw/ppc/spapr_pci.c | 135 ++++++++++++++++++++++++
hw/ppc/spapr_pci_vfio.c | 203 ++++++++++++++++++++++++++++++++++++
4 files changed, 352 insertions(+)
diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h
index 24109409f4..492f66e1ef 100644
--- a/include/hw/pci-host/spapr.h
+++ b/include/hw/pci-host/spapr.h
@@ -127,6 +127,10 @@ int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb);
void spapr_phb_vfio_reset(DeviceState *qdev);
int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t type,
uint32_t func, uint64_t addr, uint64_t mask);
+int spapr_phb_vfio_translate_errinjct_addr(SpaprPhbState *sphb,
+ uint32_t config_addr,
+ uint64_t guest_addr,
+ uint64_t *host_pci_bus_addr);
#else
static inline bool spapr_phb_eeh_available(SpaprPhbState *sphb)
{
@@ -159,6 +163,13 @@ static inline int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t type,
{
return RTAS_OUT_NOT_SUPPORTED;
}
+static inline int spapr_phb_vfio_translate_errinjct_addr(SpaprPhbState *sphb,
+ uint32_t config_addr,
+ uint64_t guest_addr,
+ uint64_t *host_addr)
+{
+ return -ENOTSUP;
+}
#endif
void spapr_phb_dma_reset(SpaprPhbState *sphb);
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 253dc0e862..47791c71bd 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -274,6 +274,9 @@ struct SpaprMachineState {
bool fadump_registered;
bool fadump_dump_active;
FadumpMemStruct registered_fdm;
+
+ /* ibm,errinjct session token (0 = no session open) */
+ uint32_t errinjct_token;
};
#define H_SUCCESS 0
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index c1d4b7806e..cff12ef268 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -704,6 +704,138 @@ param_error_exit:
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
}
+static int spapr_errinjct_parse_ioa_bus_error(target_ulong param_buf,
+ bool is_64bit,
+ uint64_t *addr, uint64_t *mask,
+ uint32_t *config_addr,
+ uint64_t *buid, uint32_t *func)
+{
+ if (is_64bit) {
+ *addr = ((uint64_t)rtas_ld(param_buf, 0) << 32) |
+ rtas_ld(param_buf, 1);
+ *mask = ((uint64_t)rtas_ld(param_buf, 2) << 32) |
+ rtas_ld(param_buf, 3);
+ *config_addr = rtas_ld(param_buf, 4);
+ *buid = ((uint64_t)rtas_ld(param_buf, 5) << 32) |
+ rtas_ld(param_buf, 6);
+ *func = rtas_ld(param_buf, 7);
+ } else {
+ *addr = rtas_ld(param_buf, 0);
+ *mask = rtas_ld(param_buf, 1);
+ *config_addr = rtas_ld(param_buf, 2);
+ *buid = ((uint64_t)rtas_ld(param_buf, 3) << 32) |
+ rtas_ld(param_buf, 4);
+ *func = rtas_ld(param_buf, 5);
+ }
+ return RTAS_OUT_SUCCESS;
+}
+
+/*
+ * Non-IOA RTAS error types (page corrupt, dcache, icache, tlb, special
+ * event) are validated but not supported for VFIO injection. VFIO EEH
+ * is PE/PHB-scoped and those work buffers do not carry a BUID, so QEMU
+ * cannot select the right VFIO container safely.
+ */
+static void spapr_errinjct_return_non_ioa_unsupported(target_ulong rets)
+{
+ rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED);
+}
+
+static void rtas_ibm_errinjct(PowerPCCPU *cpu, SpaprMachineState *spapr,
+ uint32_t token, uint32_t nargs,
+ target_ulong args, uint32_t nret,
+ target_ulong rets)
+{
+ SpaprPhbState *sphb = NULL;
+ target_ulong param_buf;
+ uint64_t addr = 0, mask = 0, buid = 0;
+ uint64_t inject_addr = 0;
+ uint32_t config_addr = 0;
+ uint32_t func = 0;
+ uint32_t type, o_token;
+ bool is_64bit;
+ int ret;
+
+ if (nargs != 3 || nret != 1) {
+ goto param_error_exit;
+ }
+
+ type = rtas_ld(args, 0);
+ o_token = rtas_ld(args, 1);
+ param_buf = rtas_ld(args, 2);
+
+ if (!param_buf) {
+ goto param_error_exit;
+ }
+
+ if (!spapr->errinjct_token || o_token != spapr->errinjct_token) {
+ goto param_error_exit;
+ }
+
+ switch (type) {
+ case RTAS_ERR_TYPE_IOA_BUS_ERROR:
+ case RTAS_ERR_TYPE_IOA_BUS_ERROR_64:
+ is_64bit = (type == RTAS_ERR_TYPE_IOA_BUS_ERROR_64);
+ ret = spapr_errinjct_parse_ioa_bus_error(param_buf, is_64bit,
+ &addr, &mask,
+ &config_addr, &buid, &func);
+ if (ret != RTAS_OUT_SUCCESS) {
+ goto param_error_exit;
+ }
+ break;
+
+ case RTAS_ERR_TYPE_RECOVERED_SPECIAL_EVENT:
+ case RTAS_ERR_TYPE_CORRUPTED_PAGE:
+ case RTAS_ERR_TYPE_CORRUPTED_DCACHE_START:
+ case RTAS_ERR_TYPE_CORRUPTED_DCACHE_END:
+ case RTAS_ERR_TYPE_CORRUPTED_ICACHE_START:
+ case RTAS_ERR_TYPE_CORRUPTED_ICACHE_END:
+ case RTAS_ERR_TYPE_CORRUPTED_TLB_START:
+ case RTAS_ERR_TYPE_CORRUPTED_TLB_END:
+ spapr_errinjct_return_non_ioa_unsupported(rets);
+ return;
+
+ default:
+ goto param_error_exit;
+ }
+
+ /* IOA path: BUID selects the target PHB */
+ if (!buid) {
+ goto param_error_exit;
+ }
+
+ sphb = spapr_pci_find_phb(spapr, buid);
+ if (!sphb) {
+ error_report("ibm,errinjct: no PHB for BUID=0x%016" PRIx64, buid);
+ rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
+ return;
+ }
+
+ inject_addr = addr;
+
+ /*
+ * addr=0, mask=0 means a non-address-scoped IOA injection. This
+ * matches powerpc-utils errinjct -a 0 -m 0 behaviour; skip translation
+ * and forward addr/mask as zero.
+ */
+ if (addr || mask) {
+ ret = spapr_phb_vfio_translate_errinjct_addr(sphb, config_addr,
+ addr, &inject_addr);
+ if (ret) {
+ rtas_st(rets, 0, ret == -EOPNOTSUPP ? RTAS_OUT_NOT_SUPPORTED
+ : RTAS_OUT_PARAM_ERROR);
+ return;
+ }
+ }
+
+ ret = spapr_phb_vfio_errinjct(sphb, type, func, inject_addr, mask);
+ rtas_st(rets, 0, ret);
+ return;
+
+param_error_exit:
+ rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
+}
+
static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
{
/*
@@ -2380,6 +2512,9 @@ void spapr_pci_rtas_init(void)
spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL,
"ibm,slot-error-detail",
rtas_ibm_slot_error_detail);
+ spapr_rtas_register(RTAS_IBM_ERRINJCT,
+ "ibm,errinjct",
+ rtas_ibm_errinjct);
}
static void spapr_pci_register_types(void)
diff --git a/hw/ppc/spapr_pci_vfio.c b/hw/ppc/spapr_pci_vfio.c
index 7afca0cec6..2f428531cc 100644
--- a/hw/ppc/spapr_pci_vfio.c
+++ b/hw/ppc/spapr_pci_vfio.c
@@ -318,6 +318,201 @@ int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb)
return RTAS_OUT_SUCCESS;
}
+typedef struct SpaprVFIOErrinjctBarMatch {
+ uint64_t guest_addr;
+
+ PCIDevice *pdev;
+ VFIOPCIDevice *vdev;
+ int bar;
+
+ uint64_t guest_bar_start;
+ uint64_t bar_size;
+ uint64_t offset;
+} SpaprVFIOErrinjctBarMatch;
+
+static VFIOPCIDevice *spapr_vfio_errinjct_pci_to_vfio(PCIDevice *pdev)
+{
+ if (!object_dynamic_cast(OBJECT(pdev), TYPE_VFIO_PCI)) {
+ return NULL;
+ }
+
+ return container_of(pdev, VFIOPCIDevice, parent_obj);
+}
+
+static void spapr_vfio_errinjct_find_bar_cb(PCIBus *bus,
+ PCIDevice *pdev,
+ void *opaque)
+{
+ SpaprVFIOErrinjctBarMatch *ctx = opaque;
+ VFIOPCIDevice *vdev;
+ int bar;
+
+ if (ctx->pdev) {
+ return;
+ }
+
+ vdev = spapr_vfio_errinjct_pci_to_vfio(pdev);
+ if (!vdev) {
+ return;
+ }
+
+ for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
+ pcibus_t guest_bar_start;
+ uint64_t bar_size;
+ uint64_t offset;
+
+ bar_size = vdev->bars[bar].region.size;
+ if (!bar_size) {
+ continue;
+ }
+
+ guest_bar_start = pci_get_bar_addr(pdev, bar);
+ if (guest_bar_start == PCI_BAR_UNMAPPED) {
+ continue;
+ }
+
+ if (ctx->guest_addr < guest_bar_start ||
+ ctx->guest_addr - guest_bar_start >= bar_size) {
+ if (vdev->bars[bar].mem64) {
+ bar++;
+ }
+ continue;
+ }
+
+ offset = ctx->guest_addr - guest_bar_start;
+
+ ctx->pdev = pdev;
+ ctx->vdev = vdev;
+ ctx->bar = bar;
+ ctx->guest_bar_start = guest_bar_start;
+ ctx->bar_size = bar_size;
+ ctx->offset = offset;
+
+ return;
+ }
+}
+
+static int spapr_vfio_errinjct_get_host_bar(VFIOPCIDevice *vdev,
+ int bar,
+ uint64_t *host_bar_start)
+{
+ g_autofree char *path = NULL;
+ g_autofree char *contents = NULL;
+ char *line;
+ char *saveptr = NULL;
+ unsigned long long start;
+ unsigned long long end;
+ unsigned long long flags;
+ int i;
+
+ if (!vdev || !host_bar_start || bar < 0 || bar >= PCI_STD_NUM_BARS) {
+ return -EINVAL;
+ }
+
+ /*
+ * Read the host Linux sysfs resource file for the BAR. Do not use a
+ * VFIO PCI config-space read because that may return the
+ * guest-programmed BAR value rather than the host resource address.
+ */
+ path = g_strdup_printf("/sys/bus/pci/devices/%04x:%02x:%02x.%u/resource",
+ vdev->host.domain,
+ vdev->host.bus,
+ vdev->host.slot,
+ vdev->host.function);
+
+ if (!g_file_get_contents(path, &contents, NULL, NULL)) {
+ error_report("vfio/eeh errinjct: failed to read %s", path);
+ return -ENOENT;
+ }
+
+ line = strtok_r(contents, "\n", &saveptr);
+
+ for (i = 0; line; i++, line = strtok_r(NULL, "\n", &saveptr)) {
+ if (i != bar) {
+ continue;
+ }
+
+ if (sscanf(line, "%llx %llx %llx", &start, &end, &flags) != 3) {
+ error_report("vfio/eeh errinjct: malformed %s BAR%d",
+ path, bar);
+ return -EINVAL;
+ }
+
+ if (!start || end < start) {
+ error_report("vfio/eeh errinjct: invalid host resource BAR%d "
+ "start=0x%llx end=0x%llx flags=0x%llx",
+ bar, start, end, flags);
+ return -EINVAL;
+ }
+
+ *host_bar_start = start;
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+int spapr_phb_vfio_translate_errinjct_addr(SpaprPhbState *sphb,
+ uint32_t config_addr,
+ uint64_t guest_addr,
+ uint64_t *host_pci_bus_addr)
+{
+ PCIHostState *phb;
+ SpaprVFIOErrinjctBarMatch ctx = {
+ .guest_addr = guest_addr,
+ .pdev = NULL,
+ .vdev = NULL,
+ .bar = -1,
+ };
+ uint64_t host_bar_start;
+ int rc;
+
+ if (!sphb || !host_pci_bus_addr) {
+ return -EINVAL;
+ }
+
+ phb = PCI_HOST_BRIDGE(sphb);
+
+ /*
+ * BUID has already selected @sphb before this helper is called.
+ * config_addr is retained for logging/debug only. Do not rely on it
+ * to find the target device; some RTAS IOA buffers may not carry a
+ * valid guest BDF-style config address. Scan VFIO BARs under this
+ * PHB and match guest_addr against the guest BAR layout instead.
+ */
+ pci_for_each_device_under_bus(phb->bus,
+ spapr_vfio_errinjct_find_bar_cb,
+ &ctx);
+
+ if (!ctx.pdev) {
+ error_report("vfio/eeh errinjct: guest addr 0x%" PRIx64
+ " not within any VFIO BAR under BUID=0x%016" PRIx64
+ " config_addr=0x%08x",
+ guest_addr, sphb->buid, config_addr);
+ return -ENODEV;
+ }
+
+ rc = spapr_vfio_errinjct_get_host_bar(ctx.vdev, ctx.bar, &host_bar_start);
+ if (rc) {
+ error_report("vfio/eeh errinjct: failed to get host BAR%d for "
+ "dev=%s BUID=0x%016" PRIx64 " config_addr=0x%08x rc=%d",
+ ctx.bar, ctx.pdev->name, sphb->buid, config_addr, rc);
+ return rc;
+ }
+
+ if (host_bar_start == ctx.guest_bar_start) {
+ error_report("vfio/eeh errinjct: refusing guest BAR as host BAR: "
+ "dev=%s BAR%d guest_bar=0x%" PRIx64
+ " host_bar=0x%" PRIx64,
+ ctx.pdev->name, ctx.bar,
+ ctx.guest_bar_start, host_bar_start);
+ return -EOPNOTSUPP;
+ }
+
+ *host_pci_bus_addr = host_bar_start + ctx.offset;
+ return 0;
+}
+
static int spapr_vfio_errinjct_rtas_type_to_vfio(uint32_t rtas_type)
{
switch (rtas_type) {
@@ -424,4 +619,12 @@ int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t type,
return RTAS_OUT_NOT_SUPPORTED;
}
+int spapr_phb_vfio_translate_errinjct_addr(SpaprPhbState *sphb,
+ uint32_t config_addr,
+ uint64_t guest_addr,
+ uint64_t *host_pci_bus_addr)
+{
+ return -ENOTSUP;
+}
+
#endif /* CONFIG_VFIO_PCI */
--
2.51.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v5 3/6] ppc/spapr: Add support for ibm, open-errinjct and ibm, close-errinjct
2026-09-01 17:41 [PATCH v5 0/6] ppc/spapr: Add RTAS error injection support for VFIO EEH Narayana Murty N
2026-09-01 17:41 ` [PATCH v5 1/6] ppc/spapr: Add VFIO EEH error injection backend Narayana Murty N
2026-09-01 17:41 ` [PATCH v5 2/6] ppc/spapr: Add ibm,errinjct RTAS call handler Narayana Murty N
@ 2026-09-01 17:41 ` Narayana Murty N
2026-09-01 17:41 ` [PATCH v5 4/6] ppc/spapr: Advertise RTAS error injection call support via FDT property Narayana Murty N
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Narayana Murty N @ 2026-09-01 17:41 UTC (permalink / raw)
To: qemu-devel, qemu-ppc, mahesh, sbhat, anushree.mathur, clg,
sourabhjain, adityag, nikhilks
Cc: pierrick.bouvier, rathc, npiggin, harshpb, amachhiw, hbathini,
shivangu
Add RTAS handlers for ibm,open-errinjct and ibm,close-errinjct. These
calls manage exclusive access to the error-injection facility through a
simple session token mechanism: only one session may be open at a time.
ibm,open-errinjct (nargs=0, nret=2):
Returns rets[0]=token, rets[1]=status.
On success: token=1, status=RTAS_OUT_SUCCESS.
Already-open: token=0, status=RTAS_OUT_ALREADY_OPEN.
Bad args: token=0, status=RTAS_OUT_PARAM_ERROR.
ibm,close-errinjct (nargs=1, nret=1):
Takes the session token in args[0].
Returns RTAS_OUT_SUCCESS on a matching open token.
Returns RTAS_OUT_NOT_OPEN if the token is invalid or no session exists.
RTAS_IBM_OPEN_ERRINJCT and RTAS_IBM_CLOSE_ERRINJCT token values and
RTAS_OUT_ALREADY_OPEN / RTAS_OUT_NOT_OPEN return codes are added to
include/hw/ppc/spapr.h.
Signed-off-by: Narayana Murty N <nnmlinux@linux.ibm.com>
---
include/hw/ppc/spapr.h | 8 +++++-
hw/ppc/spapr_pci.c | 57 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 64 insertions(+), 1 deletion(-)
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 47791c71bd..bcb1da5fab 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -825,8 +825,14 @@ enum rtas_err_type {
#define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C)
#define RTAS_CONFIGURE_KERNEL_DUMP (RTAS_TOKEN_BASE + 0x2D)
#define RTAS_IBM_ERRINJCT (RTAS_TOKEN_BASE + 0x2E)
+#define RTAS_IBM_OPEN_ERRINJCT (RTAS_TOKEN_BASE + 0x2F)
+#define RTAS_IBM_CLOSE_ERRINJCT (RTAS_TOKEN_BASE + 0x30)
-#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2F)
+#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x31)
+
+/* ibm,open-errinjct/ibm,close-errinjct return codes */
+#define RTAS_OUT_ALREADY_OPEN -4
+#define RTAS_OUT_NOT_OPEN -5
/* RTAS ibm,get-system-parameter token values */
#define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index cff12ef268..20cb913f12 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -836,6 +836,57 @@ param_error_exit:
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
}
+static void rtas_ibm_open_errinjct(PowerPCCPU *cpu, SpaprMachineState *spapr,
+ uint32_t token, uint32_t nargs,
+ target_ulong args, uint32_t nret,
+ target_ulong rets)
+{
+ if (nargs != 0 || nret != 2) {
+ rtas_st(rets, 0, 0);
+ rtas_st(rets, 1, RTAS_OUT_PARAM_ERROR);
+ return;
+ }
+
+ if (spapr->errinjct_token) {
+ /* Session already open: return token=0, status=ALREADY_OPEN */
+ rtas_st(rets, 0, 0);
+ rtas_st(rets, 1, RTAS_OUT_ALREADY_OPEN);
+ return;
+ }
+
+ spapr->errinjct_token = 1;
+
+ /*
+ * ibm,open-errinjct has an unusual return convention: rets[0] is the
+ * session token and rets[1] is the status code.
+ */
+ rtas_st(rets, 0, spapr->errinjct_token);
+ rtas_st(rets, 1, RTAS_OUT_SUCCESS);
+}
+
+static void rtas_ibm_close_errinjct(PowerPCCPU *cpu, SpaprMachineState *spapr,
+ uint32_t token, uint32_t nargs,
+ target_ulong args, uint32_t nret,
+ target_ulong rets)
+{
+ uint32_t o_token;
+
+ if (nargs != 1 || nret != 1) {
+ rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
+ return;
+ }
+
+ o_token = rtas_ld(args, 0);
+
+ if (!spapr->errinjct_token || o_token != spapr->errinjct_token) {
+ rtas_st(rets, 0, RTAS_OUT_NOT_OPEN);
+ return;
+ }
+
+ spapr->errinjct_token = 0;
+ rtas_st(rets, 0, RTAS_OUT_SUCCESS);
+}
+
static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
{
/*
@@ -2515,6 +2566,12 @@ void spapr_pci_rtas_init(void)
spapr_rtas_register(RTAS_IBM_ERRINJCT,
"ibm,errinjct",
rtas_ibm_errinjct);
+ spapr_rtas_register(RTAS_IBM_OPEN_ERRINJCT,
+ "ibm,open-errinjct",
+ rtas_ibm_open_errinjct);
+ spapr_rtas_register(RTAS_IBM_CLOSE_ERRINJCT,
+ "ibm,close-errinjct",
+ rtas_ibm_close_errinjct);
}
static void spapr_pci_register_types(void)
--
2.51.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v5 4/6] ppc/spapr: Advertise RTAS error injection call support via FDT property
2026-09-01 17:41 [PATCH v5 0/6] ppc/spapr: Add RTAS error injection support for VFIO EEH Narayana Murty N
` (2 preceding siblings ...)
2026-09-01 17:41 ` [PATCH v5 3/6] ppc/spapr: Add support for ibm, open-errinjct and ibm, close-errinjct Narayana Murty N
@ 2026-09-01 17:41 ` Narayana Murty N
2026-09-01 17:41 ` [PATCH v5 5/6] ppc/spapr: Split VFIO EEH support from general VFIO code Narayana Murty N
2026-09-01 17:41 ` [PATCH v5 6/6] MAINTAINERS: Add self as sPAPR EEH reviewer under PPC RAS Narayana Murty N
5 siblings, 0 replies; 7+ messages in thread
From: Narayana Murty N @ 2026-09-01 17:41 UTC (permalink / raw)
To: qemu-devel, qemu-ppc, mahesh, sbhat, anushree.mathur, clg,
sourabhjain, adityag, nikhilks
Cc: pierrick.bouvier, rathc, npiggin, harshpb, amachhiw, hbathini,
shivangu
Advertise the supported ibm,errinjct token types to the guest through
the "ibm,errinjct-tokens" property under the RTAS node in the device
tree.
The property blob is built directly from a QEMU-side static table.
No host /proc/device-tree/rtas/ibm,errinjct-tokens probing is done
QEMU presents the same token set regardless of the host platform,
which avoids host-specific dependencies.
Each entry in the blob is a NUL-terminated token name string followed
by a big-endian uint32 type value, matching the PAPR specification for
ibm,errinjct-tokens.
"ibm,open-errinjct" and "ibm,close-errinjct" string properties are
also added to advertise the session-management calls.
Signed-off-by: Narayana Murty N <nnmlinux@linux.ibm.com>
---
hw/ppc/spapr.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 20e024907b..4c5b06d03d 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -116,6 +116,8 @@
#define PHANDLE_INTC 0x00001111
+#define ERRINJCT_BLOB_MAX 512
+
/* These two functions implement the VCPU id numbering: one to compute them
* all and one to identify thread 0 of a VCORE. Any change to the first one
* is likely to have an impact on the second one, so let's keep them close.
@@ -1081,6 +1083,65 @@ static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt)
*/
_FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
+ /*
+ * Advertise supported ibm,errinjct token types to the guest via the
+ * "ibm,errinjct-tokens" RTAS FDT property. The blob is built locally
+ * from the QEMU-side token table; no /proc/device-tree probing is done.
+ * Each entry is: NUL-terminated name string || big-endian uint32 type.
+ */
+ {
+ static const struct {
+ const char *name;
+ uint32_t type;
+ } tok_table[] = {
+ { "recovered-special-event",
+ RTAS_ERR_TYPE_RECOVERED_SPECIAL_EVENT },
+ { "corrupted-page", RTAS_ERR_TYPE_CORRUPTED_PAGE },
+ { "ioa-bus-error", RTAS_ERR_TYPE_IOA_BUS_ERROR },
+ { "corrupted-dcache-start",
+ RTAS_ERR_TYPE_CORRUPTED_DCACHE_START },
+ { "corrupted-dcache-end",
+ RTAS_ERR_TYPE_CORRUPTED_DCACHE_END },
+ { "corrupted-icache-start",
+ RTAS_ERR_TYPE_CORRUPTED_ICACHE_START },
+ { "corrupted-icache-end",
+ RTAS_ERR_TYPE_CORRUPTED_ICACHE_END },
+ { "corrupted-tlb-start",
+ RTAS_ERR_TYPE_CORRUPTED_TLB_START },
+ { "corrupted-tlb-end", RTAS_ERR_TYPE_CORRUPTED_TLB_END },
+ { "ioa-bus-error-64", RTAS_ERR_TYPE_IOA_BUS_ERROR_64 },
+ };
+ g_autofree char *errinject_tokens = NULL;
+ uint8_t blob[ERRINJCT_BLOB_MAX];
+ size_t blen = 0;
+ bool ok = true;
+
+ for (int i = 0; i < G_N_ELEMENTS(tok_table) && ok; i++) {
+ size_t slen = strlen(tok_table[i].name) + 1;
+ uint32_t be_type;
+
+ if (blen + slen + sizeof(be_type) > ERRINJCT_BLOB_MAX) {
+ ok = false;
+ break;
+ }
+ memcpy(blob + blen, tok_table[i].name, slen);
+ blen += slen;
+ be_type = cpu_to_be32(tok_table[i].type);
+ memcpy(blob + blen, &be_type, sizeof(be_type));
+ blen += sizeof(be_type);
+ }
+
+ if (ok) {
+ errinject_tokens = g_memdup2(blob, blen);
+ _FDT(fdt_setprop(fdt, rtas, "ibm,errinjct-tokens",
+ errinject_tokens, blen));
+ _FDT(fdt_setprop_string(fdt, rtas, "ibm,open-errinjct",
+ "ibm,open-errinjct"));
+ _FDT(fdt_setprop_string(fdt, rtas, "ibm,close-errinjct",
+ "ibm,close-errinjct"));
+ }
+ }
+
_FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
lrdr_capacity, sizeof(lrdr_capacity)));
--
2.51.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v5 5/6] ppc/spapr: Split VFIO EEH support from general VFIO code
2026-09-01 17:41 [PATCH v5 0/6] ppc/spapr: Add RTAS error injection support for VFIO EEH Narayana Murty N
` (3 preceding siblings ...)
2026-09-01 17:41 ` [PATCH v5 4/6] ppc/spapr: Advertise RTAS error injection call support via FDT property Narayana Murty N
@ 2026-09-01 17:41 ` Narayana Murty N
2026-09-01 17:41 ` [PATCH v5 6/6] MAINTAINERS: Add self as sPAPR EEH reviewer under PPC RAS Narayana Murty N
5 siblings, 0 replies; 7+ messages in thread
From: Narayana Murty N @ 2026-09-01 17:41 UTC (permalink / raw)
To: qemu-devel, qemu-ppc, mahesh, sbhat, anushree.mathur, clg,
sourabhjain, adityag, nikhilks
Cc: pierrick.bouvier, rathc, npiggin, harshpb, amachhiw, hbathini,
shivangu
Move all EEH and error-injection functions from spapr_pci_vfio.c into
a dedicated hw/ppc/spapr_eeh.c. spapr_eeh.c is compiled only
when CONFIG_VFIO_PCI is enabled;
spapr_pci_vfio.c is retained as a stub-only file compiled on Linux
when CONFIG_VFIO_PCI is not available, providing the non-functional
fallback implementations needed for Linux/pseries builds that do not
include VFIO PCI.
meson.build: replace the single spapr_pci_vfio.c entry with an
if_true/if_false pair keyed on CONFIG_VFIO_PCI:
CONFIG_VFIO_PCI=y -> spapr_eeh.c (real implementation)
CONFIG_VFIO_PCI=n -> spapr_pci_vfio-stubs.c (stubs)
No functional change to the EEH state machine.
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Narayana Murty N <nnmlinux@linux.ibm.com>
---
include/hw/pci-host/spapr.h | 56 +---
include/hw/ppc/spapr_vfio.h | 31 ++
hw/ppc/spapr_eeh.c | 571 +++++++++++++++++++++++++++++++++
hw/ppc/spapr_pci.c | 1 +
hw/ppc/spapr_pci_vfio.c | 591 +----------------------------------
stubs/spapr_phb_vfio-stubs.c | 62 ++++
hw/ppc/Kconfig | 2 +-
hw/ppc/meson.build | 1 +
stubs/meson.build | 1 +
9 files changed, 670 insertions(+), 646 deletions(-)
create mode 100644 include/hw/ppc/spapr_vfio.h
create mode 100644 hw/ppc/spapr_eeh.c
create mode 100644 stubs/spapr_phb_vfio-stubs.c
diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h
index 492f66e1ef..d2bc90a3d2 100644
--- a/include/hw/pci-host/spapr.h
+++ b/include/hw/pci-host/spapr.h
@@ -116,61 +116,7 @@ void spapr_phb_remove_pci_device_cb(DeviceState *dev);
int spapr_pci_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
void *fdt, int *fdt_start_offset, Error **errp);
-/* VFIO EEH hooks */
-#ifdef CONFIG_LINUX
-bool spapr_phb_eeh_available(SpaprPhbState *sphb);
-int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb,
- unsigned int addr, int option);
-int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, int *state);
-int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option);
-int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb);
-void spapr_phb_vfio_reset(DeviceState *qdev);
-int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t type,
- uint32_t func, uint64_t addr, uint64_t mask);
-int spapr_phb_vfio_translate_errinjct_addr(SpaprPhbState *sphb,
- uint32_t config_addr,
- uint64_t guest_addr,
- uint64_t *host_pci_bus_addr);
-#else
-static inline bool spapr_phb_eeh_available(SpaprPhbState *sphb)
-{
- return false;
-}
-static inline int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb,
- unsigned int addr, int option)
-{
- return RTAS_OUT_HW_ERROR;
-}
-static inline int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb,
- int *state)
-{
- return RTAS_OUT_HW_ERROR;
-}
-static inline int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option)
-{
- return RTAS_OUT_HW_ERROR;
-}
-static inline int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb)
-{
- return RTAS_OUT_HW_ERROR;
-}
-static inline void spapr_phb_vfio_reset(DeviceState *qdev)
-{
-}
-static inline int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t type,
- uint32_t func, uint64_t addr,
- uint64_t mask)
-{
- return RTAS_OUT_NOT_SUPPORTED;
-}
-static inline int spapr_phb_vfio_translate_errinjct_addr(SpaprPhbState *sphb,
- uint32_t config_addr,
- uint64_t guest_addr,
- uint64_t *host_addr)
-{
- return -ENOTSUP;
-}
-#endif
+/* VFIO EEH hooks - see hw/ppc/spapr_vfio.h for declarations */
void spapr_phb_dma_reset(SpaprPhbState *sphb);
diff --git a/include/hw/ppc/spapr_vfio.h b/include/hw/ppc/spapr_vfio.h
new file mode 100644
index 0000000000..5aabb262f2
--- /dev/null
+++ b/include/hw/ppc/spapr_vfio.h
@@ -0,0 +1,31 @@
+/*
+ * sPAPR VFIO EEH Header
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#ifndef HW_PPC_SPAPR_VFIO_H
+#define HW_PPC_SPAPR_VFIO_H
+
+/*
+ * Forward declarations to avoid pulling in full spapr headers
+ * This allows stubs and other files to compile without libfdt dependencies
+ */
+typedef struct SpaprPhbState SpaprPhbState;
+typedef struct DeviceState DeviceState;
+
+/* VFIO EEH function declarations */
+bool spapr_phb_eeh_available(SpaprPhbState *sphb);
+int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb,
+ unsigned int addr, int option);
+int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, int *state);
+int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option);
+int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb);
+void spapr_phb_vfio_reset(DeviceState *qdev);
+void spapr_phb_vfio_eeh_reenable(SpaprPhbState *sphb);
+int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t type,
+ uint32_t func, uint64_t addr, uint64_t mask);
+int spapr_phb_vfio_translate_errinjct_addr(SpaprPhbState *sphb,
+ uint32_t config_addr,
+ uint64_t guest_addr,
+ uint64_t *host_pci_bus_addr);
+#endif /* HW_PPC_SPAPR_VFIO_H */
diff --git a/hw/ppc/spapr_eeh.c b/hw/ppc/spapr_eeh.c
new file mode 100644
index 0000000000..a9b7fe2d67
--- /dev/null
+++ b/hw/ppc/spapr_eeh.c
@@ -0,0 +1,571 @@
+/*
+ * QEMU sPAPR PCI host for VFIO
+ *
+ * Copyright (c) 2011-2014 Alexey Kardashevskiy, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License,
+ * or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include <sys/ioctl.h>
+#include <linux/vfio.h>
+#include "hw/ppc/spapr.h"
+#include "hw/pci-host/spapr.h"
+#include "hw/pci/msix.h"
+#include "hw/pci/pci_device.h"
+#include "hw/vfio/vfio-container-legacy.h"
+#include "qemu/error-report.h"
+#include "hw/vfio/pci.h"
+#include "hw/ppc/spapr_vfio.h"
+
+/*
+ * Interfaces for IBM EEH (Enhanced Error Handling)
+ */
+static bool vfio_eeh_container_ok(VFIOLegacyContainer *container)
+{
+ /*
+ * As of 2016-03-04 (linux-4.5) the host kernel EEH/VFIO
+ * implementation is broken if there are multiple groups in a
+ * container. The hardware works in units of Partitionable
+ * Endpoints (== IOMMU groups) and the EEH operations naively
+ * iterate across all groups in the container, without any logic
+ * to make sure the groups have their state synchronized. For
+ * certain operations (ENABLE) that might be ok, until an error
+ * occurs, but for others (GET_STATE) it's clearly broken.
+ */
+
+ /*
+ * XXX Once fixed kernels exist, test for them here
+ */
+
+ if (QLIST_EMPTY(&container->group_list)) {
+ return false;
+ }
+
+ if (QLIST_NEXT(QLIST_FIRST(&container->group_list), container_next)) {
+ return false;
+ }
+
+ return true;
+}
+
+static int vfio_eeh_container_op(VFIOLegacyContainer *container, uint32_t op)
+{
+ struct vfio_eeh_pe_op pe_op = {
+ .argsz = sizeof(pe_op),
+ .op = op,
+ };
+ int ret;
+
+ if (!vfio_eeh_container_ok(container)) {
+ error_report("vfio/eeh: EEH_PE_OP 0x%x: "
+ "kernel requires a container with exactly one group", op);
+ return -EPERM;
+ }
+
+ ret = ioctl(container->fd, VFIO_EEH_PE_OP, &pe_op);
+ if (ret < 0) {
+ error_report("vfio/eeh: EEH_PE_OP 0x%x failed: %m", op);
+ return -errno;
+ }
+
+ return ret;
+}
+
+static VFIOLegacyContainer *vfio_eeh_as_container(AddressSpace *as)
+{
+ VFIOAddressSpace *space = vfio_address_space_get(as);
+ VFIOContainer *bcontainer = NULL;
+
+ if (QLIST_EMPTY(&space->containers)) {
+ /* No containers to act on */
+ goto out;
+ }
+
+ bcontainer = QLIST_FIRST(&space->containers);
+
+ if (QLIST_NEXT(bcontainer, next)) {
+ /*
+ * We don't yet have logic to synchronize EEH state across
+ * multiple containers
+ */
+ bcontainer = NULL;
+ goto out;
+ }
+
+out:
+ vfio_address_space_put(space);
+ return VFIO_IOMMU_LEGACY(bcontainer);
+}
+
+static bool vfio_eeh_as_ok(AddressSpace *as)
+{
+ VFIOLegacyContainer *container = vfio_eeh_as_container(as);
+
+ return (container != NULL) && vfio_eeh_container_ok(container);
+}
+
+static int vfio_eeh_as_op(AddressSpace *as, uint32_t op)
+{
+ VFIOLegacyContainer *container = vfio_eeh_as_container(as);
+
+ if (!container) {
+ return -ENODEV;
+ }
+ return vfio_eeh_container_op(container, op);
+}
+
+bool spapr_phb_eeh_available(SpaprPhbState *sphb)
+{
+ return vfio_eeh_as_ok(&sphb->iommu_as);
+}
+
+void spapr_phb_vfio_eeh_reenable(SpaprPhbState *sphb)
+{
+ vfio_eeh_as_op(&sphb->iommu_as, VFIO_EEH_PE_ENABLE);
+}
+
+static void spapr_eeh_pci_find_device(PCIBus *bus, PCIDevice *pdev,
+ void *opaque)
+{
+ bool *found = opaque;
+
+ if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) {
+ *found = true;
+ }
+}
+
+int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb,
+ unsigned int addr, int option)
+{
+ uint32_t op;
+ int ret;
+
+ switch (option) {
+ case RTAS_EEH_DISABLE:
+ op = VFIO_EEH_PE_DISABLE;
+ break;
+ case RTAS_EEH_ENABLE: {
+ PCIHostState *phb;
+ bool found = false;
+
+ /*
+ * The EEH functionality is enabled per sphb level instead of
+ * per PCI device. We have already identified this specific sphb
+ * based on buid passed as argument to ibm,set-eeh-option rtas
+ * call. Now we just need to check the validity of the PCI
+ * pass-through devices (vfio-pci) under this sphb bus.
+ * We have already validated that all the devices under this sphb
+ * are from same iommu group (within same PE) before coming here.
+ *
+ * Prior to linux commit 98ba956f6a389 ("powerpc/pseries/eeh:
+ * Rework device EEH PE determination") kernel would call
+ * eeh-set-option for each device in the PE using the device's
+ * config_address as the argument rather than the PE address.
+ * Hence if we check validity of supplied config_addr whether
+ * it matches to this PHB will cause issues with older kernel
+ * versions v5.9 and older. If we return an error from
+ * eeh-set-option when the argument isn't a valid PE address
+ * then older kernels (v5.9 and older) will interpret that as
+ * EEH not being supported.
+ */
+ phb = PCI_HOST_BRIDGE(sphb);
+ pci_for_each_device(phb->bus, (addr >> 16) & 0xFF,
+ spapr_eeh_pci_find_device, &found);
+
+ if (!found) {
+ return RTAS_OUT_PARAM_ERROR;
+ }
+
+ op = VFIO_EEH_PE_ENABLE;
+ break;
+ }
+ case RTAS_EEH_THAW_IO:
+ op = VFIO_EEH_PE_UNFREEZE_IO;
+ break;
+ case RTAS_EEH_THAW_DMA:
+ op = VFIO_EEH_PE_UNFREEZE_DMA;
+ break;
+ default:
+ return RTAS_OUT_PARAM_ERROR;
+ }
+
+ ret = vfio_eeh_as_op(&sphb->iommu_as, op);
+ if (ret < 0) {
+ return RTAS_OUT_HW_ERROR;
+ }
+
+ return RTAS_OUT_SUCCESS;
+}
+
+int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, int *state)
+{
+ int ret;
+
+ ret = vfio_eeh_as_op(&sphb->iommu_as, VFIO_EEH_PE_GET_STATE);
+ if (ret < 0) {
+ return RTAS_OUT_PARAM_ERROR;
+ }
+
+ *state = ret;
+ return RTAS_OUT_SUCCESS;
+}
+
+static void spapr_phb_vfio_eeh_clear_dev_msix(PCIBus *bus,
+ PCIDevice *pdev,
+ void *opaque)
+{
+ /* Check if the device is VFIO PCI device */
+ if (!object_dynamic_cast(OBJECT(pdev), "vfio-pci")) {
+ return;
+ }
+
+ /*
+ * The MSIx table will be cleaned out by reset. We need
+ * disable it so that it can be reenabled properly. Also,
+ * the cached MSIx table should be cleared as it's not
+ * reflecting the contents in hardware.
+ */
+ if (msix_enabled(pdev)) {
+ uint16_t flags;
+
+ flags = pci_host_config_read_common(pdev,
+ pdev->msix_cap + PCI_MSIX_FLAGS,
+ pci_config_size(pdev), 2);
+ flags &= ~PCI_MSIX_FLAGS_ENABLE;
+ pci_host_config_write_common(pdev,
+ pdev->msix_cap + PCI_MSIX_FLAGS,
+ pci_config_size(pdev), flags, 2);
+ }
+
+ msix_reset(pdev);
+}
+
+static void spapr_phb_vfio_eeh_clear_bus_msix(PCIBus *bus, void *opaque)
+{
+ pci_for_each_device_under_bus(bus, spapr_phb_vfio_eeh_clear_dev_msix,
+ NULL);
+}
+
+static void spapr_phb_vfio_eeh_pre_reset(SpaprPhbState *sphb)
+{
+ PCIHostState *phb = PCI_HOST_BRIDGE(sphb);
+
+ pci_for_each_bus(phb->bus, spapr_phb_vfio_eeh_clear_bus_msix, NULL);
+}
+
+int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option)
+{
+ uint32_t op;
+ int ret;
+
+ switch (option) {
+ case RTAS_SLOT_RESET_DEACTIVATE:
+ op = VFIO_EEH_PE_RESET_DEACTIVATE;
+ break;
+ case RTAS_SLOT_RESET_HOT:
+ spapr_phb_vfio_eeh_pre_reset(sphb);
+ op = VFIO_EEH_PE_RESET_HOT;
+ break;
+ case RTAS_SLOT_RESET_FUNDAMENTAL:
+ spapr_phb_vfio_eeh_pre_reset(sphb);
+ op = VFIO_EEH_PE_RESET_FUNDAMENTAL;
+ break;
+ default:
+ return RTAS_OUT_PARAM_ERROR;
+ }
+
+ ret = vfio_eeh_as_op(&sphb->iommu_as, op);
+ if (ret < 0) {
+ return RTAS_OUT_HW_ERROR;
+ }
+
+ return RTAS_OUT_SUCCESS;
+}
+
+int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb)
+{
+ int ret;
+
+ ret = vfio_eeh_as_op(&sphb->iommu_as, VFIO_EEH_PE_CONFIGURE);
+ if (ret < 0) {
+ return RTAS_OUT_PARAM_ERROR;
+ }
+
+ return RTAS_OUT_SUCCESS;
+}
+
+typedef struct SpaprVFIOErrinjctBarMatch {
+ uint64_t guest_addr;
+
+ PCIDevice *pdev;
+ VFIOPCIDevice *vdev;
+ int bar;
+
+ uint64_t guest_bar_start;
+ uint64_t bar_size;
+ uint64_t offset;
+} SpaprVFIOErrinjctBarMatch;
+
+static VFIOPCIDevice *spapr_vfio_errinjct_pci_to_vfio(PCIDevice *pdev)
+{
+ if (!object_dynamic_cast(OBJECT(pdev), TYPE_VFIO_PCI)) {
+ return NULL;
+ }
+
+ return container_of(pdev, VFIOPCIDevice, parent_obj);
+}
+
+static void spapr_vfio_errinjct_find_bar_cb(PCIBus *bus,
+ PCIDevice *pdev,
+ void *opaque)
+{
+ SpaprVFIOErrinjctBarMatch *ctx = opaque;
+ VFIOPCIDevice *vdev;
+ int bar;
+
+ if (ctx->pdev) {
+ return;
+ }
+
+ vdev = spapr_vfio_errinjct_pci_to_vfio(pdev);
+ if (!vdev) {
+ return;
+ }
+
+ for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
+ pcibus_t guest_bar_start;
+ uint64_t bar_size;
+ uint64_t offset;
+
+ bar_size = vdev->bars[bar].region.size;
+ if (!bar_size) {
+ continue;
+ }
+
+ guest_bar_start = pci_get_bar_addr(pdev, bar);
+ if (guest_bar_start == PCI_BAR_UNMAPPED) {
+ continue;
+ }
+
+ if (ctx->guest_addr < guest_bar_start ||
+ ctx->guest_addr - guest_bar_start >= bar_size) {
+ if (vdev->bars[bar].mem64) {
+ bar++;
+ }
+ continue;
+ }
+
+ offset = ctx->guest_addr - guest_bar_start;
+
+ ctx->pdev = pdev;
+ ctx->vdev = vdev;
+ ctx->bar = bar;
+ ctx->guest_bar_start = guest_bar_start;
+ ctx->bar_size = bar_size;
+ ctx->offset = offset;
+
+ return;
+ }
+}
+
+static int spapr_vfio_errinjct_get_host_bar(VFIOPCIDevice *vdev,
+ int bar,
+ uint64_t *host_bar_start)
+{
+ g_autofree char *path = NULL;
+ g_autofree char *contents = NULL;
+ char *line;
+ char *saveptr = NULL;
+ unsigned long long start;
+ unsigned long long end;
+ unsigned long long flags;
+ int i;
+
+ if (!vdev || !host_bar_start || bar < 0 || bar >= PCI_STD_NUM_BARS) {
+ return -EINVAL;
+ }
+
+ /*
+ * Read the host Linux sysfs resource file for the BAR. Do not use a
+ * VFIO PCI config-space read because that may return the
+ * guest-programmed BAR value rather than the host resource address.
+ */
+ path = g_strdup_printf("/sys/bus/pci/devices/%04x:%02x:%02x.%u/resource",
+ vdev->host.domain,
+ vdev->host.bus,
+ vdev->host.slot,
+ vdev->host.function);
+
+ if (!g_file_get_contents(path, &contents, NULL, NULL)) {
+ error_report("vfio/eeh errinjct: failed to read %s", path);
+ return -ENOENT;
+ }
+
+ line = strtok_r(contents, "\n", &saveptr);
+
+ for (i = 0; line; i++, line = strtok_r(NULL, "\n", &saveptr)) {
+ if (i != bar) {
+ continue;
+ }
+
+ if (sscanf(line, "%llx %llx %llx", &start, &end, &flags) != 3) {
+ error_report("vfio/eeh errinjct: malformed %s BAR%d",
+ path, bar);
+ return -EINVAL;
+ }
+
+ if (!start || end < start) {
+ error_report("vfio/eeh errinjct: invalid host resource BAR%d "
+ "start=0x%llx end=0x%llx flags=0x%llx",
+ bar, start, end, flags);
+ return -EINVAL;
+ }
+
+ *host_bar_start = start;
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+int spapr_phb_vfio_translate_errinjct_addr(SpaprPhbState *sphb,
+ uint32_t config_addr,
+ uint64_t guest_addr,
+ uint64_t *host_pci_bus_addr)
+{
+ PCIHostState *phb;
+ SpaprVFIOErrinjctBarMatch ctx = {
+ .guest_addr = guest_addr,
+ .pdev = NULL,
+ .vdev = NULL,
+ .bar = -1,
+ };
+ uint64_t host_bar_start;
+ int rc;
+
+ if (!sphb || !host_pci_bus_addr) {
+ return -EINVAL;
+ }
+
+ phb = PCI_HOST_BRIDGE(sphb);
+
+ /*
+ * BUID has already selected @sphb before this helper is called.
+ * config_addr is retained for logging/debug only. Do not rely on it
+ * to find the target device; some RTAS IOA buffers may not carry a
+ * valid guest BDF-style config address. Scan VFIO BARs under this
+ * PHB and match guest_addr against the guest BAR layout instead.
+ */
+ pci_for_each_device_under_bus(phb->bus,
+ spapr_vfio_errinjct_find_bar_cb,
+ &ctx);
+
+ if (!ctx.pdev) {
+ error_report("vfio/eeh errinjct: guest addr 0x%" PRIx64
+ " not within any VFIO BAR under BUID=0x%016" PRIx64
+ " config_addr=0x%08x",
+ guest_addr, sphb->buid, config_addr);
+ return -ENODEV;
+ }
+
+ rc = spapr_vfio_errinjct_get_host_bar(ctx.vdev, ctx.bar, &host_bar_start);
+ if (rc) {
+ error_report("vfio/eeh errinjct: failed to get host BAR%d for "
+ "dev=%s BUID=0x%016" PRIx64 " config_addr=0x%08x rc=%d",
+ ctx.bar, ctx.pdev->name, sphb->buid, config_addr, rc);
+ return rc;
+ }
+
+ if (host_bar_start == ctx.guest_bar_start) {
+ error_report("vfio/eeh errinjct: refusing guest BAR as host BAR: "
+ "dev=%s BAR%d guest_bar=0x%" PRIx64
+ " host_bar=0x%" PRIx64,
+ ctx.pdev->name, ctx.bar,
+ ctx.guest_bar_start, host_bar_start);
+ return -EOPNOTSUPP;
+ }
+
+ *host_pci_bus_addr = host_bar_start + ctx.offset;
+ return 0;
+}
+
+static int spapr_vfio_errinjct_rtas_type_to_vfio(uint32_t rtas_type)
+{
+ switch (rtas_type) {
+ case RTAS_ERR_TYPE_IOA_BUS_ERROR:
+ return EEH_ERR_TYPE_32;
+ case RTAS_ERR_TYPE_IOA_BUS_ERROR_64:
+ return EEH_ERR_TYPE_64;
+ default:
+ return -1;
+ }
+}
+
+static bool spapr_vfio_errinjct_func_valid(uint32_t func)
+{
+ return func <= EEH_ERR_FUNC_MAX;
+}
+
+int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t type,
+ uint32_t func, uint64_t addr, uint64_t mask)
+{
+ VFIOLegacyContainer *container;
+ struct vfio_eeh_pe_op op = {
+ .op = VFIO_EEH_PE_INJECT_ERR,
+ .argsz = sizeof(op),
+ };
+ int vfio_type;
+
+ if (!sphb) {
+ return RTAS_OUT_PARAM_ERROR;
+ }
+
+ if (!spapr_vfio_errinjct_func_valid(func)) {
+ return RTAS_OUT_PARAM_ERROR;
+ }
+
+ vfio_type = spapr_vfio_errinjct_rtas_type_to_vfio(type);
+ if (vfio_type < 0) {
+ return RTAS_OUT_NOT_SUPPORTED;
+ }
+
+ container = vfio_eeh_as_container(&sphb->iommu_as);
+ if (!container) {
+ error_report("vfio/eeh errinjct: no VFIO EEH container for PHB");
+ return RTAS_OUT_NOT_SUPPORTED;
+ }
+
+ op.err.type = vfio_type;
+ op.err.func = func;
+ op.err.addr = addr;
+ op.err.mask = mask;
+
+ if (ioctl(container->fd, VFIO_EEH_PE_OP, &op) < 0) {
+ error_report("vfio/eeh errinjct: VFIO_EEH_PE_OP failed: %s",
+ strerror(errno));
+ switch (errno) {
+ case EINVAL:
+ return RTAS_OUT_PARAM_ERROR;
+ case ENOTTY:
+ case EOPNOTSUPP:
+ return RTAS_OUT_NOT_SUPPORTED;
+ default:
+ return RTAS_OUT_HW_ERROR;
+ }
+ }
+
+ return RTAS_OUT_SUCCESS;
+}
+
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index 20cb913f12..33a1011890 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -33,6 +33,7 @@
#include "hw/pci/msix.h"
#include "hw/pci/pci_host.h"
#include "hw/ppc/spapr.h"
+#include "hw/ppc/spapr_vfio.h"
#include "hw/pci-host/spapr.h"
#include <libfdt.h>
#include "trace.h"
diff --git a/hw/ppc/spapr_pci_vfio.c b/hw/ppc/spapr_pci_vfio.c
index 2f428531cc..e6ecc3f1ee 100644
--- a/hw/ppc/spapr_pci_vfio.c
+++ b/hw/ppc/spapr_pci_vfio.c
@@ -22,120 +22,12 @@
#include <linux/vfio.h>
#include "hw/ppc/spapr.h"
#include "hw/pci-host/spapr.h"
+#include "hw/ppc/spapr_vfio.h"
#include "hw/pci/msix.h"
#include "hw/pci/pci_device.h"
#include "hw/vfio/vfio-container-legacy.h"
#include "qemu/error-report.h"
#include "hw/vfio/pci.h"
-#include CONFIG_DEVICES /* CONFIG_VFIO_PCI */
-
-/*
- * Interfaces for IBM EEH (Enhanced Error Handling)
- */
-#ifdef CONFIG_VFIO_PCI
-static bool vfio_eeh_container_ok(VFIOLegacyContainer *container)
-{
- /*
- * As of 2016-03-04 (linux-4.5) the host kernel EEH/VFIO
- * implementation is broken if there are multiple groups in a
- * container. The hardware works in units of Partitionable
- * Endpoints (== IOMMU groups) and the EEH operations naively
- * iterate across all groups in the container, without any logic
- * to make sure the groups have their state synchronized. For
- * certain operations (ENABLE) that might be ok, until an error
- * occurs, but for others (GET_STATE) it's clearly broken.
- */
-
- /*
- * XXX Once fixed kernels exist, test for them here
- */
-
- if (QLIST_EMPTY(&container->group_list)) {
- return false;
- }
-
- if (QLIST_NEXT(QLIST_FIRST(&container->group_list), container_next)) {
- return false;
- }
-
- return true;
-}
-
-static int vfio_eeh_container_op(VFIOLegacyContainer *container, uint32_t op)
-{
- struct vfio_eeh_pe_op pe_op = {
- .argsz = sizeof(pe_op),
- .op = op,
- };
- int ret;
-
- if (!vfio_eeh_container_ok(container)) {
- error_report("vfio/eeh: EEH_PE_OP 0x%x: "
- "kernel requires a container with exactly one group", op);
- return -EPERM;
- }
-
- ret = ioctl(container->fd, VFIO_EEH_PE_OP, &pe_op);
- if (ret < 0) {
- error_report("vfio/eeh: EEH_PE_OP 0x%x failed: %m", op);
- return -errno;
- }
-
- return ret;
-}
-
-static VFIOLegacyContainer *vfio_eeh_as_container(AddressSpace *as)
-{
- VFIOAddressSpace *space = vfio_address_space_get(as);
- VFIOContainer *bcontainer = NULL;
-
- if (QLIST_EMPTY(&space->containers)) {
- /* No containers to act on */
- goto out;
- }
-
- bcontainer = QLIST_FIRST(&space->containers);
-
- if (QLIST_NEXT(bcontainer, next)) {
- /*
- * We don't yet have logic to synchronize EEH state across
- * multiple containers
- */
- bcontainer = NULL;
- goto out;
- }
-
-out:
- vfio_address_space_put(space);
- return VFIO_IOMMU_LEGACY(bcontainer);
-}
-
-static bool vfio_eeh_as_ok(AddressSpace *as)
-{
- VFIOLegacyContainer *container = vfio_eeh_as_container(as);
-
- return (container != NULL) && vfio_eeh_container_ok(container);
-}
-
-static int vfio_eeh_as_op(AddressSpace *as, uint32_t op)
-{
- VFIOLegacyContainer *container = vfio_eeh_as_container(as);
-
- if (!container) {
- return -ENODEV;
- }
- return vfio_eeh_container_op(container, op);
-}
-
-bool spapr_phb_eeh_available(SpaprPhbState *sphb)
-{
- return vfio_eeh_as_ok(&sphb->iommu_as);
-}
-
-static void spapr_phb_vfio_eeh_reenable(SpaprPhbState *sphb)
-{
- vfio_eeh_as_op(&sphb->iommu_as, VFIO_EEH_PE_ENABLE);
-}
void spapr_phb_vfio_reset(DeviceState *qdev)
{
@@ -147,484 +39,3 @@ void spapr_phb_vfio_reset(DeviceState *qdev)
*/
spapr_phb_vfio_eeh_reenable(SPAPR_PCI_HOST_BRIDGE(qdev));
}
-
-static void spapr_eeh_pci_find_device(PCIBus *bus, PCIDevice *pdev,
- void *opaque)
-{
- bool *found = opaque;
-
- if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) {
- *found = true;
- }
-}
-
-int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb,
- unsigned int addr, int option)
-{
- uint32_t op;
- int ret;
-
- switch (option) {
- case RTAS_EEH_DISABLE:
- op = VFIO_EEH_PE_DISABLE;
- break;
- case RTAS_EEH_ENABLE: {
- PCIHostState *phb;
- bool found = false;
-
- /*
- * The EEH functionality is enabled per sphb level instead of
- * per PCI device. We have already identified this specific sphb
- * based on buid passed as argument to ibm,set-eeh-option rtas
- * call. Now we just need to check the validity of the PCI
- * pass-through devices (vfio-pci) under this sphb bus.
- * We have already validated that all the devices under this sphb
- * are from same iommu group (within same PE) before coming here.
- *
- * Prior to linux commit 98ba956f6a389 ("powerpc/pseries/eeh:
- * Rework device EEH PE determination") kernel would call
- * eeh-set-option for each device in the PE using the device's
- * config_address as the argument rather than the PE address.
- * Hence if we check validity of supplied config_addr whether
- * it matches to this PHB will cause issues with older kernel
- * versions v5.9 and older. If we return an error from
- * eeh-set-option when the argument isn't a valid PE address
- * then older kernels (v5.9 and older) will interpret that as
- * EEH not being supported.
- */
- phb = PCI_HOST_BRIDGE(sphb);
- pci_for_each_device(phb->bus, (addr >> 16) & 0xFF,
- spapr_eeh_pci_find_device, &found);
-
- if (!found) {
- return RTAS_OUT_PARAM_ERROR;
- }
-
- op = VFIO_EEH_PE_ENABLE;
- break;
- }
- case RTAS_EEH_THAW_IO:
- op = VFIO_EEH_PE_UNFREEZE_IO;
- break;
- case RTAS_EEH_THAW_DMA:
- op = VFIO_EEH_PE_UNFREEZE_DMA;
- break;
- default:
- return RTAS_OUT_PARAM_ERROR;
- }
-
- ret = vfio_eeh_as_op(&sphb->iommu_as, op);
- if (ret < 0) {
- return RTAS_OUT_HW_ERROR;
- }
-
- return RTAS_OUT_SUCCESS;
-}
-
-int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, int *state)
-{
- int ret;
-
- ret = vfio_eeh_as_op(&sphb->iommu_as, VFIO_EEH_PE_GET_STATE);
- if (ret < 0) {
- return RTAS_OUT_PARAM_ERROR;
- }
-
- *state = ret;
- return RTAS_OUT_SUCCESS;
-}
-
-static void spapr_phb_vfio_eeh_clear_dev_msix(PCIBus *bus,
- PCIDevice *pdev,
- void *opaque)
-{
- /* Check if the device is VFIO PCI device */
- if (!object_dynamic_cast(OBJECT(pdev), "vfio-pci")) {
- return;
- }
-
- /*
- * The MSIx table will be cleaned out by reset. We need
- * disable it so that it can be reenabled properly. Also,
- * the cached MSIx table should be cleared as it's not
- * reflecting the contents in hardware.
- */
- if (msix_enabled(pdev)) {
- uint16_t flags;
-
- flags = pci_host_config_read_common(pdev,
- pdev->msix_cap + PCI_MSIX_FLAGS,
- pci_config_size(pdev), 2);
- flags &= ~PCI_MSIX_FLAGS_ENABLE;
- pci_host_config_write_common(pdev,
- pdev->msix_cap + PCI_MSIX_FLAGS,
- pci_config_size(pdev), flags, 2);
- }
-
- msix_reset(pdev);
-}
-
-static void spapr_phb_vfio_eeh_clear_bus_msix(PCIBus *bus, void *opaque)
-{
- pci_for_each_device_under_bus(bus, spapr_phb_vfio_eeh_clear_dev_msix,
- NULL);
-}
-
-static void spapr_phb_vfio_eeh_pre_reset(SpaprPhbState *sphb)
-{
- PCIHostState *phb = PCI_HOST_BRIDGE(sphb);
-
- pci_for_each_bus(phb->bus, spapr_phb_vfio_eeh_clear_bus_msix, NULL);
-}
-
-int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option)
-{
- uint32_t op;
- int ret;
-
- switch (option) {
- case RTAS_SLOT_RESET_DEACTIVATE:
- op = VFIO_EEH_PE_RESET_DEACTIVATE;
- break;
- case RTAS_SLOT_RESET_HOT:
- spapr_phb_vfio_eeh_pre_reset(sphb);
- op = VFIO_EEH_PE_RESET_HOT;
- break;
- case RTAS_SLOT_RESET_FUNDAMENTAL:
- spapr_phb_vfio_eeh_pre_reset(sphb);
- op = VFIO_EEH_PE_RESET_FUNDAMENTAL;
- break;
- default:
- return RTAS_OUT_PARAM_ERROR;
- }
-
- ret = vfio_eeh_as_op(&sphb->iommu_as, op);
- if (ret < 0) {
- return RTAS_OUT_HW_ERROR;
- }
-
- return RTAS_OUT_SUCCESS;
-}
-
-int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb)
-{
- int ret;
-
- ret = vfio_eeh_as_op(&sphb->iommu_as, VFIO_EEH_PE_CONFIGURE);
- if (ret < 0) {
- return RTAS_OUT_PARAM_ERROR;
- }
-
- return RTAS_OUT_SUCCESS;
-}
-
-typedef struct SpaprVFIOErrinjctBarMatch {
- uint64_t guest_addr;
-
- PCIDevice *pdev;
- VFIOPCIDevice *vdev;
- int bar;
-
- uint64_t guest_bar_start;
- uint64_t bar_size;
- uint64_t offset;
-} SpaprVFIOErrinjctBarMatch;
-
-static VFIOPCIDevice *spapr_vfio_errinjct_pci_to_vfio(PCIDevice *pdev)
-{
- if (!object_dynamic_cast(OBJECT(pdev), TYPE_VFIO_PCI)) {
- return NULL;
- }
-
- return container_of(pdev, VFIOPCIDevice, parent_obj);
-}
-
-static void spapr_vfio_errinjct_find_bar_cb(PCIBus *bus,
- PCIDevice *pdev,
- void *opaque)
-{
- SpaprVFIOErrinjctBarMatch *ctx = opaque;
- VFIOPCIDevice *vdev;
- int bar;
-
- if (ctx->pdev) {
- return;
- }
-
- vdev = spapr_vfio_errinjct_pci_to_vfio(pdev);
- if (!vdev) {
- return;
- }
-
- for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
- pcibus_t guest_bar_start;
- uint64_t bar_size;
- uint64_t offset;
-
- bar_size = vdev->bars[bar].region.size;
- if (!bar_size) {
- continue;
- }
-
- guest_bar_start = pci_get_bar_addr(pdev, bar);
- if (guest_bar_start == PCI_BAR_UNMAPPED) {
- continue;
- }
-
- if (ctx->guest_addr < guest_bar_start ||
- ctx->guest_addr - guest_bar_start >= bar_size) {
- if (vdev->bars[bar].mem64) {
- bar++;
- }
- continue;
- }
-
- offset = ctx->guest_addr - guest_bar_start;
-
- ctx->pdev = pdev;
- ctx->vdev = vdev;
- ctx->bar = bar;
- ctx->guest_bar_start = guest_bar_start;
- ctx->bar_size = bar_size;
- ctx->offset = offset;
-
- return;
- }
-}
-
-static int spapr_vfio_errinjct_get_host_bar(VFIOPCIDevice *vdev,
- int bar,
- uint64_t *host_bar_start)
-{
- g_autofree char *path = NULL;
- g_autofree char *contents = NULL;
- char *line;
- char *saveptr = NULL;
- unsigned long long start;
- unsigned long long end;
- unsigned long long flags;
- int i;
-
- if (!vdev || !host_bar_start || bar < 0 || bar >= PCI_STD_NUM_BARS) {
- return -EINVAL;
- }
-
- /*
- * Read the host Linux sysfs resource file for the BAR. Do not use a
- * VFIO PCI config-space read because that may return the
- * guest-programmed BAR value rather than the host resource address.
- */
- path = g_strdup_printf("/sys/bus/pci/devices/%04x:%02x:%02x.%u/resource",
- vdev->host.domain,
- vdev->host.bus,
- vdev->host.slot,
- vdev->host.function);
-
- if (!g_file_get_contents(path, &contents, NULL, NULL)) {
- error_report("vfio/eeh errinjct: failed to read %s", path);
- return -ENOENT;
- }
-
- line = strtok_r(contents, "\n", &saveptr);
-
- for (i = 0; line; i++, line = strtok_r(NULL, "\n", &saveptr)) {
- if (i != bar) {
- continue;
- }
-
- if (sscanf(line, "%llx %llx %llx", &start, &end, &flags) != 3) {
- error_report("vfio/eeh errinjct: malformed %s BAR%d",
- path, bar);
- return -EINVAL;
- }
-
- if (!start || end < start) {
- error_report("vfio/eeh errinjct: invalid host resource BAR%d "
- "start=0x%llx end=0x%llx flags=0x%llx",
- bar, start, end, flags);
- return -EINVAL;
- }
-
- *host_bar_start = start;
- return 0;
- }
-
- return -EINVAL;
-}
-
-int spapr_phb_vfio_translate_errinjct_addr(SpaprPhbState *sphb,
- uint32_t config_addr,
- uint64_t guest_addr,
- uint64_t *host_pci_bus_addr)
-{
- PCIHostState *phb;
- SpaprVFIOErrinjctBarMatch ctx = {
- .guest_addr = guest_addr,
- .pdev = NULL,
- .vdev = NULL,
- .bar = -1,
- };
- uint64_t host_bar_start;
- int rc;
-
- if (!sphb || !host_pci_bus_addr) {
- return -EINVAL;
- }
-
- phb = PCI_HOST_BRIDGE(sphb);
-
- /*
- * BUID has already selected @sphb before this helper is called.
- * config_addr is retained for logging/debug only. Do not rely on it
- * to find the target device; some RTAS IOA buffers may not carry a
- * valid guest BDF-style config address. Scan VFIO BARs under this
- * PHB and match guest_addr against the guest BAR layout instead.
- */
- pci_for_each_device_under_bus(phb->bus,
- spapr_vfio_errinjct_find_bar_cb,
- &ctx);
-
- if (!ctx.pdev) {
- error_report("vfio/eeh errinjct: guest addr 0x%" PRIx64
- " not within any VFIO BAR under BUID=0x%016" PRIx64
- " config_addr=0x%08x",
- guest_addr, sphb->buid, config_addr);
- return -ENODEV;
- }
-
- rc = spapr_vfio_errinjct_get_host_bar(ctx.vdev, ctx.bar, &host_bar_start);
- if (rc) {
- error_report("vfio/eeh errinjct: failed to get host BAR%d for "
- "dev=%s BUID=0x%016" PRIx64 " config_addr=0x%08x rc=%d",
- ctx.bar, ctx.pdev->name, sphb->buid, config_addr, rc);
- return rc;
- }
-
- if (host_bar_start == ctx.guest_bar_start) {
- error_report("vfio/eeh errinjct: refusing guest BAR as host BAR: "
- "dev=%s BAR%d guest_bar=0x%" PRIx64
- " host_bar=0x%" PRIx64,
- ctx.pdev->name, ctx.bar,
- ctx.guest_bar_start, host_bar_start);
- return -EOPNOTSUPP;
- }
-
- *host_pci_bus_addr = host_bar_start + ctx.offset;
- return 0;
-}
-
-static int spapr_vfio_errinjct_rtas_type_to_vfio(uint32_t rtas_type)
-{
- switch (rtas_type) {
- case RTAS_ERR_TYPE_IOA_BUS_ERROR:
- return EEH_ERR_TYPE_32;
- case RTAS_ERR_TYPE_IOA_BUS_ERROR_64:
- return EEH_ERR_TYPE_64;
- default:
- return -1;
- }
-}
-
-static bool spapr_vfio_errinjct_func_valid(uint32_t func)
-{
- return func <= EEH_ERR_FUNC_MAX;
-}
-
-int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t type,
- uint32_t func, uint64_t addr, uint64_t mask)
-{
- VFIOLegacyContainer *container;
- struct vfio_eeh_pe_op op = {
- .op = VFIO_EEH_PE_INJECT_ERR,
- .argsz = sizeof(op),
- };
- int vfio_type;
-
- if (!sphb) {
- return RTAS_OUT_PARAM_ERROR;
- }
-
- if (!spapr_vfio_errinjct_func_valid(func)) {
- return RTAS_OUT_PARAM_ERROR;
- }
-
- vfio_type = spapr_vfio_errinjct_rtas_type_to_vfio(type);
- if (vfio_type < 0) {
- return RTAS_OUT_NOT_SUPPORTED;
- }
-
- container = vfio_eeh_as_container(&sphb->iommu_as);
- if (!container) {
- error_report("vfio/eeh errinjct: no VFIO EEH container for PHB");
- return RTAS_OUT_NOT_SUPPORTED;
- }
-
- op.err.type = vfio_type;
- op.err.func = func;
- op.err.addr = addr;
- op.err.mask = mask;
-
- if (ioctl(container->fd, VFIO_EEH_PE_OP, &op) < 0) {
- error_report("vfio/eeh errinjct: VFIO_EEH_PE_OP failed: %s",
- strerror(errno));
- switch (errno) {
- case EINVAL:
- return RTAS_OUT_PARAM_ERROR;
- case ENOTTY:
- case EOPNOTSUPP:
- return RTAS_OUT_NOT_SUPPORTED;
- default:
- return RTAS_OUT_HW_ERROR;
- }
- }
-
- return RTAS_OUT_SUCCESS;
-}
-
-#else
-
-bool spapr_phb_eeh_available(SpaprPhbState *sphb)
-{
- return false;
-}
-
-void spapr_phb_vfio_reset(DeviceState *qdev)
-{
-}
-
-int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb,
- unsigned int addr, int option)
-{
- return RTAS_OUT_NOT_SUPPORTED;
-}
-
-int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, int *state)
-{
- return RTAS_OUT_NOT_SUPPORTED;
-}
-
-int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option)
-{
- return RTAS_OUT_NOT_SUPPORTED;
-}
-
-int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb)
-{
- return RTAS_OUT_NOT_SUPPORTED;
-}
-
-int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t type,
- uint32_t func, uint64_t addr, uint64_t mask)
-{
- return RTAS_OUT_NOT_SUPPORTED;
-}
-
-int spapr_phb_vfio_translate_errinjct_addr(SpaprPhbState *sphb,
- uint32_t config_addr,
- uint64_t guest_addr,
- uint64_t *host_pci_bus_addr)
-{
- return -ENOTSUP;
-}
-
-#endif /* CONFIG_VFIO_PCI */
diff --git a/stubs/spapr_phb_vfio-stubs.c b/stubs/spapr_phb_vfio-stubs.c
new file mode 100644
index 0000000000..4d86d9000e
--- /dev/null
+++ b/stubs/spapr_phb_vfio-stubs.c
@@ -0,0 +1,62 @@
+/*
+ * Stubs for sPAPR PCI VFIO EEH
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "hw/ppc/spapr_vfio.h"
+
+/* RTAS return codes */
+#define RTAS_OUT_NOT_SUPPORTED (-3)
+
+
+bool spapr_phb_eeh_available(SpaprPhbState *sphb)
+{
+ return false;
+}
+
+int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb,
+ unsigned int addr, int option)
+{
+ return RTAS_OUT_NOT_SUPPORTED;
+}
+
+int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, int *state)
+{
+ return RTAS_OUT_NOT_SUPPORTED;
+}
+
+int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option)
+{
+ return RTAS_OUT_NOT_SUPPORTED;
+}
+
+int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb)
+{
+ return RTAS_OUT_NOT_SUPPORTED;
+}
+
+void spapr_phb_vfio_reset(DeviceState *qdev)
+{
+}
+
+void spapr_phb_vfio_eeh_reenable(SpaprPhbState *sphb)
+{
+}
+
+int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t type,
+ uint32_t func, uint64_t addr, uint64_t mask)
+{
+ return RTAS_OUT_NOT_SUPPORTED;
+}
+
+int spapr_phb_vfio_translate_errinjct_addr(SpaprPhbState *sphb,
+ uint32_t config_addr,
+ uint64_t guest_addr,
+ uint64_t *host_pci_bus_addr)
+{
+ return -ENOTSUP;
+}
+
+
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index 347dcce690..3714d708d9 100644
--- a/hw/ppc/Kconfig
+++ b/hw/ppc/Kconfig
@@ -6,7 +6,7 @@ config PSERIES
imply PCI_DEVICES
imply TEST_DEVICES
imply VIRTIO_VGA
- imply VFIO_PCI if LINUX # needed by spapr_pci_vfio.c
+ imply VFIO_PCI if LINUX # needed by spapr_pci_vfio.c and spapr_eeh.c
select NVDIMM
select DIMM
select PCI
diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build
index 37aa535db2..4e03973440 100644
--- a/hw/ppc/meson.build
+++ b/hw/ppc/meson.build
@@ -36,6 +36,7 @@ ppc_ss.add(when: 'CONFIG_SPAPR_RNG', if_true: files('spapr_rng.c'))
if host_os == 'linux'
ppc_ss.add(when: 'CONFIG_PSERIES', if_true: files(
'spapr_pci_vfio.c',
+ 'spapr_eeh.c',
))
endif
diff --git a/stubs/meson.build b/stubs/meson.build
index 3b2f2680b1..2879d6f70e 100644
--- a/stubs/meson.build
+++ b/stubs/meson.build
@@ -90,6 +90,7 @@ if have_system
stub_ss.add(files('hmp-cmd-info_tlb.c'))
stub_ss.add(files('hmp-cmds-hw-s390x.c'))
stub_ss.add(files('hmp-cmds-target-i386.c'))
+ stub_ss.add(files('spapr_phb_vfio-stubs.c'))
endif
if have_system or have_user
--
2.51.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v5 6/6] MAINTAINERS: Add self as sPAPR EEH reviewer under PPC RAS
2026-09-01 17:41 [PATCH v5 0/6] ppc/spapr: Add RTAS error injection support for VFIO EEH Narayana Murty N
` (4 preceding siblings ...)
2026-09-01 17:41 ` [PATCH v5 5/6] ppc/spapr: Split VFIO EEH support from general VFIO code Narayana Murty N
@ 2026-09-01 17:41 ` Narayana Murty N
5 siblings, 0 replies; 7+ messages in thread
From: Narayana Murty N @ 2026-09-01 17:41 UTC (permalink / raw)
To: qemu-devel, qemu-ppc, mahesh, sbhat, anushree.mathur, clg,
sourabhjain, adityag, nikhilks
Cc: pierrick.bouvier, rathc, npiggin, harshpb, amachhiw, hbathini,
shivangu
Adding self as reviewer for the sPAPR EEH under PPC RAS.
Updating the EEH specific file name as got updated in previous patches.
Signed-off-by: Narayana Murty N <nnmlinux@linux.ibm.com>
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 4a49a40294..581c109392 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1770,11 +1770,13 @@ M: Aditya Gupta <adityag@linux.ibm.com>
R: Sourabh Jain <sourabhjain@linux.ibm.com>
R: Hari Bathini <hbathini@linux.ibm.com>
R: Shivang Upadhyay <shivangu@linux.ibm.com>
+R: Narayana Murty N <nnmlinux@linux.ibm.com>
L: qemu-ppc@nongnu.org
S: Maintained
F: hw/ppc/spapr_events.c
F: hw/ppc/spapr_fadump.c
F: hw/ppc/spapr_pci_vfio.c
+F: hw/ppc/spapr_eeh.c
F: hw/ppc/spapr_rtas.c
F: hw/ppc/pnv_mpipl.c
F: include/hw/ppc/spapr_fadump.h
--
2.51.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
end of thread, other threads:[~2026-09-01 17:43 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-09-01 17:41 [PATCH v5 0/6] ppc/spapr: Add RTAS error injection support for VFIO EEH Narayana Murty N
2026-09-01 17:41 ` [PATCH v5 1/6] ppc/spapr: Add VFIO EEH error injection backend Narayana Murty N
2026-09-01 17:41 ` [PATCH v5 2/6] ppc/spapr: Add ibm,errinjct RTAS call handler Narayana Murty N
2026-09-01 17:41 ` [PATCH v5 3/6] ppc/spapr: Add support for ibm, open-errinjct and ibm, close-errinjct Narayana Murty N
2026-09-01 17:41 ` [PATCH v5 4/6] ppc/spapr: Advertise RTAS error injection call support via FDT property Narayana Murty N
2026-09-01 17:41 ` [PATCH v5 5/6] ppc/spapr: Split VFIO EEH support from general VFIO code Narayana Murty N
2026-09-01 17:41 ` [PATCH v5 6/6] MAINTAINERS: Add self as sPAPR EEH reviewer under PPC RAS Narayana Murty N
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