From: Alex Deucher <alexander.deucher@amd.com>
To: <amd-gfx@lists.freedesktop.org>, <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Subject: [PATCH 05/31] drm/amdgpu/gmc9: set vmhub funcs for gfxhub and mmhub
Date: Tue, 1 Sep 2026 16:10:08 -0400 [thread overview]
Message-ID: <20260901201034.2960437-6-alexander.deucher@amd.com> (raw)
In-Reply-To: <20260901201034.2960437-1-alexander.deucher@amd.com>
This was handled in gmc_v9_0 directly. Set the pointers
so that we can use rely on the callbacks in the generic gmc
helpers.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 33 ++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c | 33 ++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 21 +--------------
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 33 ++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c | 32 +++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c | 32 +++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 32 +++++++++++++++++++++++
7 files changed, 196 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index bfe247b1a333c..f4e6c8b6c2cf9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -410,6 +410,37 @@ static void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
}
+static void
+gfxhub_v1_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
+ uint32_t status)
+{
+ /* this is handled in gmc_v9_0.c already */
+}
+
+static uint32_t gfxhub_v1_0_get_invalidate_req(unsigned int vmid,
+ uint32_t flush_type)
+{
+ u32 req = 0;
+
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
+ PER_VMID_INVALIDATE_REQ, 1 << vmid);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
+ CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
+
+ return req;
+}
+
+static const struct amdgpu_vmhub_funcs gfxhub_v1_0_vmhub_funcs = {
+ .print_l2_protection_fault_status = gfxhub_v1_0_print_l2_protection_fault_status,
+ .get_invalidate_req = gfxhub_v1_0_get_invalidate_req,
+};
+
static void gfxhub_v1_0_init(struct amdgpu_device *adev)
{
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
@@ -439,6 +470,8 @@ static void gfxhub_v1_0_init(struct amdgpu_device *adev)
hub->eng_distance = mmVM_INVALIDATE_ENG1_REQ - mmVM_INVALIDATE_ENG0_REQ;
hub->eng_addr_distance = mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
+
+ hub->vmhub_funcs = &gfxhub_v1_0_vmhub_funcs;
}
const struct amdgpu_gfxhub_funcs gfxhub_v1_0_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
index fbdf46070b38b..fd216e1670abe 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
@@ -539,6 +539,37 @@ static void gfxhub_v1_2_set_fault_enable_default(struct amdgpu_device *adev,
gfxhub_v1_2_xcc_set_fault_enable_default(adev, value, xcc_mask);
}
+static void
+gfxhub_v1_2_print_l2_protection_fault_status(struct amdgpu_device *adev,
+ uint32_t status)
+{
+ /* this is handled in gmc_v9_0.c already */
+}
+
+static uint32_t gfxhub_v1_2_get_invalidate_req(unsigned int vmid,
+ uint32_t flush_type)
+{
+ u32 req = 0;
+
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
+ PER_VMID_INVALIDATE_REQ, 1 << vmid);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
+ CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
+
+ return req;
+}
+
+static const struct amdgpu_vmhub_funcs gfxhub_v1_2_vmhub_funcs = {
+ .print_l2_protection_fault_status = gfxhub_v1_2_print_l2_protection_fault_status,
+ .get_invalidate_req = gfxhub_v1_2_get_invalidate_req,
+};
+
static void gfxhub_v1_2_xcc_init(struct amdgpu_device *adev, uint32_t xcc_mask)
{
struct amdgpu_vmhub *hub;
@@ -577,6 +608,8 @@ static void gfxhub_v1_2_xcc_init(struct amdgpu_device *adev, uint32_t xcc_mask)
hub->eng_addr_distance =
regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
+
+ hub->vmhub_funcs = &gfxhub_v1_2_vmhub_funcs;
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 80f1cf1f21736..73b96efd45484 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -705,25 +705,6 @@ static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
}
}
-static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid,
- uint32_t flush_type)
-{
- u32 req = 0;
-
- req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
- PER_VMID_INVALIDATE_REQ, 1 << vmid);
- req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
- req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
- req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
- req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
- req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
- req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
- req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
- CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
-
- return req;
-}
-
/**
* gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore
*
@@ -785,7 +766,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
BUG_ON(vmhub >= AMDGPU_MAX_VMHUBS);
hub = &adev->vmhub[vmhub];
- inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type);
+ inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng;
req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 243eabda06077..46b0fc94007cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -464,6 +464,37 @@ static void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool
WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
}
+static uint32_t mmhub_v1_0_get_invalidate_req(unsigned int vmid,
+ uint32_t flush_type)
+{
+ u32 req = 0;
+
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
+ PER_VMID_INVALIDATE_REQ, 1 << vmid);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
+ CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
+
+ return req;
+}
+
+static void
+mmhub_v1_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
+ uint32_t status)
+{
+ /* this is handled in gmc_v9_0.c already */
+}
+
+static const struct amdgpu_vmhub_funcs mmhub_v1_0_vmhub_funcs = {
+ .print_l2_protection_fault_status = mmhub_v1_0_print_l2_protection_fault_status,
+ .get_invalidate_req = mmhub_v1_0_get_invalidate_req,
+};
+
static void mmhub_v1_0_init(struct amdgpu_device *adev)
{
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
@@ -493,6 +524,8 @@ static void mmhub_v1_0_init(struct amdgpu_device *adev)
hub->eng_distance = mmVM_INVALIDATE_ENG1_REQ - mmVM_INVALIDATE_ENG0_REQ;
hub->eng_addr_distance = mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
+
+ hub->vmhub_funcs = &mmhub_v1_0_vmhub_funcs;
}
static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
index 2adee2b94c37d..84d1dc32728bd 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
@@ -448,6 +448,37 @@ static void mmhub_v1_7_set_fault_enable_default(struct amdgpu_device *adev, bool
WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL, tmp);
}
+static void
+mmhub_v1_7_print_l2_protection_fault_status(struct amdgpu_device *adev,
+ uint32_t status)
+{
+ /* this is handled in gmc_v9_0.c already */
+}
+
+static uint32_t mmhub_v1_7_get_invalidate_req(unsigned int vmid,
+ uint32_t flush_type)
+{
+ u32 req = 0;
+
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
+ PER_VMID_INVALIDATE_REQ, 1 << vmid);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
+ CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
+
+ return req;
+}
+
+static const struct amdgpu_vmhub_funcs mmhub_v1_7_vmhub_funcs = {
+ .print_l2_protection_fault_status = mmhub_v1_7_print_l2_protection_fault_status,
+ .get_invalidate_req = mmhub_v1_7_get_invalidate_req,
+};
+
static void mmhub_v1_7_init(struct amdgpu_device *adev)
{
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
@@ -476,6 +507,7 @@ static void mmhub_v1_7_init(struct amdgpu_device *adev)
hub->eng_addr_distance = regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
+ hub->vmhub_funcs = &mmhub_v1_7_vmhub_funcs;
}
static void mmhub_v1_7_update_medium_grain_clock_gating(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
index 47d07cd25fc41..4c9f41905b650 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
@@ -577,6 +577,37 @@ static void mmhub_v1_8_set_fault_enable_default(struct amdgpu_device *adev, bool
}
}
+static void
+mmhub_v1_8_print_l2_protection_fault_status(struct amdgpu_device *adev,
+ uint32_t status)
+{
+ /* this is handled in gmc_v9_0.c already */
+}
+
+static uint32_t mmhub_v1_8_get_invalidate_req(unsigned int vmid,
+ uint32_t flush_type)
+{
+ u32 req = 0;
+
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
+ PER_VMID_INVALIDATE_REQ, 1 << vmid);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
+ CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
+
+ return req;
+}
+
+static const struct amdgpu_vmhub_funcs mmhub_v1_8_vmhub_funcs = {
+ .print_l2_protection_fault_status = mmhub_v1_8_print_l2_protection_fault_status,
+ .get_invalidate_req = mmhub_v1_8_get_invalidate_req,
+};
+
static void mmhub_v1_8_init(struct amdgpu_device *adev)
{
struct amdgpu_vmhub *hub;
@@ -610,6 +641,7 @@ static void mmhub_v1_8_init(struct amdgpu_device *adev)
regVM_INVALIDATE_ENG0_REQ;
hub->eng_addr_distance = regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
+ hub->vmhub_funcs = &mmhub_v1_8_vmhub_funcs;
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
index fe0710b55c3ac..af7958931b152 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
@@ -536,6 +536,37 @@ static void mmhub_v9_4_set_fault_enable_default(struct amdgpu_device *adev, bool
}
}
+static void
+mmhub_v9_4_print_l2_protection_fault_status(struct amdgpu_device *adev,
+ uint32_t status)
+{
+ /* this is handled in gmc_v9_0.c already */
+}
+
+static uint32_t mmhub_v9_4_get_invalidate_req(unsigned int vmid,
+ uint32_t flush_type)
+{
+ u32 req = 0;
+
+ req = REG_SET_FIELD(req, VML2VC0_VM_INVALIDATE_ENG0_REQ,
+ PER_VMID_INVALIDATE_REQ, 1 << vmid);
+ req = REG_SET_FIELD(req, VML2VC0_VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
+ req = REG_SET_FIELD(req, VML2VC0_VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
+ req = REG_SET_FIELD(req, VML2VC0_VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
+ req = REG_SET_FIELD(req, VML2VC0_VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
+ req = REG_SET_FIELD(req, VML2VC0_VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
+ req = REG_SET_FIELD(req, VML2VC0_VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
+ req = REG_SET_FIELD(req, VML2VC0_VM_INVALIDATE_ENG0_REQ,
+ CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
+
+ return req;
+}
+
+static const struct amdgpu_vmhub_funcs mmhub_v9_4_vmhub_funcs = {
+ .print_l2_protection_fault_status = mmhub_v9_4_print_l2_protection_fault_status,
+ .get_invalidate_req = mmhub_v9_4_get_invalidate_req,
+};
+
static void mmhub_v9_4_init(struct amdgpu_device *adev)
{
struct amdgpu_vmhub *hub[MMHUB_NUM_INSTANCES] = {
@@ -584,6 +615,7 @@ static void mmhub_v9_4_init(struct amdgpu_device *adev)
mmVML2VC0_VM_INVALIDATE_ENG0_REQ;
hub[i]->eng_addr_distance = mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
+ hub[i]->vmhub_funcs = &mmhub_v9_4_vmhub_funcs;
}
}
--
2.55.0
next prev parent reply other threads:[~2026-09-01 20:11 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-01 20:10 [PATCH V2 00/31] Rework GPU TLB invalidation Alex Deucher
2026-09-01 20:10 ` [PATCH 01/31] drm/amdgpu/gmc9: disallow gfxoff around TLB flushes Alex Deucher
2026-09-02 7:10 ` Christian König
2026-09-02 13:08 ` Alex Deucher
2026-09-02 13:10 ` Alex Deucher
2026-09-01 20:10 ` [PATCH 02/31] drm/amdgpu/gmc10: " Alex Deucher
2026-09-01 20:10 ` [PATCH 03/31] drm/amdgpu/gmc11: " Alex Deucher
2026-09-01 20:10 ` [PATCH 04/31] drm/amdgpu/gmc12: " Alex Deucher
2026-09-01 20:10 ` Alex Deucher [this message]
2026-09-01 20:10 ` [PATCH 06/31] drm/amdgpu: add a gmc flag for using MMIO for TLB flush Alex Deucher
2026-09-01 20:10 ` [PATCH 07/31] drm/amdgpu/gmc9: use MMIO for TLB flushes Alex Deucher
2026-09-01 20:10 ` [PATCH 08/31] drm/amdgpu/gmc10: " Alex Deucher
2026-09-01 20:10 ` [PATCH 09/31] drm/amdgpu/gmc11: " Alex Deucher
2026-09-01 20:10 ` [PATCH 10/31] drm/amdgpu/gmc12: " Alex Deucher
2026-09-01 20:10 ` [PATCH 11/31] drm/amdgpu: add a buffer funcs callback for TLB invalidation Alex Deucher
2026-09-01 20:10 ` [PATCH 12/31] drm/amdgpu/sdma5.0: add tlb invalidation buffer func callback Alex Deucher
2026-09-01 20:10 ` [PATCH 13/31] drm/amdgpu/sdma5.2: " Alex Deucher
2026-09-01 20:10 ` [PATCH 14/31] drm/amdgpu/sdma6: " Alex Deucher
2026-09-01 20:10 ` [PATCH 15/31] drm/amdgpu/sdma7: " Alex Deucher
2026-09-01 20:10 ` [PATCH 16/31] drm/amdgpu: simplify amdgpu_gmc_flush_gpu_tlb() Alex Deucher
2026-09-01 20:10 ` [PATCH 17/31] drm/amdgpu: add tlb invalidation method enum Alex Deucher
2026-09-01 20:10 ` [PATCH 18/31] drm/amdgpu: plumb tlb inv method in amdgpu_gmc_flush_gpu_tlb_gart() Alex Deucher
2026-09-01 20:10 ` [PATCH 19/31] drm/amdgpu: uplevel reset check " Alex Deucher
2026-09-01 20:10 ` [PATCH 20/31] drm/amdgpu/gmc: add new callback to lookup vmid to pasid mapping Alex Deucher
2026-09-02 6:26 ` Zhang, Jesse(Jie)
2026-09-01 20:10 ` [PATCH 21/31] drm/amdgpu: add a gmc callback for the inv semaphore Alex Deucher
2026-09-01 20:10 ` [PATCH 22/31] drm/amdgpu/gmc: rework pasid flushing Alex Deucher
2026-09-02 3:04 ` Zhang, Jesse(Jie)
2026-09-01 20:10 ` [PATCH 23/31] drm/amdgpu/gmc9: use SDMA for gart TLB invalidation Alex Deucher
2026-09-01 20:10 ` [PATCH 24/31] drm/amdgpu/gmc10: " Alex Deucher
2026-09-01 20:10 ` [PATCH 25/31] drm/amdgpu/gmc11: " Alex Deucher
2026-09-01 20:10 ` [PATCH 26/31] drm/amdgpu/gmc12: " Alex Deucher
2026-09-01 20:10 ` [PATCH 27/31] drm/amdgpu/gmc10: use SDMA for pasid " Alex Deucher
2026-09-01 20:10 ` [PATCH 28/31] drm/amdgpu/gmc11: " Alex Deucher
2026-09-01 20:10 ` [PATCH 29/31] drm/amdgpu/gmc12: use MES or " Alex Deucher
2026-09-01 20:10 ` [PATCH 30/31] drm/amdgpu/gmc12: drop MES tlb inv in gmc callbacks Alex Deucher
2026-09-01 20:10 ` [PATCH 31/31] drm/amdgpu/gmc: add helpers for various tlb inv functions Alex Deucher
2026-09-02 7:07 ` [PATCH V2 00/31] Rework GPU TLB invalidation Christian König
2026-09-02 13:06 ` Alex Deucher
2026-09-02 13:20 ` Christian König
2026-09-02 13:25 ` Alex Deucher
2026-09-02 13:38 ` Alex Deucher
2026-09-02 13:57 ` Christian König
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