From: Igor Paunovic <royalnet026@gmail.com>
To: Huseyin BIYIK <boogiepop@gmx.com>
Cc: Igor Paunovic <royalnet026@gmail.com>,
Nicolas Dufresne <nicolas@ndufresne.ca>,
Tomeu Vizoso <tomeu@tomeuvizoso.net>,
Heiko Stuebner <heiko@sntech.de>,
Jiaxing Hu <gahing@gahingwoo.com>,
Oded Gabbay <ogabbay@kernel.org>, Jonas Karlman <jonas@kwiboo.se>,
dri-devel@lists.freedesktop.org,
linux-rockchip@lists.infradead.org
Subject: Re: [RFC] accel/rocket: DVFS on RK3588 - a hardware constraint, and some numbers
Date: Thu, 3 Sep 2026 11:16:37 +0200 [thread overview]
Message-ID: <20260903091646.7183-1-royalnet026@gmail.com> (raw)
In-Reply-To: <20260902110432.22069-1-royalnet026@gmail.com>
Yesterday I wrote:
> My next step is to cherry-pick that commit into my BL31: if EL3
> also reads zero, the silicon answer wins.
Done this morning, and the answer is in: the firewall wins, and
Huseyin called it right.
Setup: d2d6928641ba cherry-picked onto the upstream TF-A v2.12 my
board runs (banner v2.12.0-10-g70d814213 verified over UART after
flashing). With that BL31, clk_get_rate() goes through EL3 reading
the PVTPLL status words directly.
NPU, from EL3: NPUGRF+0x24 reads a real value. clk_get_rate()
returns exactly 1000000000 at the 1 GHz OPP and exactly 700000000
at 700 MHz. At the same moment, the same register read from a
kernel module (EL1) still returns 0x00000000. Same register, same
instant: secure world sees the counter, non-secure gets zeros.
So the counter is alive in silicon, and yesterday's dead end was
the per-ip-core access restriction you suspected - not a missing
clock and not an unbonded counter.
GPU, from EL3, as cross-check under glmark2 load: five consecutive
reads gave 1048, 1053, 1047, 1054, 1049 MHz at the 1000 MHz OPP -
live jitter, matching the 1042 I measured from userspace mmap
yesterday. So EL3 reports raw measurements, which makes the NPU
result the more interesting one:
The NPU PVTPLL apparently LOCKS to its target (readback == nominal
to the MHz, at two operating points), while the GPU one free-runs
about 5% above nominal. Same register layout, same CON2 contents
as far as I can see - do you know what makes the two instances
behave differently?
Practical upshot for this series: with your TF-A commit in BL31,
plain clk_get_rate() gives the kernel measured rates with no GRF
access from the non-secure side at all. That is the clean
telemetry path for rocket DVFS, and one more reason your commit
earns its keep on RK3588.
One honest gap: I could not yet take the voltage-vs-frequency
curve (my devfreq module holds the NPU rail at 850 mV as a
regulator consumer, so undervolting from a second consumer is
refused). Future work.
Igor
WARNING: multiple messages have this Message-ID (diff)
From: Igor Paunovic <royalnet026@gmail.com>
To: Huseyin BIYIK <boogiepop@gmx.com>
Cc: Igor Paunovic <royalnet026@gmail.com>,
Nicolas Dufresne <nicolas@ndufresne.ca>,
Tomeu Vizoso <tomeu@tomeuvizoso.net>,
Heiko Stuebner <heiko@sntech.de>,
Jiaxing Hu <gahing@gahingwoo.com>,
Oded Gabbay <ogabbay@kernel.org>, Jonas Karlman <jonas@kwiboo.se>,
dri-devel@lists.freedesktop.org,
linux-rockchip@lists.infradead.org
Subject: Re: [RFC] accel/rocket: DVFS on RK3588 - a hardware constraint, and some numbers
Date: Thu, 3 Sep 2026 11:16:37 +0200 [thread overview]
Message-ID: <20260903091646.7183-1-royalnet026@gmail.com> (raw)
In-Reply-To: <20260902110432.22069-1-royalnet026@gmail.com>
Yesterday I wrote:
> My next step is to cherry-pick that commit into my BL31: if EL3
> also reads zero, the silicon answer wins.
Done this morning, and the answer is in: the firewall wins, and
Huseyin called it right.
Setup: d2d6928641ba cherry-picked onto the upstream TF-A v2.12 my
board runs (banner v2.12.0-10-g70d814213 verified over UART after
flashing). With that BL31, clk_get_rate() goes through EL3 reading
the PVTPLL status words directly.
NPU, from EL3: NPUGRF+0x24 reads a real value. clk_get_rate()
returns exactly 1000000000 at the 1 GHz OPP and exactly 700000000
at 700 MHz. At the same moment, the same register read from a
kernel module (EL1) still returns 0x00000000. Same register, same
instant: secure world sees the counter, non-secure gets zeros.
So the counter is alive in silicon, and yesterday's dead end was
the per-ip-core access restriction you suspected - not a missing
clock and not an unbonded counter.
GPU, from EL3, as cross-check under glmark2 load: five consecutive
reads gave 1048, 1053, 1047, 1054, 1049 MHz at the 1000 MHz OPP -
live jitter, matching the 1042 I measured from userspace mmap
yesterday. So EL3 reports raw measurements, which makes the NPU
result the more interesting one:
The NPU PVTPLL apparently LOCKS to its target (readback == nominal
to the MHz, at two operating points), while the GPU one free-runs
about 5% above nominal. Same register layout, same CON2 contents
as far as I can see - do you know what makes the two instances
behave differently?
Practical upshot for this series: with your TF-A commit in BL31,
plain clk_get_rate() gives the kernel measured rates with no GRF
access from the non-secure side at all. That is the clean
telemetry path for rocket DVFS, and one more reason your commit
earns its keep on RK3588.
One honest gap: I could not yet take the voltage-vs-frequency
curve (my devfreq module holds the NPU rail at 850 mV as a
regulator consumer, so undervolting from a second consumer is
refused). Future work.
Igor
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Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
next prev parent reply other threads:[~2026-09-03 9:17 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-01 13:16 [RFC] accel/rocket: DVFS on RK3588 - a hardware constraint, and some numbers Igor Paunovic
2026-08-01 13:16 ` Igor Paunovic
2026-08-01 19:32 ` Jiaxing Hu
2026-08-01 19:32 ` Jiaxing Hu
2026-08-02 12:04 ` Igor Paunovic
2026-08-02 12:04 ` Igor Paunovic
2026-08-15 18:24 ` Tomeu Vizoso
2026-08-15 18:24 ` Tomeu Vizoso
2026-08-17 18:22 ` Nicolas Dufresne
2026-08-17 18:22 ` Nicolas Dufresne
2026-08-18 7:27 ` Igor Paunovic
2026-08-18 7:27 ` Igor Paunovic
2026-08-18 12:12 ` Jonas Karlman
2026-08-18 12:12 ` Jonas Karlman
2026-08-18 12:30 ` Jonas Karlman
2026-08-18 12:30 ` Jonas Karlman
2026-08-19 5:52 ` Igor Paunovic
2026-08-19 5:52 ` Igor Paunovic
2026-08-19 9:40 ` Jonas Karlman
2026-08-19 9:40 ` Jonas Karlman
2026-08-19 12:59 ` Igor Paunovic
2026-08-19 12:59 ` Igor Paunovic
2026-08-19 16:20 ` Jonas Karlman
2026-08-19 16:20 ` Jonas Karlman
2026-08-19 18:48 ` Igor Paunovic
2026-08-19 18:48 ` Igor Paunovic
2026-08-19 20:07 ` Hüseyin BIYIK
2026-08-19 20:07 ` Hüseyin BIYIK
2026-09-02 11:04 ` Igor Paunovic
2026-09-02 11:04 ` Igor Paunovic
2026-09-03 9:16 ` Igor Paunovic [this message]
2026-09-03 9:16 ` Igor Paunovic
[not found] ` <2f88072c-6aa3-4294-a35d-722d1c7a405c@email.android.com>
2026-09-03 18:51 ` Igor Paunovic
2026-09-03 18:51 ` Igor Paunovic
2026-09-04 11:08 ` Jiaxing Hu
2026-09-04 11:08 ` Jiaxing Hu
2026-09-04 12:46 ` Igor Paunovic
2026-09-04 12:46 ` Igor Paunovic
2026-09-05 5:13 ` Jiaxing Hu
2026-09-05 5:13 ` Jiaxing Hu
2026-09-05 7:01 ` Igor Paunovic
2026-09-05 7:01 ` Igor Paunovic
2026-08-19 18:47 ` Nicolas Dufresne
2026-08-19 18:47 ` Nicolas Dufresne
2026-09-04 11:19 ` Jiaxing Hu
2026-09-04 11:19 ` Jiaxing Hu
[not found] <DKDOBW9CJ2Y3.10EEIZDTXPYJZ@cknow-tech.com>
2026-08-01 14:40 ` Igor Paunovic
2026-08-01 14:40 ` Igor Paunovic
2026-08-01 16:29 ` Diederik de Haas
2026-08-01 16:29 ` Diederik de Haas
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