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From: "Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Subject: [PULL 39/51] target-info: remove machine_typename
Date: Thu,  3 Sep 2026 12:39:23 +0200	[thread overview]
Message-ID: <20260903103936.62355-40-philmd@oss.qualcomm.com> (raw)
In-Reply-To: <20260903103936.62355-1-philmd@oss.qualcomm.com>

From: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>

This field is now unused, so we can remove it.

Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20260901202043.26532-5-pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
 include/qemu/target-info-impl.h   | 2 --
 include/qemu/target-info.h        | 8 --------
 configs/targets/aarch64-softmmu.c | 1 -
 configs/targets/arm-softmmu.c     | 1 -
 configs/targets/riscv32-softmmu.c | 1 -
 configs/targets/riscv64-softmmu.c | 1 -
 target-info-stub.c                | 1 -
 target-info.c                     | 5 -----
 8 files changed, 20 deletions(-)

diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-info-impl.h
index c917d546eab..cf42aabbc8b 100644
--- a/include/qemu/target-info-impl.h
+++ b/include/qemu/target-info-impl.h
@@ -21,8 +21,6 @@ typedef struct TargetInfo {
     unsigned long_bits;
     /* runtime equivalent of CPU_RESOLVING_TYPE definition */
     const char *cpu_type;
-    /* QOM typename machines for this binary must implement */
-    const char *machine_typename;
     /* related to TARGET_BIG_ENDIAN definition */
     EndianMode endianness;
     /*
diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h
index 6c5b714288e..b23e5bc5865 100644
--- a/include/qemu/target-info.h
+++ b/include/qemu/target-info.h
@@ -23,14 +23,6 @@ const char *target_name(void);
  */
 unsigned target_long_bits(void);
 
-/**
- * target_machine_typename:
- *
- * Returns: Name of the QOM interface implemented by machines
- *          usable on this target binary.
- */
-const char *target_machine_typename(void);
-
 /**
  * target_cpu_type:
  *
diff --git a/configs/targets/aarch64-softmmu.c b/configs/targets/aarch64-softmmu.c
index 75d95b0e743..2200a4f19e9 100644
--- a/configs/targets/aarch64-softmmu.c
+++ b/configs/targets/aarch64-softmmu.c
@@ -18,7 +18,6 @@ static const TargetInfo target_info_aarch64_system = {
     .target_arch = SYS_EMU_TARGET_AARCH64,
     .long_bits = 64,
     .cpu_type = TYPE_ARM_CPU,
-    .machine_typename = TYPE_TARGET_AARCH64_MACHINE,
     .endianness = ENDIAN_MODE_LITTLE,
     .page_bits_vary = true,
     .page_bits_init = TARGET_PAGE_BITS_LEGACY,
diff --git a/configs/targets/arm-softmmu.c b/configs/targets/arm-softmmu.c
index 73546fa5737..9d558a0c1a1 100644
--- a/configs/targets/arm-softmmu.c
+++ b/configs/targets/arm-softmmu.c
@@ -18,7 +18,6 @@ static const TargetInfo target_info_arm_system = {
     .target_arch = SYS_EMU_TARGET_ARM,
     .long_bits = 32,
     .cpu_type = TYPE_ARM_CPU,
-    .machine_typename = TYPE_TARGET_ARM_MACHINE,
     .endianness = ENDIAN_MODE_LITTLE,
     .page_bits_vary = true,
     .page_bits_init = TARGET_PAGE_BITS_LEGACY,
diff --git a/configs/targets/riscv32-softmmu.c b/configs/targets/riscv32-softmmu.c
index 752c813077e..c1d94679c7e 100644
--- a/configs/targets/riscv32-softmmu.c
+++ b/configs/targets/riscv32-softmmu.c
@@ -18,7 +18,6 @@ static const TargetInfo target_info_riscv32_system = {
     .target_arch = SYS_EMU_TARGET_RISCV32,
     .long_bits = 32,
     .cpu_type = TYPE_RISCV_CPU,
-    .machine_typename = TYPE_TARGET_RISCV32_MACHINE,
     .endianness = ENDIAN_MODE_LITTLE,
     .page_bits_init = TARGET_PAGE_BITS,
 };
diff --git a/configs/targets/riscv64-softmmu.c b/configs/targets/riscv64-softmmu.c
index 5150f0fe9d9..f648a5c8944 100644
--- a/configs/targets/riscv64-softmmu.c
+++ b/configs/targets/riscv64-softmmu.c
@@ -18,7 +18,6 @@ static const TargetInfo target_info_riscv64_system = {
     .target_arch = SYS_EMU_TARGET_RISCV64,
     .long_bits = 64,
     .cpu_type = TYPE_RISCV_CPU,
-    .machine_typename = TYPE_TARGET_RISCV64_MACHINE,
     .endianness = ENDIAN_MODE_LITTLE,
     .page_bits_init = TARGET_PAGE_BITS,
 };
diff --git a/target-info-stub.c b/target-info-stub.c
index 22b7911201c..d121b8c0170 100644
--- a/target-info-stub.c
+++ b/target-info-stub.c
@@ -29,7 +29,6 @@ static const TargetInfo target_info_stub = {
     .target_arch = glue(SYS_EMU_TARGET_, TARGET_ARCH),
     .long_bits = TARGET_LONG_BITS,
     .cpu_type = CPU_RESOLVING_TYPE,
-    .machine_typename = TYPE_MACHINE,
     .endianness = TARGET_BIG_ENDIAN ? ENDIAN_MODE_BIG : ENDIAN_MODE_LITTLE,
 #ifdef TARGET_PAGE_BITS_VARY
     .page_bits_vary = true,
diff --git a/target-info.c b/target-info.c
index 04c69c41f8a..012b384036d 100644
--- a/target-info.c
+++ b/target-info.c
@@ -32,11 +32,6 @@ const char *target_cpu_type(void)
     return target_info()->cpu_type;
 }
 
-const char *target_machine_typename(void)
-{
-    return target_info()->machine_typename;
-}
-
 EndianMode target_endian_mode(void)
 {
     return target_info()->endianness;
-- 
2.53.0



  parent reply	other threads:[~2026-09-03 10:44 UTC|newest]

Thread overview: 53+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 01/51] hw/sd: give the RPMB vmstate subsection a name of its own Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 02/51] hw/sd: sdhci: Fix SDMA boundary bug Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 03/51] qtest: add xilinx-zynq SDHCI sdma test Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 04/51] hw/sd: sdhci: Migrate the Host Control 2 register Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 05/51] hw/sd: sdhci: Accept version 4 enable without UHS-I Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 06/51] hw/sd: sdhci: Factor sdhci_advance_sdma_address() helper out Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 07/51] hw/sd: sdhci: Factor sdhci_sdma_address() " Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 08/51] hw/sd: sdhci: Use version 4 system address for SDMA Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 09/51] hw/sd: sdhci: Support version 4 ADMA 64-bit addressing Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 10/51] hw/sd: sdhci: Resume version 4 SDMA at buffer boundaries Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 11/51] hw/sd/sdcard: Register device ops in drives without media Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 12/51] hw/cxl: fix timer leak in cxl_destroy_cci() Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 13/51] hw/sd/axiado_sdhci: Add header guard Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 14/51] MAINTAINERS: Cover pflash QTest in pflash section Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 15/51] hw/block/pflash_cfi01: Always set romd mode when clearing wcycle and cmd Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 16/51] hw/block/pflash_cfi02: Add migration support Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 17/51] accel/tcg: Rename for exception codes named @ret as @excp Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 18/51] accel/tcg: Restrict EXCP_HALTED handling to system emulation Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 19/51] accel/tcg: Check %halted field in cpu_handle_halt() caller Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 20/51] target/i386: Remove const qualifier in ptw_setl*() Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 21/51] linux-user: Uncast void pointer argument as Object in target_cpu_free() Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 22/51] cpus: Add const-qualified CPU environment accessors Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 23/51] linux-user: Replace env_cpu_const() by generic env_cpu() equivalent Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 24/51] system/cpus: Constify various CPUState arguments Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 25/51] target/avr: Constify CPUAVRState for some cpu_*() getters Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 26/51] target/hexagon: Constify CPUHexagonState in hexagon_thread_is_enabled() Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 27/51] target/i386: Constify CPU*State for cpu_*_interrupt() getters Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 28/51] target/loongarch: Constify LoongArchTLB Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 29/51] target/mips: Constify CPUMIPSState for various cpu_*() getters Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 30/51] target/s390x: Constify S390CPU for cpu_has_*() getters Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 31/51] target/riscv: Constify @iprio argument in riscv_cpu_pending_to_irq() Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 32/51] target/sparc: Constify CPUSPARCState for various cpu_*() getters Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 33/51] target/tricore: Document architectural interrupts as not implemented Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 34/51] target/xtensa: Constify CPUXtensaState in xtensa_replicate_windowstart() Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 35/51] target/arm: Return immediately on error in kvm_arch_init() Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 36/51] qom/object: add is_available callback to TypeInfo Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 37/51] hw/arm: filter minimal set of machines Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 38/51] system: query machines using TYPE_MACHINE Philippe Mathieu-Daudé
2026-09-03 10:39 ` Philippe Mathieu-Daudé [this message]
2026-09-03 10:39 ` [PULL 40/51] hw/arm: remove TYPE_TARGET_{AARCH64,ARM}_MACHINE Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 41/51] hw/arm: remove {arm, arm_aarch64, aarch64}_machine_interfaces Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 42/51] hw/arm: remove DEFINE_MACHINE_{AARCH64,ARM} Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 43/51] hw/arm: remove machines-qom.h Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 44/51] hw/riscv: remove TYPE_TARGET_{RISCV32,RISCV64}_MACHINE Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 45/51] hw/riscv: remove {riscv32, riscv32_64, riscv64}_machine_interfaces Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 46/51] hw/riscv: remove DEFINE_MACHINE_{RISCV32,RISCV64} Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 47/51] hw/riscv: remove machines-qom.h Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 48/51] rustfmt: disable wrap_comments Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 49/51] system: improve -mon deprecation warning Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 50/51] MAINTAINERS: Stop reviewing meson-related patches Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 51/51] MAINTAINERS: Update PhilMD's email address Philippe Mathieu-Daudé
2026-09-03 19:15 ` [PULL 00/51] Misc HW/accel patches for 2026-09-03 Peter Maydell

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