Re: [PATCH] drm/msm/dsi: Fix setting completely bogus rate for byte clock

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Reverting commit 6cd33b6f4155 directly reintroduces a panel scanout glitch on MSM8916 and similar older platforms during runtime DCS commands.
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commit bc484ede914d3152ef2331cbb6fea324d910f6be
Author: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

drm/msm/dsi: Fix setting completely bogus rate for byte clock

This commit reverts 6cd33b6f4155 ("drm/msm/dsi: round 6G byte clock rate to
the PLL-achievable value") because the rounding of the byte clock rate broke
DSI display initialization on newer devices like Eliza. It removes the
clk_round_rate() call that modified msm_host->byte_clk_rate.

> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 7e4e3718b536c..78e6436a92b21 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -669,24 +669,12 @@ static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
>  
>  int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
>  {
[ ... ]
>  	dsi_calc_pclk(msm_host, is_bonded_dsi);
> -
> -	rounded_byte_clk_rate = clk_round_rate(msm_host->byte_clk,
> -					       msm_host->byte_clk_rate);
> -	if (rounded_byte_clk_rate < 0) {
> -		pr_err("%s: failed to round byte clock rate, %ld\n",
> -		       __func__, rounded_byte_clk_rate);
> -		return rounded_byte_clk_rate;
> -	}
> -
> -	msm_host->byte_clk_rate = rounded_byte_clk_rate;
>  	msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);

[Severity: High]
Does removing clk_round_rate() reintroduce panel scanout glitches on older
platforms like MSM8916 during runtime DCS commands?

Without rounding the byte clock rate up front, the ideal rate computed by
dsi_calc_pclk() is retained in msm_host->byte_clk_rate. 

When link_clk_set_rate() is called later with this ideal rate, it appears the
clock framework detects a discrepancy with the actual PLL rate, which then
forces the PHY PLL to unnecessarily re-lock. This re-lock visually corrupts
the display scanout and causes the panel to lose pixel lock whenever runtime
commands (like backlight writes) are sent.

While this revert fixes the initialization on newer platforms where the
clock is not yet properly parented at this stage, it seems to reintroduce
the regression on older platforms that the original commit specifically
addressed. Is there a way to apply this workaround only for newer hardware,
or ensure the clock is parented properly before calling clk_round_rate()?

>  	return 0;
>  }

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Sashiko AI review · https://sashiko.dev/#/patchset/20260903104732.145353-2-krzysztof.kozlowski@oss.qualcomm.com?part=1