[PATCH] drm/msm/dsi: Fix setting completely bogus rate for byte clock

[PATCH] drm/msm/dsi: Fix setting completely bogus rate for byte clock

[Krzysztof Kozlowski]

Revert commit 6cd33b6f4155 ("drm/msm/dsi: round 6G byte clock rate to
the PLL-achievable value") because it is absolutely untested on newer
hardware and obviously wrong: it rounds the byte clock when the byte
clock is not parented properly, so the rounded rate (used later to
actually set byte clock rate) is 19.2 MHz.

This broke DSI display on Eliza and probably SM8750, Kaanapali and many
other new devices:

[    3.164727] dsi_link_clk_set_rate_6g: Failed to set rate pixel clk, -22
[    3.164729] msm_dsi_host_power_on: failed to enable link clocks. ret=-22
[    3.164733] dsi_mgr_bridge_power_on: power on host 0 failed, -22
[    3.164760] msm_dsi ae94000.dsi: Power on failed: -22

Fixes: 6cd33b6f4155 ("drm/msm/dsi: round 6G byte clock rate to the PLL-achievable value")
Cc: stable@vger.kernel.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
 drivers/gpu/drm/msm/dsi/dsi_host.c | 12 ------------
 1 file changed, 12 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 7e4e3718b536..78e6436a92b2 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -669,24 +669,12 @@ static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
 
 int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
 {
-	long rounded_byte_clk_rate;
-
 	if (!msm_host->mode) {
 		pr_err("%s: mode not set\n", __func__);
 		return -EINVAL;
 	}
 
 	dsi_calc_pclk(msm_host, is_bonded_dsi);
-
-	rounded_byte_clk_rate = clk_round_rate(msm_host->byte_clk,
-					       msm_host->byte_clk_rate);
-	if (rounded_byte_clk_rate < 0) {
-		pr_err("%s: failed to round byte clock rate, %ld\n",
-		       __func__, rounded_byte_clk_rate);
-		return rounded_byte_clk_rate;
-	}
-
-	msm_host->byte_clk_rate = rounded_byte_clk_rate;
 	msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);
 	return 0;
 }
-- 
2.53.0

Re: [PATCH] drm/msm/dsi: Fix setting completely bogus rate for byte clock

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Reverting commit 6cd33b6f4155 directly reintroduces a panel scanout glitch on MSM8916 and similar older platforms during runtime DCS commands.
--

commit bc484ede914d3152ef2331cbb6fea324d910f6be
Author: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

drm/msm/dsi: Fix setting completely bogus rate for byte clock

This commit reverts 6cd33b6f4155 ("drm/msm/dsi: round 6G byte clock rate to
the PLL-achievable value") because the rounding of the byte clock rate broke
DSI display initialization on newer devices like Eliza. It removes the
clk_round_rate() call that modified msm_host->byte_clk_rate.

> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 7e4e3718b536c..78e6436a92b21 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -669,24 +669,12 @@ static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
>  
>  int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
>  {
[ ... ]
>  	dsi_calc_pclk(msm_host, is_bonded_dsi);
> -
> -	rounded_byte_clk_rate = clk_round_rate(msm_host->byte_clk,
> -					       msm_host->byte_clk_rate);
> -	if (rounded_byte_clk_rate < 0) {
> -		pr_err("%s: failed to round byte clock rate, %ld\n",
> -		       __func__, rounded_byte_clk_rate);
> -		return rounded_byte_clk_rate;
> -	}
> -
> -	msm_host->byte_clk_rate = rounded_byte_clk_rate;
>  	msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);

[Severity: High]
Does removing clk_round_rate() reintroduce panel scanout glitches on older
platforms like MSM8916 during runtime DCS commands?

Without rounding the byte clock rate up front, the ideal rate computed by
dsi_calc_pclk() is retained in msm_host->byte_clk_rate. 

When link_clk_set_rate() is called later with this ideal rate, it appears the
clock framework detects a discrepancy with the actual PLL rate, which then
forces the PHY PLL to unnecessarily re-lock. This re-lock visually corrupts
the display scanout and causes the panel to lose pixel lock whenever runtime
commands (like backlight writes) are sent.

While this revert fixes the initialization on newer platforms where the
clock is not yet properly parented at this stage, it seems to reintroduce
the regression on older platforms that the original commit specifically
addressed. Is there a way to apply this workaround only for newer hardware,
or ensure the clock is parented properly before calling clk_round_rate()?

>  	return 0;
>  }

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260903104732.145353-2-krzysztof.kozlowski@oss.qualcomm.com?part=1

Re: [PATCH] drm/msm/dsi: Fix setting completely bogus rate for byte clock

[Krzysztof Kozlowski]

On 03/09/2026 12:52, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [High] Reverting commit 6cd33b6f4155 directly reintroduces a panel scanout glitch on MSM8916 and similar older platforms during runtime DCS commands.

Obviously. The problem should be fixed other way, not by introducing
incorrect clock rate rounding breaking other platforms.

That commit introduced regression so it gets reverted till authors come
with proper solution, for example.


Best regards,
Krzysztof

Re: [PATCH] drm/msm/dsi: Fix setting completely bogus rate for byte clock

[Krzysztof Kozlowski]

On 03/09/2026 12:47, Krzysztof Kozlowski wrote:
> Revert commit 6cd33b6f4155 ("drm/msm/dsi: round 6G byte clock rate to
> the PLL-achievable value") because it is absolutely untested on newer
> hardware and obviously wrong: it rounds the byte clock when the byte
> clock is not parented properly, so the rounded rate (used later to
> actually set byte clock rate) is 19.2 MHz.
> 
> This broke DSI display on Eliza and probably SM8750, Kaanapali and many
> other new devices:
> 
> [    3.164727] dsi_link_clk_set_rate_6g: Failed to set rate pixel clk, -22
> [    3.164729] msm_dsi_host_power_on: failed to enable link clocks. ret=-22
> [    3.164733] dsi_mgr_bridge_power_on: power on host 0 failed, -22
> [    3.164760] msm_dsi ae94000.dsi: Power on failed: -22
> 
> Fixes: 6cd33b6f4155 ("drm/msm/dsi: round 6G byte clock rate to the PLL-achievable value")
> Cc: stable@vger.kernel.org

Actually this was pointed out to me, so:

Reported-by: Abel Vesa <abel.vesa@oss.qualcomm.com>


Best regards,
Krzysztof

Re: [PATCH] drm/msm/dsi: Fix setting completely bogus rate for byte clock

[Dmitry Baryshkov]

On Thu, Sep 03, 2026 at 01:02:57PM +0200, Krzysztof Kozlowski wrote:
> On 03/09/2026 12:52, sashiko-bot@kernel.org wrote:
> > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> > - [High] Reverting commit 6cd33b6f4155 directly reintroduces a panel scanout glitch on MSM8916 and similar older platforms during runtime DCS commands.
> 
> Obviously. The problem should be fixed other way, not by introducing
> incorrect clock rate rounding breaking other platforms.
> 
> That commit introduced regression so it gets reverted till authors come
> with proper solution, for example.

Fixed by
http://lore.kernel.org/dri-devel/20260903-fix-eliza-dsi-v1-1-3474a6c9f2e0@oss.qualcomm.com

-- 
With best wishes
Dmitry