From: Bruce Richardson <bruce.richardson@intel.com>
To: dev@dpdk.org
Cc: Bruce Richardson <bruce.richardson@intel.com>,
Anatoly Burakov <anatoly.burakov@intel.com>
Subject: [PATCH 13/13] net/ice: enable context desc offloads for vector Tx
Date: Thu, 3 Sep 2026 18:04:21 +0100 [thread overview]
Message-ID: <20260903170421.361293-1-bruce.richardson@intel.com> (raw)
In-Reply-To: <20260903170140.360477-1-bruce.richardson@intel.com>
Use the context descriptor Tx vector paths from intel/common in ice
driver to enable more offloads on the vector path for ice driver.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
doc/guides/rel_notes/release_26_11.rst | 6 ++++
drivers/net/intel/ice/ice_ethdev.h | 3 ++
drivers/net/intel/ice/ice_rxtx.c | 31 ++++++++++++++++++---
drivers/net/intel/ice/ice_rxtx.h | 11 ++++++++
drivers/net/intel/ice/ice_rxtx_vec_avx2.c | 24 ++++++++++++++++
drivers/net/intel/ice/ice_rxtx_vec_avx512.c | 24 ++++++++++++++++
6 files changed, 95 insertions(+), 4 deletions(-)
diff --git a/doc/guides/rel_notes/release_26_11.rst b/doc/guides/rel_notes/release_26_11.rst
index 907f9013ff..47eccd9401 100644
--- a/doc/guides/rel_notes/release_26_11.rst
+++ b/doc/guides/rel_notes/release_26_11.rst
@@ -64,6 +64,12 @@ New Features
* Renamed the ``enable_ptype_lldp`` devarg to ``enable_lldp``.
The old name is no longer accepted.
+* **Updated Intel ice driver.**
+
+ * Added Tx context descriptor support to the AVX2 and AVX512 vector Tx
+ paths, enabling QinQ tag insertion and outer IPv4/UDP checksum
+ offloads on those paths.
+
Removed Items
-------------
diff --git a/drivers/net/intel/ice/ice_ethdev.h b/drivers/net/intel/ice/ice_ethdev.h
index 7ee3ea8a70..d357181a2a 100644
--- a/drivers/net/intel/ice/ice_ethdev.h
+++ b/drivers/net/intel/ice/ice_ethdev.h
@@ -213,8 +213,10 @@ enum ice_tx_func_type {
ICE_TX_SIMPLE,
ICE_TX_AVX2,
ICE_TX_AVX2_OFFLOAD,
+ ICE_TX_AVX2_CTX_OFFLOAD,
ICE_TX_AVX512,
ICE_TX_AVX512_OFFLOAD,
+ ICE_TX_AVX512_CTX_OFFLOAD,
ICE_TX_NEON,
};
@@ -673,6 +675,7 @@ struct ice_adapter {
bool rx_bulk_alloc_allowed;
bool tx_vec_allowed;
bool tx_simple_allowed;
+ bool use_ctx;
enum ice_rx_func_type rx_func_type;
enum ice_tx_func_type tx_func_type;
/* ptype mapping table */
diff --git a/drivers/net/intel/ice/ice_rxtx.c b/drivers/net/intel/ice/ice_rxtx.c
index 313cbd25d5..c6a464b2c1 100644
--- a/drivers/net/intel/ice/ice_rxtx.c
+++ b/drivers/net/intel/ice/ice_rxtx.c
@@ -883,6 +883,7 @@ ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
/* record what kind of descriptor cleanup we need on teardown */
txq->use_vec_entry = ad->tx_vec_allowed || ad->tx_simple_allowed;
+ txq->use_ctx = ad->use_ctx;
if (txq->tsq != NULL && txq->tsq->ts_flag > 0) {
struct ice_aqc_set_txtime_qgrp *ts_elem;
@@ -1193,7 +1194,7 @@ ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
return -EINVAL;
}
- ci_txq_release_all_mbufs(txq, false);
+ ci_txq_release_all_mbufs(txq, txq->use_ctx);
ice_reset_tx_queue(txq);
dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
@@ -1256,7 +1257,7 @@ ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
return -EINVAL;
}
- ci_txq_release_all_mbufs(txq, false);
+ ci_txq_release_all_mbufs(txq, txq->use_ctx);
txq->qtx_tail = NULL;
return 0;
@@ -1744,7 +1745,7 @@ ice_tx_queue_release(void *txq)
return;
}
- ci_txq_release_all_mbufs(q, false);
+ ci_txq_release_all_mbufs(q, q->use_ctx);
rte_free(q->sw_ring);
rte_free(q->rs_last_id);
if (q->tsq) {
@@ -3526,7 +3527,8 @@ static const struct ci_tx_path_info ice_tx_path_infos[] = {
.features = {
.tx_offloads = ICE_TX_SCALAR_OFFLOADS
},
- .pkt_prep = ice_prep_pkts
+ .pkt_prep = ice_prep_pkts,
+ .supports_ctx = true
},
[ICE_TX_SIMPLE] = {
.pkt_burst = ice_xmit_pkts_simple,
@@ -3556,6 +3558,16 @@ static const struct ci_tx_path_info ice_tx_path_infos[] = {
},
.pkt_prep = ice_prep_pkts
},
+ [ICE_TX_AVX2_CTX_OFFLOAD] = {
+ .pkt_burst = ice_xmit_pkts_vec_avx2_ctx_offload,
+ .info = "Offload Vector AVX2 Ctx",
+ .features = {
+ .tx_offloads = ICE_TX_VECTOR_CTX_OFFLOAD_OFFLOADS,
+ .simd_width = RTE_VECT_SIMD_256
+ },
+ .pkt_prep = ice_prep_pkts,
+ .supports_ctx = true
+ },
#ifdef CC_AVX512_SUPPORT
[ICE_TX_AVX512] = {
.pkt_burst = ice_xmit_pkts_vec_avx512,
@@ -3575,6 +3587,16 @@ static const struct ci_tx_path_info ice_tx_path_infos[] = {
},
.pkt_prep = ice_prep_pkts
},
+ [ICE_TX_AVX512_CTX_OFFLOAD] = {
+ .pkt_burst = ice_xmit_pkts_vec_avx512_ctx_offload,
+ .info = "Offload Vector AVX512 Ctx",
+ .features = {
+ .tx_offloads = ICE_TX_VECTOR_CTX_OFFLOAD_OFFLOADS,
+ .simd_width = RTE_VECT_SIMD_512
+ },
+ .pkt_prep = ice_prep_pkts,
+ .supports_ctx = true
+ },
#endif
#elif defined(RTE_ARCH_ARM64)
[ICE_TX_NEON] = {
@@ -3788,6 +3810,7 @@ ice_set_tx_function(struct rte_eth_dev *dev)
ad->tx_vec_allowed =
(ice_tx_path_infos[ad->tx_func_type].features.simd_width >= RTE_VECT_SIMD_128);
#endif
+ ad->use_ctx = ice_tx_path_infos[ad->tx_func_type].supports_ctx;
dev->tx_pkt_burst = mbuf_check ? ice_xmit_pkts_check :
ice_tx_path_infos[ad->tx_func_type].pkt_burst;
diff --git a/drivers/net/intel/ice/ice_rxtx.h b/drivers/net/intel/ice/ice_rxtx.h
index 999b6b30d6..bee8a464f5 100644
--- a/drivers/net/intel/ice/ice_rxtx.h
+++ b/drivers/net/intel/ice/ice_rxtx.h
@@ -135,6 +135,12 @@
RTE_ETH_TX_OFFLOAD_UDP_CKSUM | \
RTE_ETH_TX_OFFLOAD_TCP_CKSUM | \
RTE_ETH_TX_OFFLOAD_SCTP_CKSUM)
+/* vector ctx offload path: QinQ outer tag + outer/tunnel checksum via ctx desc */
+#define ICE_TX_VECTOR_CTX_OFFLOAD_OFFLOADS ( \
+ ICE_TX_VECTOR_OFFLOAD_OFFLOADS | \
+ RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
+ RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM | \
+ RTE_ETH_TX_OFFLOAD_QINQ_INSERT)
/* Max header size can be 2K - 64 bytes */
#define ICE_RX_HDR_BUF_SIZE (2048 - 64)
@@ -284,6 +290,8 @@ uint16_t ice_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
uint16_t nb_pkts);
uint16_t ice_xmit_pkts_vec_avx2_offload(void *tx_queue, struct rte_mbuf **tx_pkts,
uint16_t nb_pkts);
+uint16_t ice_xmit_pkts_vec_avx2_ctx_offload(void *tx_queue, struct rte_mbuf **tx_pkts,
+ uint16_t nb_pkts);
uint16_t ice_recv_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
uint16_t nb_pkts);
uint16_t ice_recv_pkts_vec_avx512_offload(void *rx_queue,
@@ -300,6 +308,9 @@ uint16_t ice_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
uint16_t ice_xmit_pkts_vec_avx512_offload(void *tx_queue,
struct rte_mbuf **tx_pkts,
uint16_t nb_pkts);
+uint16_t ice_xmit_pkts_vec_avx512_ctx_offload(void *tx_queue,
+ struct rte_mbuf **tx_pkts,
+ uint16_t nb_pkts);
int ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc);
int ice_tx_done_cleanup(void *txq, uint32_t free_cnt);
int ice_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc);
diff --git a/drivers/net/intel/ice/ice_rxtx_vec_avx2.c b/drivers/net/intel/ice/ice_rxtx_vec_avx2.c
index 00b5d51aab..056b2dc49b 100644
--- a/drivers/net/intel/ice/ice_rxtx_vec_avx2.c
+++ b/drivers/net/intel/ice/ice_rxtx_vec_avx2.c
@@ -810,6 +810,30 @@ ice_xmit_pkts_vec_avx2_offload(void *tx_queue, struct rte_mbuf **tx_pkts,
return ice_xmit_pkts_vec_avx2_common(tx_queue, tx_pkts, nb_pkts, true);
}
+uint16_t
+ice_xmit_pkts_vec_avx2_ctx_offload(void *tx_queue, struct rte_mbuf **tx_pkts,
+ uint16_t nb_pkts)
+{
+ uint16_t nb_tx = 0;
+ struct ci_tx_queue *txq = (struct ci_tx_queue *)tx_queue;
+
+ while (nb_pkts) {
+ uint16_t ret, num;
+
+ /* cross rs_thresh boundary is not allowed */
+ num = (uint16_t)RTE_MIN(nb_pkts << 1, txq->tx_rs_thresh);
+ num = num >> 1;
+ ret = ci_xmit_fixed_burst_vec_ctx_avx2(tx_queue, &tx_pkts[nb_tx], num,
+ true, CI_TAG_IN_DATA_DESC, CI_TAG_IN_CTX_DESC, NULL);
+ nb_tx += ret;
+ nb_pkts -= ret;
+ if (ret < num)
+ break;
+ }
+
+ return nb_tx;
+}
+
int __rte_cold
ice_rxq_vec_setup(struct ci_rx_queue *rxq)
{
diff --git a/drivers/net/intel/ice/ice_rxtx_vec_avx512.c b/drivers/net/intel/ice/ice_rxtx_vec_avx512.c
index d8ede5cb42..0548c293bb 100644
--- a/drivers/net/intel/ice/ice_rxtx_vec_avx512.c
+++ b/drivers/net/intel/ice/ice_rxtx_vec_avx512.c
@@ -882,3 +882,27 @@ ice_xmit_pkts_vec_avx512_offload(void *tx_queue, struct rte_mbuf **tx_pkts,
{
return ice_xmit_pkts_vec_avx512_common(tx_queue, tx_pkts, nb_pkts, true);
}
+
+uint16_t
+ice_xmit_pkts_vec_avx512_ctx_offload(void *tx_queue, struct rte_mbuf **tx_pkts,
+ uint16_t nb_pkts)
+{
+ uint16_t nb_tx = 0;
+ struct ci_tx_queue *txq = (struct ci_tx_queue *)tx_queue;
+
+ while (nb_pkts) {
+ uint16_t ret, num;
+
+ /* cross rs_thresh boundary is not allowed */
+ num = (uint16_t)RTE_MIN(nb_pkts << 1, txq->tx_rs_thresh);
+ num = num >> 1;
+ ret = ci_xmit_fixed_burst_vec_ctx_avx512(tx_queue, &tx_pkts[nb_tx], num,
+ true, CI_TAG_IN_DATA_DESC, CI_TAG_IN_CTX_DESC, NULL);
+ nb_tx += ret;
+ nb_pkts -= ret;
+ if (ret < num)
+ break;
+ }
+
+ return nb_tx;
+}
--
2.53.0
next prev parent reply other threads:[~2026-09-03 17:04 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-03 17:01 [PATCH 00/13] Consolidate ice and iavf vector Tx paths Bruce Richardson
2026-09-03 17:01 ` [PATCH 01/13] net/iavf: remove unnecessary alignment calls Bruce Richardson
2026-09-03 17:01 ` [PATCH 02/13] net/intel: make Tx context flag common Bruce Richardson
2026-09-03 17:01 ` [PATCH 03/13] net/iavf: use separate params for VLAN and QinQ position Bruce Richardson
2026-09-03 17:01 ` [PATCH 04/13] net/iavf: deduplicate tunnel field fill functions Bruce Richardson
2026-09-04 7:01 ` David Marchand
2026-09-03 17:01 ` [PATCH 05/13] net/intel: define common macros for tunneling bit-shifts Bruce Richardson
2026-09-03 17:01 ` [PATCH 06/13] net/intel: move iavf descriptor writing functions to common Bruce Richardson
2026-09-03 17:01 ` [PATCH 07/13] net/intel: use function callback for lldp Bruce Richardson
2026-09-03 17:01 ` [PATCH 08/13] net/ice: use common descriptor creation functions Bruce Richardson
2026-09-03 17:01 ` [PATCH 09/13] net/intel: move vector Tx paths to common Bruce Richardson
2026-09-03 17:03 ` [PATCH 10/13] net/ice: use common AVX Tx functions Bruce Richardson
2026-09-03 17:04 ` [PATCH 11/13] net/intel: add common vector Tx fns with context handling Bruce Richardson
2026-09-03 17:04 ` [PATCH 12/13] net/intel: improve Tx path selection logic Bruce Richardson
2026-09-03 17:04 ` Bruce Richardson [this message]
2026-09-04 7:10 ` [PATCH 00/13] Consolidate ice and iavf vector Tx paths David Marchand
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