From: Hawking Zhang <Hawking.Zhang@amd.com>
To: <amd-gfx@lists.freedesktop.org>, Likun Gao <Likun.Gao@amd.com>
Cc: Hawking Zhang <Hawking.Zhang@amd.com>
Subject: [PATCH 11/13] drm/amdgpu: Drop nbio v7_11_x support from nbif v6_3_1
Date: Sat, 5 Sep 2026 18:05:36 +0800 [thread overview]
Message-ID: <20260905100538.12877-12-Hawking.Zhang@amd.com> (raw)
In-Reply-To: <20260905100538.12877-1-Hawking.Zhang@amd.com>
nbio v7_11_4 and v7_11_5 now have dedicated implementations.
Select nbio v7_11_4 function and HDP flush tables during IP
discovery, and remove the version-specific register offsets
and doorbell handling from nbif v6_3_1.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 6 +-
drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c | 89 +++----------------
2 files changed, 19 insertions(+), 76 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 7710a8ed3d44..905332144836 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -45,6 +45,7 @@
#include "nbio_v7_4.h"
#include "nbio_v7_9.h"
#include "nbio_v7_11.h"
+#include "nbio_v7_11_4.h"
#include "nbio_v7_11_5.h"
#include "hdp_v4_0.h"
#include "vega10_ih.h"
@@ -3794,10 +3795,13 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg;
break;
case IP_VERSION(6, 3, 1):
- case IP_VERSION(7, 11, 4):
adev->nbio.funcs = &nbif_v6_3_1_funcs;
adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg;
break;
+ case IP_VERSION(7, 11, 4):
+ adev->nbio.funcs = &nbio_v7_11_4_funcs;
+ adev->nbio.hdp_flush_reg = &nbio_v7_11_4_hdp_flush_reg;
+ break;
case IP_VERSION(7, 11, 5):
adev->nbio.funcs = &nbio_v7_11_5_funcs;
adev->nbio.hdp_flush_reg = &nbio_v7_11_5_hdp_flush_reg;
diff --git a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c
index a74b17a47fd2..766cfbde55aa 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c
@@ -30,33 +30,6 @@
#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
#include <uapi/linux/kfd_ioctl.h>
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_nbif_4_10 0x4f0aeb
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_nbif_4_10_BASE_IDX 3
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1_nbif_4_10 0x4f0aec
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1_nbif_4_10_BASE_IDX 3
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10 0x4f0aed
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10_BASE_IDX 3
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1_nbif_4_10 0x4f0aee
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1_nbif_4_10_BASE_IDX 3
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10 0x4f0aef
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10_BASE_IDX 3
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1_nbif_4_10 0x4f0af0
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1_nbif_4_10_BASE_IDX 3
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_nbif_4_10 0x4f0af1
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_nbif_4_10_BASE_IDX 3
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1_nbif_4_10 0x4f0af2
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1_nbif_4_10_BASE_IDX 3
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10 0x4f0af3
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10_BASE_IDX 3
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1_nbif_4_10 0x4f0af4
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1_nbif_4_10_BASE_IDX 3
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10 0x4f0af5
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10_BASE_IDX 3
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1_nbif_4_10 0x4f0af6
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1_nbif_4_10_BASE_IDX 3
-#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_nbif_4_10 0x0021
-#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_nbif_4_10_BASE_IDX 2
-
static void nbif_v6_3_1_remap_hdp_registers(struct amdgpu_device *adev)
{
WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
@@ -69,10 +42,7 @@ static u32 nbif_v6_3_1_get_rev_id(struct amdgpu_device *adev)
{
u32 tmp;
- if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4))
- tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_nbif_4_10);
- else
- tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
+ tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
@@ -130,12 +100,8 @@ static void nbif_v6_3_1_sdma_doorbell_range(struct amdgpu_device *adev,
S2A_DOORBELL_PORT2_RANGE_SIZE,
0);
- if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4))
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10,
- doorbell_range);
- else
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- doorbell_range);
+ WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
+ doorbell_range);
}
}
@@ -146,8 +112,6 @@ static void nbif_v6_3_1_vcn_doorbell_range(struct amdgpu_device *adev,
u32 doorbell_range;
if (instance) {
- if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4))
- return;
doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL);
} else {
doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL);
@@ -180,15 +144,10 @@ static void nbif_v6_3_1_vcn_doorbell_range(struct amdgpu_device *adev,
S2A_DOORBELL_PORT4_RANGE_SIZE,
0);
- if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) {
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10,
- doorbell_range);
- } else {
- if (instance)
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range);
- else
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, doorbell_range);
- }
+ if (instance)
+ WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range);
+ else
+ WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, doorbell_range);
}
static void nbif_v6_3_1_vpe_doorbell_range(struct amdgpu_device *adev,
@@ -229,24 +188,14 @@ static void nbif_v6_3_1_vpe_doorbell_range(struct amdgpu_device *adev,
0);
}
- if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4) ||
- amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) {
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10, doorbell_range);
- } else {
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range);
- }
+ WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range);
}
static void nbif_v6_3_1_gc_doorbell_init(struct amdgpu_device *adev)
{
- if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) {
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_nbif_4_10, 0x30000007);
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_nbif_4_10, 0x3000000d);
- } else {
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, 0x30000007);
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL, 0x3000000d);
- }
+ WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, 0x30000007);
+ WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL, 0x3000000d);
}
static void nbif_v6_3_1_enable_doorbell_aperture(struct amdgpu_device *adev,
@@ -311,12 +260,8 @@ static void nbif_v6_3_1_ih_doorbell_range(struct amdgpu_device *adev,
S2A_DOORBELL_PORT1_RANGE_SIZE,
0);
- if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4))
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10,
- ih_doorbell_range);
- else
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- ih_doorbell_range);
+ WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
+ ih_doorbell_range);
}
static void nbif_v6_3_1_ih_control(struct amdgpu_device *adev)
@@ -371,18 +316,12 @@ static u32 nbif_v6_3_1_get_hdp_flush_done_offset(struct amdgpu_device *adev)
static u32 nbif_v6_3_1_get_pcie_index_offset(struct amdgpu_device *adev)
{
- if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4))
- return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX);
- else
- return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX);
+ return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX);
}
static u32 nbif_v6_3_1_get_pcie_data_offset(struct amdgpu_device *adev)
{
- if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4))
- return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA);
- else
- return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA);
+ return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA);
}
const struct nbio_hdp_flush_reg nbif_v6_3_1_hdp_flush_reg = {
--
2.17.1
next prev parent reply other threads:[~2026-09-05 10:06 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-05 10:05 [PATCH 00/13] drm/amdgpu: Simplify nbio doorbell range programming Hawking Zhang
2026-09-05 10:05 ` [PATCH 01/13] drm/amdgpu: Add common NBIO doorbell entry helpers Hawking Zhang
2026-09-05 10:05 ` [PATCH 02/13] drm/amdgpu: Add nbio v6_3_2 doorbell layout Hawking Zhang
2026-09-05 10:05 ` [PATCH 03/13] drm/amdgpu: Use common doorbell helpers in nbio v6_3_2 Hawking Zhang
2026-09-05 10:05 ` [PATCH 04/13] drm/amdgpu: Add nbio v4_3 doorbell layout Hawking Zhang
2026-09-05 10:05 ` [PATCH 05/13] drm/amdgpu: Use common doorbell helpers in nbio v4_3 Hawking Zhang
2026-09-05 10:05 ` [PATCH 06/13] drm/amdgpu: Support doorbell range programming through smn Hawking Zhang
2026-09-05 10:05 ` [PATCH 07/13] drm/amdgpu: Use common doorbell helpers in nbio v7_9 Hawking Zhang
2026-09-05 10:05 ` [PATCH 08/13] drm/amdgpu: Use common doorbell helpers in nbio v7_11_5 Hawking Zhang
2026-09-05 10:05 ` [PATCH 09/13] drm/amdgpu: Add nbif v4_10_0 ip headers Hawking Zhang
2026-09-05 10:05 ` [PATCH 10/13] drm/amdgpu: Add nbio v7_11_4 support Hawking Zhang
2026-09-05 10:05 ` Hawking Zhang [this message]
2026-09-05 10:05 ` [PATCH 12/13] drm/amdgpu: Use common doorbell helpers in nbio v7_11_4 Hawking Zhang
2026-09-05 10:05 ` [PATCH 13/13] drm/amdgpu: Use common doorbell helpers in nbif v6_3_1 Hawking Zhang
2026-09-07 3:56 ` Gao, Likun
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