From: Hawking Zhang <Hawking.Zhang@amd.com>
To: <amd-gfx@lists.freedesktop.org>, Likun Gao <Likun.Gao@amd.com>
Cc: Hawking Zhang <Hawking.Zhang@amd.com>
Subject: [PATCH 02/13] drm/amdgpu: Add nbio v6_3_2 doorbell layout
Date: Sat, 5 Sep 2026 18:05:27 +0800 [thread overview]
Message-ID: <20260905100538.12877-3-Hawking.Zhang@amd.com> (raw)
In-Reply-To: <20260905100538.12877-1-Hawking.Zhang@amd.com>
Describe nbio v6_3_2 doorbell_entry_ctrl and
doorbell_entry_ctrl1 field layout from IP register
header and initialize gc, ih, vcn, and sdma
port and register assignments.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c | 100 +++++++++++++++++++++++
1 file changed, 100 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c
index a40a13ca1011..4f5a5f310905 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c
@@ -26,6 +26,57 @@
#include "amdgpu.h"
#include "nbio_v6_3_2.h"
+static const struct amdgpu_nbio_doorbell_layout
+nbio_v6_3_2_doorbell_layout = {
+ .ctrl = {
+ .enable = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_ENABLE),
+ .awid = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_AWID),
+ .fence_enable = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_FENCE_ENABLE),
+ .range_offset = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_RANGE_OFFSET),
+ .range_size = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_RANGE_SIZE),
+ .disable_64bit = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS),
+ .deduct_range_offset = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET),
+ .drop = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_DROP_EN),
+ .awaddr_31_28 = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE),
+ },
+ .ctrl1 = {
+ .target_port_type = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1,
+ S2A_DOORBELL_PORT0_TARGET_PORT_TYPE),
+ .target_die_id = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1,
+ S2A_DOORBELL_PORT0_TARGET_DIEID),
+ .target_port_id = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1,
+ S2A_DOORBELL_PORT0_TARGET_PORT_ID),
+ .override_poison_data = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1,
+ S2A_DOORBELL_PORT0_OVERRIDE_POISON_DATA),
+ .disable_4k_page_decode = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1,
+ S2A_DOORBELL_PORT0_4K_PAGE_DECODE_DISABLE),
+ },
+ .has_ctrl1 = true,
+};
+
static u32 nbio_v6_3_2_get_pcie_index_offset(struct amdgpu_device *adev)
{
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2);
@@ -71,8 +122,57 @@ static void nbio_v6_3_2_mc_access_enable(struct amdgpu_device *adev,
WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
}
+static void nbio_v6_3_2_init_doorbell_entry_registers(
+ struct amdgpu_device *adev)
+{
+ struct amdgpu_nbio_doorbell_entries *entries;
+ u32 ctrl_base, ctrl1_base;
+ u32 i;
+
+ memset(adev->nbio.doorbell_entries, 0,
+ sizeof(adev->nbio.doorbell_entries));
+ adev->nbio.doorbell_layout = &nbio_v6_3_2_doorbell_layout;
+
+ ctrl_base = SOC15_REG_OFFSET(
+ NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL);
+ ctrl1_base = SOC15_REG_OFFSET(
+ NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1);
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_CP];
+ entries->num_entries = 1;
+ entries->entry[0].port = 0;
+ entries->entry[0].ctrl_reg = ctrl_base;
+ entries->entry[0].ctrl1_reg = ctrl1_base;
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_IH];
+ entries->num_entries = 1;
+ entries->entry[0].port = 1;
+ entries->entry[0].ctrl_reg = ctrl_base + 2;
+ entries->entry[0].ctrl1_reg = ctrl1_base + 2;
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_VCN];
+ entries->num_entries = 4;
+ for (i = 0; i < entries->num_entries; i++) {
+ entries->entry[i].port = i + 2;
+ entries->entry[i].ctrl_reg = ctrl_base + (i + 2) * 2;
+ entries->entry[i].ctrl1_reg = ctrl1_base + (i + 2) * 2;
+ }
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_SDMA];
+ entries->num_entries = 1;
+ entries->entry[0].port = 6;
+ entries->entry[0].ctrl_reg = ctrl_base + 6 * 2;
+ entries->entry[0].ctrl1_reg = ctrl1_base + 6 * 2;
+}
+
static void nbio_v6_3_2_init_registers(struct amdgpu_device *adev)
{
+ nbio_v6_3_2_init_doorbell_entry_registers(adev);
+
WREG32_SOC15(NBIO, 0, regXCD_DOORBELL_FENCE_1,
(0xff & ~(adev->gfx.xcc_mask)) <<
XCD_DOORBELL_FENCE_1__XCD_0_DOORBELL_DISABLE__SHIFT);
--
2.17.1
next prev parent reply other threads:[~2026-09-05 10:06 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-05 10:05 [PATCH 00/13] drm/amdgpu: Simplify nbio doorbell range programming Hawking Zhang
2026-09-05 10:05 ` [PATCH 01/13] drm/amdgpu: Add common NBIO doorbell entry helpers Hawking Zhang
2026-09-05 10:05 ` Hawking Zhang [this message]
2026-09-05 10:05 ` [PATCH 03/13] drm/amdgpu: Use common doorbell helpers in nbio v6_3_2 Hawking Zhang
2026-09-05 10:05 ` [PATCH 04/13] drm/amdgpu: Add nbio v4_3 doorbell layout Hawking Zhang
2026-09-05 10:05 ` [PATCH 05/13] drm/amdgpu: Use common doorbell helpers in nbio v4_3 Hawking Zhang
2026-09-05 10:05 ` [PATCH 06/13] drm/amdgpu: Support doorbell range programming through smn Hawking Zhang
2026-09-05 10:05 ` [PATCH 07/13] drm/amdgpu: Use common doorbell helpers in nbio v7_9 Hawking Zhang
2026-09-05 10:05 ` [PATCH 08/13] drm/amdgpu: Use common doorbell helpers in nbio v7_11_5 Hawking Zhang
2026-09-05 10:05 ` [PATCH 09/13] drm/amdgpu: Add nbif v4_10_0 ip headers Hawking Zhang
2026-09-05 10:05 ` [PATCH 10/13] drm/amdgpu: Add nbio v7_11_4 support Hawking Zhang
2026-09-05 10:05 ` [PATCH 11/13] drm/amdgpu: Drop nbio v7_11_x support from nbif v6_3_1 Hawking Zhang
2026-09-05 10:05 ` [PATCH 12/13] drm/amdgpu: Use common doorbell helpers in nbio v7_11_4 Hawking Zhang
2026-09-05 10:05 ` [PATCH 13/13] drm/amdgpu: Use common doorbell helpers in nbif v6_3_1 Hawking Zhang
2026-09-07 3:56 ` Gao, Likun
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