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From: Brian Cain <brian.cain@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: "Pierrick Bouvier" <pierrick.bouvier@oss.qualcomm.com>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Brian Cain" <brian.cain@oss.qualcomm.com>,
	sid.manning@oss.qualcomm.com
Subject: [PATCH 02/17] tests/tcg/hexagon: fix undefined signed left shift in brev.c
Date: Sat,  5 Sep 2026 11:09:34 -0700	[thread overview]
Message-ID: <20260905180949.1852673-3-brian.cain@oss.qualcomm.com> (raw)
In-Reply-To: <20260905180949.1852673-1-brian.cain@oss.qualcomm.com>

Cast to uint32_t before left-shifting in sext8() to avoid undefined
behavior when shifting a negative value. The subsequent arithmetic
right shift on the int32_t cast correctly sign-extends the result.
Found with UBSan.

Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
 tests/tcg/hexagon/brev.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/tcg/hexagon/brev.c b/tests/tcg/hexagon/brev.c
index 6c7b1340849..1473e309ee0 100644
--- a/tests/tcg/hexagon/brev.c
+++ b/tests/tcg/hexagon/brev.c
@@ -106,7 +106,7 @@ uint32_t bitreverse(uint32_t x)
 
 int32_t sext8(int32_t x)
 {
-    return (x << 24) >> 24;
+    return (int32_t)((uint32_t)x << 24) >> 24;
 }
 
 #define TEST_BREV_LOAD(SZ, TYPE, BUF, SHIFT, EXP) \
-- 
2.34.1


  parent reply	other threads:[~2026-09-05 18:11 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-05 18:09 [PATCH 00/17] hexagon: TCG test coverage + ubsan fixes Brian Cain
2026-09-05 18:09 ` [PATCH 01/17] tests/tcg/hexagon: fix undefined signed left shift in circ.c Brian Cain
2026-09-08 15:54   ` Sid Manning
2026-09-05 18:09 ` Brian Cain [this message]
2026-09-09 14:43   ` [PATCH 02/17] tests/tcg/hexagon: fix undefined signed left shift in brev.c Sid Manning
2026-09-05 18:09 ` [PATCH 03/17] tests/tcg/hexagon: fix undefined signed integer overflow in hvx_misc Brian Cain
2026-09-09 14:50   ` Sid Manning
2026-09-05 18:09 ` [PATCH 04/17] tests/tcg/hexagon: fix undefined integer overflow in v69_hvx.c Brian Cain
2026-09-09 14:51   ` Sid Manning
2026-09-05 18:09 ` [PATCH 05/17] tests/tcg/multiarch: suppress UBSan for float-to-int conversions Brian Cain
2026-09-14 19:43   ` Pierrick Bouvier
2026-09-05 18:09 ` [PATCH 06/17] tests/tcg/hexagon: add FP classification, conversion, and fixup tests Brian Cain
2026-09-14 19:43   ` Pierrick Bouvier
2026-09-05 18:09 ` [PATCH 07/17] tests/tcg/hexagon: add bit interleave and convergent rounding tests Brian Cain
2026-09-10 17:54   ` Sid Manning
2026-09-05 18:09 ` [PATCH 08/17] tests/tcg/hexagon: add cond call, tstbit-jump, and endloop01 tests Brian Cain
2026-09-14 19:44   ` Pierrick Bouvier
2026-09-05 18:09 ` [PATCH 09/17] tests/tcg/hexagon: add dczeroa cache line zero test Brian Cain
2026-09-10 18:14   ` Sid Manning
2026-09-05 18:09 ` [PATCH 10/17] tests/tcg/hexagon: add HVX vwhist tests Brian Cain
2026-09-14 21:21   ` Pierrick Bouvier
2026-09-05 18:09 ` [PATCH 11/17] tests/tcg/hexagon: add sfrecipa edge case tests Brian Cain
2026-09-14 21:22   ` Pierrick Bouvier
2026-09-05 18:09 ` [PATCH 12/17] tests/tcg/hexagon: add dfmpyhh Brian Cain
2026-09-14 21:22   ` Pierrick Bouvier
2026-09-05 18:09 ` [PATCH 13/17] tests/tcg/hexagon: add unconditional store-immediate tests Brian Cain
2026-09-14 21:23   ` Pierrick Bouvier
2026-09-05 18:09 ` [PATCH 14/17] tests/tcg/hexagon: add predicate register transfer test Brian Cain
2026-09-14 21:23   ` Pierrick Bouvier
2026-09-05 18:09 ` [PATCH 15/17] tests/tcg/hexagon: add rounding conv, sffma:lib, and sfinvsqrta Brian Cain
2026-09-14 21:23   ` Pierrick Bouvier
2026-09-05 18:09 ` [PATCH 16/17] tests/tcg/hexagon: add scalar+HVX and masked store tests Brian Cain
2026-09-14 21:24   ` Pierrick Bouvier
2026-09-05 18:09 ` [PATCH 17/17] tests/tcg/hexagon: add decbin MPS test case Brian Cain
2026-09-14 21:24   ` Pierrick Bouvier

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